xlnx-versal.h (7116B)
1 /* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #ifndef XLNX_VERSAL_H 13 #define XLNX_VERSAL_H 14 15 #include "hw/sysbus.h" 16 #include "hw/arm/boot.h" 17 #include "hw/cpu/cluster.h" 18 #include "hw/or-irq.h" 19 #include "hw/sd/sdhci.h" 20 #include "hw/intc/arm_gicv3.h" 21 #include "hw/char/pl011.h" 22 #include "hw/dma/xlnx-zdma.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/rtc/xlnx-zynqmp-rtc.h" 25 #include "qom/object.h" 26 #include "hw/usb/xlnx-usb-subsystem.h" 27 #include "hw/misc/xlnx-versal-xramc.h" 28 #include "hw/nvram/xlnx-bbram.h" 29 #include "hw/nvram/xlnx-versal-efuse.h" 30 #include "hw/ssi/xlnx-versal-ospi.h" 31 #include "hw/dma/xlnx_csu_dma.h" 32 #include "hw/misc/xlnx-versal-crl.h" 33 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 34 35 #define TYPE_XLNX_VERSAL "xlnx-versal" 36 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 37 38 #define XLNX_VERSAL_NR_ACPUS 2 39 #define XLNX_VERSAL_NR_RCPUS 2 40 #define XLNX_VERSAL_NR_UARTS 2 41 #define XLNX_VERSAL_NR_GEMS 2 42 #define XLNX_VERSAL_NR_ADMAS 8 43 #define XLNX_VERSAL_NR_SDS 2 44 #define XLNX_VERSAL_NR_XRAM 4 45 #define XLNX_VERSAL_NR_IRQS 192 46 47 struct Versal { 48 /*< private >*/ 49 SysBusDevice parent_obj; 50 51 /*< public >*/ 52 struct { 53 struct { 54 MemoryRegion mr; 55 CPUClusterState cluster; 56 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 57 GICv3State gic; 58 } apu; 59 } fpd; 60 61 MemoryRegion mr_ps; 62 63 struct { 64 /* 4 ranges to access DDR. */ 65 MemoryRegion mr_ddr_ranges[4]; 66 } noc; 67 68 struct { 69 MemoryRegion mr_ocm; 70 71 struct { 72 PL011State uart[XLNX_VERSAL_NR_UARTS]; 73 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 74 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 75 VersalUsb2 usb; 76 } iou; 77 78 /* Real-time Processing Unit. */ 79 struct { 80 MemoryRegion mr; 81 MemoryRegion mr_ps_alias; 82 83 CPUClusterState cluster; 84 ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; 85 } rpu; 86 87 struct { 88 qemu_or_irq irq_orgate; 89 XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 90 } xram; 91 92 XlnxVersalCRL crl; 93 } lpd; 94 95 /* The Platform Management Controller subsystem. */ 96 struct { 97 struct { 98 SDHCIState sd[XLNX_VERSAL_NR_SDS]; 99 XlnxVersalPmcIouSlcr slcr; 100 101 struct { 102 XlnxVersalOspi ospi; 103 XlnxCSUDMA dma_src; 104 XlnxCSUDMA dma_dst; 105 MemoryRegion linear_mr; 106 qemu_or_irq irq_orgate; 107 } ospi; 108 } iou; 109 110 XlnxZynqMPRTC rtc; 111 XlnxBBRam bbram; 112 XlnxEFuse efuse; 113 XlnxVersalEFuseCtrl efuse_ctrl; 114 XlnxVersalEFuseCache efuse_cache; 115 116 qemu_or_irq apb_irq_orgate; 117 } pmc; 118 119 struct { 120 MemoryRegion *mr_ddr; 121 } cfg; 122 }; 123 124 /* Memory-map and IRQ definitions. Copied a subset from 125 * auto-generated files. */ 126 127 #define VERSAL_GIC_MAINT_IRQ 9 128 #define VERSAL_TIMER_VIRT_IRQ 11 129 #define VERSAL_TIMER_S_EL1_IRQ 13 130 #define VERSAL_TIMER_NS_EL1_IRQ 14 131 #define VERSAL_TIMER_NS_EL2_IRQ 10 132 133 #define VERSAL_CRL_IRQ 10 134 #define VERSAL_UART0_IRQ_0 18 135 #define VERSAL_UART1_IRQ_0 19 136 #define VERSAL_USB0_IRQ_0 22 137 #define VERSAL_GEM0_IRQ_0 56 138 #define VERSAL_GEM0_WAKE_IRQ_0 57 139 #define VERSAL_GEM1_IRQ_0 58 140 #define VERSAL_GEM1_WAKE_IRQ_0 59 141 #define VERSAL_ADMA_IRQ_0 60 142 #define VERSAL_XRAM_IRQ_0 79 143 #define VERSAL_PMC_APB_IRQ 121 144 #define VERSAL_OSPI_IRQ 124 145 #define VERSAL_SD0_IRQ_0 126 146 #define VERSAL_EFUSE_IRQ 139 147 #define VERSAL_RTC_ALARM_IRQ 142 148 #define VERSAL_RTC_SECONDS_IRQ 143 149 150 /* Architecturally reserved IRQs suitable for virtualization. */ 151 #define VERSAL_RSVD_IRQ_FIRST 111 152 #define VERSAL_RSVD_IRQ_LAST 118 153 154 #define MM_TOP_RSVD 0xa0000000U 155 #define MM_TOP_RSVD_SIZE 0x4000000 156 #define MM_GIC_APU_DIST_MAIN 0xf9000000U 157 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 158 #define MM_GIC_APU_REDIST_0 0xf9080000U 159 #define MM_GIC_APU_REDIST_0_SIZE 0x80000 160 161 #define MM_UART0 0xff000000U 162 #define MM_UART0_SIZE 0x10000 163 #define MM_UART1 0xff010000U 164 #define MM_UART1_SIZE 0x10000 165 166 #define MM_GEM0 0xff0c0000U 167 #define MM_GEM0_SIZE 0x10000 168 #define MM_GEM1 0xff0d0000U 169 #define MM_GEM1_SIZE 0x10000 170 171 #define MM_ADMA_CH0 0xffa80000U 172 #define MM_ADMA_CH0_SIZE 0x10000 173 174 #define MM_OCM 0xfffc0000U 175 #define MM_OCM_SIZE 0x40000 176 177 #define MM_XRAM 0xfe800000 178 #define MM_XRAMC 0xff8e0000 179 #define MM_XRAMC_SIZE 0x10000 180 181 #define MM_USB2_CTRL_REGS 0xFF9D0000 182 #define MM_USB2_CTRL_REGS_SIZE 0x10000 183 184 #define MM_USB_0 0xFE200000 185 #define MM_USB_0_SIZE 0x10000 186 187 #define MM_TOP_DDR 0x0 188 #define MM_TOP_DDR_SIZE 0x80000000U 189 #define MM_TOP_DDR_2 0x800000000ULL 190 #define MM_TOP_DDR_2_SIZE 0x800000000ULL 191 #define MM_TOP_DDR_3 0xc000000000ULL 192 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 193 #define MM_TOP_DDR_4 0x10000000000ULL 194 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 195 196 #define MM_PSM_START 0xffc80000U 197 #define MM_PSM_END 0xffcf0000U 198 199 #define MM_CRL 0xff5e0000U 200 #define MM_CRL_SIZE 0x300000 201 #define MM_IOU_SCNTR 0xff130000U 202 #define MM_IOU_SCNTR_SIZE 0x10000 203 #define MM_IOU_SCNTRS 0xff140000U 204 #define MM_IOU_SCNTRS_SIZE 0x10000 205 #define MM_FPD_CRF 0xfd1a0000U 206 #define MM_FPD_CRF_SIZE 0x140000 207 #define MM_FPD_FPD_APU 0xfd5c0000 208 #define MM_FPD_FPD_APU_SIZE 0x100 209 210 #define MM_PMC_PMC_IOU_SLCR 0xf1060000 211 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 212 213 #define MM_PMC_OSPI 0xf1010000 214 #define MM_PMC_OSPI_SIZE 0x10000 215 216 #define MM_PMC_OSPI_DAC 0xc0000000 217 #define MM_PMC_OSPI_DAC_SIZE 0x20000000 218 219 #define MM_PMC_OSPI_DMA_DST 0xf1011800 220 #define MM_PMC_OSPI_DMA_SRC 0xf1011000 221 222 #define MM_PMC_SD0 0xf1040000U 223 #define MM_PMC_SD0_SIZE 0x10000 224 #define MM_PMC_BBRAM_CTRL 0xf11f0000 225 #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 226 #define MM_PMC_EFUSE_CTRL 0xf1240000 227 #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 228 #define MM_PMC_EFUSE_CACHE 0xf1250000 229 #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 230 231 #define MM_PMC_CRP 0xf1260000U 232 #define MM_PMC_CRP_SIZE 0x10000 233 #define MM_PMC_RTC 0xf12a0000 234 #define MM_PMC_RTC_SIZE 0x10000 235 #endif