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exynos4210.h (4580B)

      1 /*
      2  *  Samsung exynos4210 SoC emulation
      3  *
      4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
      5  *    Maksim Kozlov <m.kozlov@samsung.com>
      6  *    Evgeny Voevodin <e.voevodin@samsung.com>
      7  *    Igor Mitsyanko <i.mitsyanko@samsung.com>
      8  *
      9  *
     10  *  This program is free software; you can redistribute it and/or modify it
     11  *  under the terms of the GNU General Public License as published by the
     12  *  Free Software Foundation; either version 2 of the License, or
     13  *  (at your option) any later version.
     14  *
     15  *  This program is distributed in the hope that it will be useful, but WITHOUT
     16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     17  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
     18  *  for more details.
     19  *
     20  *  You should have received a copy of the GNU General Public License along
     21  *  with this program; if not, see <http://www.gnu.org/licenses/>.
     22  */
     23 
     24 #ifndef EXYNOS4210_H
     25 #define EXYNOS4210_H
     26 
     27 #include "hw/or-irq.h"
     28 #include "hw/sysbus.h"
     29 #include "hw/cpu/a9mpcore.h"
     30 #include "hw/intc/exynos4210_gic.h"
     31 #include "hw/intc/exynos4210_combiner.h"
     32 #include "hw/core/split-irq.h"
     33 #include "target/arm/cpu-qom.h"
     34 #include "qom/object.h"
     35 
     36 #define EXYNOS4210_NCPUS                    2
     37 
     38 #define EXYNOS4210_DRAM0_BASE_ADDR          0x40000000
     39 #define EXYNOS4210_DRAM1_BASE_ADDR          0xa0000000
     40 #define EXYNOS4210_DRAM_MAX_SIZE            0x60000000  /* 1.5 GB */
     41 
     42 #define EXYNOS4210_IROM_BASE_ADDR           0x00000000
     43 #define EXYNOS4210_IROM_SIZE                0x00010000  /* 64 KB */
     44 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR    0x02000000
     45 #define EXYNOS4210_IROM_MIRROR_SIZE         0x00010000  /* 64 KB */
     46 
     47 #define EXYNOS4210_IRAM_BASE_ADDR           0x02020000
     48 #define EXYNOS4210_IRAM_SIZE                0x00020000  /* 128 KB */
     49 
     50 /* Secondary CPU startup code is in IROM memory */
     51 #define EXYNOS4210_SMP_BOOT_ADDR            EXYNOS4210_IROM_BASE_ADDR
     52 #define EXYNOS4210_SMP_BOOT_SIZE            0x1000
     53 #define EXYNOS4210_BASE_BOOT_ADDR           EXYNOS4210_DRAM0_BASE_ADDR
     54 /* Secondary CPU polling address to get loader start from */
     55 #define EXYNOS4210_SECOND_CPU_BOOTREG       0x10020814
     56 
     57 #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR    0x10500000
     58 #define EXYNOS4210_L2X0_BASE_ADDR           0x10502000
     59 
     60 /*
     61  * exynos4210 IRQ subsystem stub definitions.
     62  */
     63 #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
     64 
     65 #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ  64
     66 #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ  16
     67 #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ   \
     68     (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
     69 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
     70     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
     71 
     72 #define EXYNOS4210_I2C_NUMBER               9
     73 
     74 #define EXYNOS4210_NUM_DMA      3
     75 
     76 /*
     77  * We need one splitter for every external combiner input, plus
     78  * one for every non-zero entry in combiner_grp_to_gic_id[],
     79  * minus one for every external combiner ID in second or later
     80  * places in a combinermap[] line.
     81  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
     82  */
     83 #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
     84 
     85 struct Exynos4210State {
     86     /*< private >*/
     87     SysBusDevice parent_obj;
     88     /*< public >*/
     89     ARMCPU *cpu[EXYNOS4210_NCPUS];
     90     qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     91 
     92     MemoryRegion chipid_mem;
     93     MemoryRegion iram_mem;
     94     MemoryRegion irom_mem;
     95     MemoryRegion irom_alias_mem;
     96     MemoryRegion boot_secondary;
     97     MemoryRegion bootreg_mem;
     98     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
     99     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
    100     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
    101     A9MPPrivState a9mpcore;
    102     Exynos4210GicState ext_gic;
    103     Exynos4210CombinerState int_combiner;
    104     Exynos4210CombinerState ext_combiner;
    105     SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
    106 };
    107 
    108 #define TYPE_EXYNOS4210_SOC "exynos4210"
    109 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
    110 
    111 void exynos4210_write_secondary(ARMCPU *cpu,
    112         const struct arm_boot_info *info);
    113 
    114 /* Get IRQ number from exynos4210 IRQ subsystem stub.
    115  * To identify IRQ source use internal combiner group and bit number
    116  *  grp - group number
    117  *  bit - bit number inside group */
    118 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
    119 
    120 /*
    121  * exynos4210 UART
    122  */
    123 DeviceState *exynos4210_uart_create(hwaddr addr,
    124                                     int fifo_size,
    125                                     int channel,
    126                                     Chardev *chr,
    127                                     qemu_irq irq);
    128 
    129 #endif /* EXYNOS4210_H */