aspeed_soc.h (4949B)
1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 #include "hw/misc/aspeed_i3c.h" 26 #include "hw/ssi/aspeed_smc.h" 27 #include "hw/misc/aspeed_hace.h" 28 #include "hw/misc/aspeed_sbc.h" 29 #include "hw/watchdog/wdt_aspeed.h" 30 #include "hw/net/ftgmac100.h" 31 #include "target/arm/cpu.h" 32 #include "hw/gpio/aspeed_gpio.h" 33 #include "hw/sd/aspeed_sdhci.h" 34 #include "hw/usb/hcd-ehci.h" 35 #include "qom/object.h" 36 #include "hw/misc/aspeed_lpc.h" 37 #include "hw/misc/unimp.h" 38 #include "hw/misc/aspeed_peci.h" 39 #include "hw/char/serial.h" 40 41 #define ASPEED_SPIS_NUM 2 42 #define ASPEED_EHCIS_NUM 2 43 #define ASPEED_WDTS_NUM 4 44 #define ASPEED_CPUS_NUM 2 45 #define ASPEED_MACS_NUM 4 46 #define ASPEED_UARTS_NUM 13 47 48 struct AspeedSoCState { 49 /*< private >*/ 50 DeviceState parent; 51 52 /*< public >*/ 53 ARMCPU cpu[ASPEED_CPUS_NUM]; 54 A15MPPrivState a7mpcore; 55 ARMv7MState armv7m; 56 MemoryRegion *memory; 57 MemoryRegion *dram_mr; 58 MemoryRegion dram_container; 59 MemoryRegion sram; 60 AspeedVICState vic; 61 AspeedRtcState rtc; 62 AspeedTimerCtrlState timerctrl; 63 AspeedI2CState i2c; 64 AspeedI3CState i3c; 65 AspeedSCUState scu; 66 AspeedHACEState hace; 67 AspeedXDMAState xdma; 68 AspeedADCState adc; 69 AspeedSMCState fmc; 70 AspeedSMCState spi[ASPEED_SPIS_NUM]; 71 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 72 AspeedSBCState sbc; 73 UnimplementedDeviceState sbc_unimplemented; 74 AspeedSDMCState sdmc; 75 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 76 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 77 AspeedMiiState mii[ASPEED_MACS_NUM]; 78 AspeedGPIOState gpio; 79 AspeedGPIOState gpio_1_8v; 80 AspeedSDHCIState sdhci; 81 AspeedSDHCIState emmc; 82 AspeedLPCState lpc; 83 AspeedPECIState peci; 84 SerialMM uart[ASPEED_UARTS_NUM]; 85 Clock *sysclk; 86 UnimplementedDeviceState iomem; 87 UnimplementedDeviceState video; 88 UnimplementedDeviceState emmc_boot_controller; 89 UnimplementedDeviceState dpmcu; 90 }; 91 92 #define TYPE_ASPEED_SOC "aspeed-soc" 93 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 94 95 struct AspeedSoCClass { 96 DeviceClass parent_class; 97 98 const char *name; 99 const char *cpu_type; 100 uint32_t silicon_rev; 101 uint64_t sram_size; 102 int spis_num; 103 int ehcis_num; 104 int wdts_num; 105 int macs_num; 106 int uarts_num; 107 const int *irqmap; 108 const hwaddr *memmap; 109 uint32_t num_cpus; 110 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 111 }; 112 113 114 enum { 115 ASPEED_DEV_IOMEM, 116 ASPEED_DEV_UART1, 117 ASPEED_DEV_UART2, 118 ASPEED_DEV_UART3, 119 ASPEED_DEV_UART4, 120 ASPEED_DEV_UART5, 121 ASPEED_DEV_UART6, 122 ASPEED_DEV_UART7, 123 ASPEED_DEV_UART8, 124 ASPEED_DEV_UART9, 125 ASPEED_DEV_UART10, 126 ASPEED_DEV_UART11, 127 ASPEED_DEV_UART12, 128 ASPEED_DEV_UART13, 129 ASPEED_DEV_VUART, 130 ASPEED_DEV_FMC, 131 ASPEED_DEV_SPI1, 132 ASPEED_DEV_SPI2, 133 ASPEED_DEV_EHCI1, 134 ASPEED_DEV_EHCI2, 135 ASPEED_DEV_VIC, 136 ASPEED_DEV_SDMC, 137 ASPEED_DEV_SCU, 138 ASPEED_DEV_ADC, 139 ASPEED_DEV_SBC, 140 ASPEED_DEV_EMMC_BC, 141 ASPEED_DEV_VIDEO, 142 ASPEED_DEV_SRAM, 143 ASPEED_DEV_SDHCI, 144 ASPEED_DEV_GPIO, 145 ASPEED_DEV_GPIO_1_8V, 146 ASPEED_DEV_RTC, 147 ASPEED_DEV_TIMER1, 148 ASPEED_DEV_TIMER2, 149 ASPEED_DEV_TIMER3, 150 ASPEED_DEV_TIMER4, 151 ASPEED_DEV_TIMER5, 152 ASPEED_DEV_TIMER6, 153 ASPEED_DEV_TIMER7, 154 ASPEED_DEV_TIMER8, 155 ASPEED_DEV_WDT, 156 ASPEED_DEV_PWM, 157 ASPEED_DEV_LPC, 158 ASPEED_DEV_IBT, 159 ASPEED_DEV_I2C, 160 ASPEED_DEV_PECI, 161 ASPEED_DEV_ETH1, 162 ASPEED_DEV_ETH2, 163 ASPEED_DEV_ETH3, 164 ASPEED_DEV_ETH4, 165 ASPEED_DEV_MII1, 166 ASPEED_DEV_MII2, 167 ASPEED_DEV_MII3, 168 ASPEED_DEV_MII4, 169 ASPEED_DEV_SDRAM, 170 ASPEED_DEV_XDMA, 171 ASPEED_DEV_EMMC, 172 ASPEED_DEV_KCS, 173 ASPEED_DEV_HACE, 174 ASPEED_DEV_DPMCU, 175 ASPEED_DEV_DP, 176 ASPEED_DEV_I3C, 177 }; 178 179 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 180 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 181 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 182 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 183 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 184 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 185 const char *name, hwaddr addr, 186 uint64_t size); 187 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 188 unsigned int count, int unit0); 189 190 #endif /* ASPEED_SOC_H */