cpu-common.h (5614B)
1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 /** 11 * vaddr: 12 * Type wide enough to contain any #target_ulong virtual address. 13 */ 14 typedef uint64_t vaddr; 15 #define VADDR_PRId PRId64 16 #define VADDR_PRIu PRIu64 17 #define VADDR_PRIo PRIo64 18 #define VADDR_PRIx PRIx64 19 #define VADDR_PRIX PRIX64 20 #define VADDR_MAX UINT64_MAX 21 22 void cpu_exec_init_all(void); 23 void cpu_exec_step_atomic(CPUState *cpu); 24 25 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 26 * when intptr_t is 32-bit and we are aligning a long long. 27 */ 28 extern uintptr_t qemu_host_page_size; 29 extern intptr_t qemu_host_page_mask; 30 31 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 32 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 33 34 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 35 void qemu_init_cpu_list(void); 36 void cpu_list_lock(void); 37 void cpu_list_unlock(void); 38 unsigned int cpu_list_generation_id_get(void); 39 40 void tcg_flush_softmmu_tlb(CPUState *cs); 41 void tcg_flush_jmp_cache(CPUState *cs); 42 43 void tcg_iommu_init_notifier_list(CPUState *cpu); 44 void tcg_iommu_free_notifier_list(CPUState *cpu); 45 46 #if !defined(CONFIG_USER_ONLY) 47 48 enum device_endian { 49 DEVICE_NATIVE_ENDIAN, 50 DEVICE_BIG_ENDIAN, 51 DEVICE_LITTLE_ENDIAN, 52 }; 53 54 #if HOST_BIG_ENDIAN 55 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 56 #else 57 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 58 #endif 59 60 /* address in the RAM (different from a physical address) */ 61 #if defined(CONFIG_XEN_BACKEND) 62 typedef uint64_t ram_addr_t; 63 # define RAM_ADDR_MAX UINT64_MAX 64 # define RAM_ADDR_FMT "%" PRIx64 65 #else 66 typedef uintptr_t ram_addr_t; 67 # define RAM_ADDR_MAX UINTPTR_MAX 68 # define RAM_ADDR_FMT "%" PRIxPTR 69 #endif 70 71 /* memory API */ 72 73 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 74 /* This should not be used by devices. */ 75 ram_addr_t qemu_ram_addr_from_host(void *ptr); 76 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 77 RAMBlock *qemu_ram_block_by_name(const char *name); 78 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 79 ram_addr_t *offset); 80 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 81 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 82 void qemu_ram_unset_idstr(RAMBlock *block); 83 const char *qemu_ram_get_idstr(RAMBlock *rb); 84 void *qemu_ram_get_host_addr(RAMBlock *rb); 85 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 86 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 87 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 88 bool qemu_ram_is_shared(RAMBlock *rb); 89 bool qemu_ram_is_noreserve(RAMBlock *rb); 90 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 91 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 92 bool qemu_ram_is_migratable(RAMBlock *rb); 93 void qemu_ram_set_migratable(RAMBlock *rb); 94 void qemu_ram_unset_migratable(RAMBlock *rb); 95 int qemu_ram_get_fd(RAMBlock *rb); 96 97 size_t qemu_ram_pagesize(RAMBlock *block); 98 size_t qemu_ram_pagesize_largest(void); 99 100 /** 101 * cpu_address_space_init: 102 * @cpu: CPU to add this address space to 103 * @asidx: integer index of this address space 104 * @prefix: prefix to be used as name of address space 105 * @mr: the root memory region of address space 106 * 107 * Add the specified address space to the CPU's cpu_ases list. 108 * The address space added with @asidx 0 is the one used for the 109 * convenience pointer cpu->as. 110 * The target-specific code which registers ASes is responsible 111 * for defining what semantics address space 0, 1, 2, etc have. 112 * 113 * Before the first call to this function, the caller must set 114 * cpu->num_ases to the total number of address spaces it needs 115 * to support. 116 * 117 * Note that with KVM only one address space is supported. 118 */ 119 void cpu_address_space_init(CPUState *cpu, int asidx, 120 const char *prefix, MemoryRegion *mr); 121 122 void cpu_physical_memory_rw(hwaddr addr, void *buf, 123 hwaddr len, bool is_write); 124 static inline void cpu_physical_memory_read(hwaddr addr, 125 void *buf, hwaddr len) 126 { 127 cpu_physical_memory_rw(addr, buf, len, false); 128 } 129 static inline void cpu_physical_memory_write(hwaddr addr, 130 const void *buf, hwaddr len) 131 { 132 cpu_physical_memory_rw(addr, (void *)buf, len, true); 133 } 134 void cpu_reloading_memory_map(void); 135 void *cpu_physical_memory_map(hwaddr addr, 136 hwaddr *plen, 137 bool is_write); 138 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 139 bool is_write, hwaddr access_len); 140 void cpu_register_map_client(QEMUBH *bh); 141 void cpu_unregister_map_client(QEMUBH *bh); 142 143 bool cpu_physical_memory_is_io(hwaddr phys_addr); 144 145 /* Coalesced MMIO regions are areas where write operations can be reordered. 146 * This usually implies that write operations are side-effect free. This allows 147 * batching which can make a major impact on performance when using 148 * virtualization. 149 */ 150 void qemu_flush_coalesced_mmio_buffer(void); 151 152 void cpu_flush_icache_range(hwaddr start, hwaddr len); 153 154 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 155 156 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 157 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 158 159 #endif 160 161 /* Returns: 0 on success, -1 on error */ 162 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 163 void *ptr, size_t len, bool is_write); 164 165 /* vl.c */ 166 extern int singlestep; 167 168 void list_cpus(const char *optarg); 169 170 #endif /* CPU_COMMON_H */