xtfpga.c (24324B)
1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "cpu.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "elf.h" 37 #include "exec/memory.h" 38 #include "hw/char/serial.h" 39 #include "net/net.h" 40 #include "hw/sysbus.h" 41 #include "hw/block/flash.h" 42 #include "chardev/char.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/reset.h" 45 #include "sysemu/runstate.h" 46 #include "qemu/error-report.h" 47 #include "qemu/option.h" 48 #include "bootparam.h" 49 #include "xtensa_memory.h" 50 #include "hw/xtensa/mx_pic.h" 51 #include "migration/vmstate.h" 52 53 typedef struct XtfpgaFlashDesc { 54 hwaddr base; 55 size_t size; 56 size_t boot_base; 57 size_t sector_size; 58 } XtfpgaFlashDesc; 59 60 typedef struct XtfpgaBoardDesc { 61 const XtfpgaFlashDesc *flash; 62 size_t sram_size; 63 const hwaddr *io; 64 } XtfpgaBoardDesc; 65 66 typedef struct XtfpgaFpgaState { 67 MemoryRegion iomem; 68 uint32_t freq; 69 uint32_t leds; 70 uint32_t switches; 71 } XtfpgaFpgaState; 72 73 static void xtfpga_fpga_reset(void *opaque) 74 { 75 XtfpgaFpgaState *s = opaque; 76 77 s->leds = 0; 78 s->switches = 0; 79 } 80 81 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 82 unsigned size) 83 { 84 XtfpgaFpgaState *s = opaque; 85 86 switch (addr) { 87 case 0x0: /*build date code*/ 88 return 0x09272011; 89 90 case 0x4: /*processor clock frequency, Hz*/ 91 return s->freq; 92 93 case 0x8: /*LEDs (off = 0, on = 1)*/ 94 return s->leds; 95 96 case 0xc: /*DIP switches (off = 0, on = 1)*/ 97 return s->switches; 98 } 99 return 0; 100 } 101 102 static void xtfpga_fpga_write(void *opaque, hwaddr addr, 103 uint64_t val, unsigned size) 104 { 105 XtfpgaFpgaState *s = opaque; 106 107 switch (addr) { 108 case 0x8: /*LEDs (off = 0, on = 1)*/ 109 s->leds = val; 110 break; 111 112 case 0x10: /*board reset*/ 113 if (val == 0xdead) { 114 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 115 } 116 break; 117 } 118 } 119 120 static const MemoryRegionOps xtfpga_fpga_ops = { 121 .read = xtfpga_fpga_read, 122 .write = xtfpga_fpga_write, 123 .endianness = DEVICE_NATIVE_ENDIAN, 124 }; 125 126 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 127 hwaddr base, uint32_t freq) 128 { 129 XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1); 130 131 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 132 "xtfpga.fpga", 0x10000); 133 memory_region_add_subregion(address_space, base, &s->iomem); 134 s->freq = freq; 135 xtfpga_fpga_reset(s); 136 qemu_register_reset(xtfpga_fpga_reset, s); 137 return s; 138 } 139 140 static void xtfpga_net_init(MemoryRegion *address_space, 141 hwaddr base, 142 hwaddr descriptors, 143 hwaddr buffers, 144 qemu_irq irq, NICInfo *nd) 145 { 146 DeviceState *dev; 147 SysBusDevice *s; 148 MemoryRegion *ram; 149 150 dev = qdev_new("open_eth"); 151 qdev_set_nic_properties(dev, nd); 152 153 s = SYS_BUS_DEVICE(dev); 154 sysbus_realize_and_unref(s, &error_fatal); 155 sysbus_connect_irq(s, 0, irq); 156 memory_region_add_subregion(address_space, base, 157 sysbus_mmio_get_region(s, 0)); 158 memory_region_add_subregion(address_space, descriptors, 159 sysbus_mmio_get_region(s, 1)); 160 161 ram = g_malloc(sizeof(*ram)); 162 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 163 &error_fatal); 164 vmstate_register_ram_global(ram); 165 memory_region_add_subregion(address_space, buffers, ram); 166 } 167 168 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 169 const XtfpgaBoardDesc *board, 170 DriveInfo *dinfo, int be) 171 { 172 SysBusDevice *s; 173 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 174 175 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 176 qdev_prop_set_uint32(dev, "num-blocks", 177 board->flash->size / board->flash->sector_size); 178 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 179 qdev_prop_set_uint8(dev, "width", 2); 180 qdev_prop_set_bit(dev, "big-endian", be); 181 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 182 s = SYS_BUS_DEVICE(dev); 183 sysbus_realize_and_unref(s, &error_fatal); 184 memory_region_add_subregion(address_space, board->flash->base, 185 sysbus_mmio_get_region(s, 0)); 186 return PFLASH_CFI01(dev); 187 } 188 189 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 190 { 191 XtensaCPU *cpu = opaque; 192 193 return cpu_get_phys_page_debug(CPU(cpu), addr); 194 } 195 196 static void xtfpga_reset(void *opaque) 197 { 198 XtensaCPU *cpu = opaque; 199 200 cpu_reset(CPU(cpu)); 201 } 202 203 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 204 unsigned size) 205 { 206 return 0; 207 } 208 209 static void xtfpga_io_write(void *opaque, hwaddr addr, 210 uint64_t val, unsigned size) 211 { 212 } 213 214 static const MemoryRegionOps xtfpga_io_ops = { 215 .read = xtfpga_io_read, 216 .write = xtfpga_io_write, 217 .endianness = DEVICE_NATIVE_ENDIAN, 218 }; 219 220 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 221 { 222 #if TARGET_BIG_ENDIAN 223 int be = 1; 224 #else 225 int be = 0; 226 #endif 227 MemoryRegion *system_memory = get_system_memory(); 228 XtensaCPU *cpu = NULL; 229 CPUXtensaState *env = NULL; 230 MemoryRegion *system_io; 231 XtensaMxPic *mx_pic = NULL; 232 qemu_irq *extints; 233 DriveInfo *dinfo; 234 PFlashCFI01 *flash = NULL; 235 const char *kernel_filename = machine->kernel_filename; 236 const char *kernel_cmdline = machine->kernel_cmdline; 237 const char *dtb_filename = machine->dtb; 238 const char *initrd_filename = machine->initrd_filename; 239 const unsigned system_io_size = 224 * MiB; 240 uint32_t freq = 10000000; 241 int n; 242 unsigned int smp_cpus = machine->smp.cpus; 243 244 if (smp_cpus > 1) { 245 mx_pic = xtensa_mx_pic_init(31); 246 qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 247 } 248 for (n = 0; n < smp_cpus; n++) { 249 CPUXtensaState *cenv = NULL; 250 251 cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 252 cenv = &cpu->env; 253 if (!env) { 254 env = cenv; 255 freq = env->config->clock_freq_khz * 1000; 256 } 257 258 if (mx_pic) { 259 MemoryRegion *mx_eri; 260 261 mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 262 xtensa_get_extints(cenv), 263 xtensa_get_runstall(cenv)); 264 memory_region_add_subregion(xtensa_get_er_region(cenv), 265 0, mx_eri); 266 } 267 cenv->sregs[PRID] = n; 268 xtensa_select_static_vectors(cenv, n != 0); 269 qemu_register_reset(xtfpga_reset, cpu); 270 /* Need MMU initialized prior to ELF loading, 271 * so that ELF gets loaded into virtual addresses 272 */ 273 cpu_reset(CPU(cpu)); 274 } 275 if (smp_cpus > 1) { 276 extints = xtensa_mx_pic_get_extints(mx_pic); 277 } else { 278 extints = xtensa_get_extints(env); 279 } 280 281 if (env) { 282 XtensaMemory sysram = env->config->sysram; 283 284 sysram.location[0].size = machine->ram_size; 285 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 286 system_memory); 287 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 288 system_memory); 289 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 290 system_memory); 291 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 292 system_memory); 293 xtensa_create_memory_regions(&sysram, "xtensa.sysram", 294 system_memory); 295 } 296 297 system_io = g_malloc(sizeof(*system_io)); 298 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 299 system_io_size); 300 memory_region_add_subregion(system_memory, board->io[0], system_io); 301 if (board->io[1]) { 302 MemoryRegion *io = g_malloc(sizeof(*io)); 303 304 memory_region_init_alias(io, NULL, "xtfpga.io.cached", 305 system_io, 0, system_io_size); 306 memory_region_add_subregion(system_memory, board->io[1], io); 307 } 308 xtfpga_fpga_init(system_io, 0x0d020000, freq); 309 if (nd_table[0].used) { 310 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 311 extints[1], nd_table); 312 } 313 314 serial_mm_init(system_io, 0x0d050020, 2, extints[0], 315 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 316 317 dinfo = drive_get(IF_PFLASH, 0, 0); 318 if (dinfo) { 319 flash = xtfpga_flash_init(system_io, board, dinfo, be); 320 } 321 322 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 323 if (kernel_filename) { 324 uint32_t entry_point = env->pc; 325 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 326 uint32_t tagptr = env->config->sysrom.location[0].addr + 327 board->sram_size; 328 uint32_t cur_tagptr; 329 BpMemInfo memory_location = { 330 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 331 .start = tswap32(env->config->sysram.location[0].addr), 332 .end = tswap32(env->config->sysram.location[0].addr + 333 machine->ram_size), 334 }; 335 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 336 machine->ram_size : 0x08000000; 337 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 338 339 lowmem_end += env->config->sysram.location[0].addr; 340 cur_lowmem += env->config->sysram.location[0].addr; 341 342 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 343 system_memory); 344 345 if (kernel_cmdline) { 346 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 347 } 348 if (dtb_filename) { 349 bp_size += get_tag_size(sizeof(uint32_t)); 350 } 351 if (initrd_filename) { 352 bp_size += get_tag_size(sizeof(BpMemInfo)); 353 } 354 355 /* Put kernel bootparameters to the end of that SRAM */ 356 tagptr = (tagptr - bp_size) & ~0xff; 357 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 358 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 359 sizeof(memory_location), &memory_location); 360 361 if (kernel_cmdline) { 362 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 363 strlen(kernel_cmdline) + 1, kernel_cmdline); 364 } 365 #ifdef CONFIG_FDT 366 if (dtb_filename) { 367 int fdt_size; 368 void *fdt = load_device_tree(dtb_filename, &fdt_size); 369 uint32_t dtb_addr = tswap32(cur_lowmem); 370 371 if (!fdt) { 372 error_report("could not load DTB '%s'", dtb_filename); 373 exit(EXIT_FAILURE); 374 } 375 376 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 377 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 378 sizeof(dtb_addr), &dtb_addr); 379 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 380 g_free(fdt); 381 } 382 #else 383 if (dtb_filename) { 384 error_report("could not load DTB '%s': " 385 "FDT support is not configured in QEMU", 386 dtb_filename); 387 exit(EXIT_FAILURE); 388 } 389 #endif 390 if (initrd_filename) { 391 BpMemInfo initrd_location = { 0 }; 392 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 393 lowmem_end - cur_lowmem); 394 395 if (initrd_size < 0) { 396 initrd_size = load_image_targphys(initrd_filename, 397 cur_lowmem, 398 lowmem_end - cur_lowmem); 399 } 400 if (initrd_size < 0) { 401 error_report("could not load initrd '%s'", initrd_filename); 402 exit(EXIT_FAILURE); 403 } 404 initrd_location.start = tswap32(cur_lowmem); 405 initrd_location.end = tswap32(cur_lowmem + initrd_size); 406 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 407 sizeof(initrd_location), &initrd_location); 408 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 409 } 410 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 411 env->regs[2] = tagptr; 412 413 uint64_t elf_entry; 414 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 415 &elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); 416 if (success > 0) { 417 entry_point = elf_entry; 418 } else { 419 hwaddr ep; 420 int is_linux; 421 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 422 translate_phys_addr, cpu); 423 if (success > 0 && is_linux) { 424 entry_point = ep; 425 } else { 426 error_report("could not load kernel '%s'", 427 kernel_filename); 428 exit(EXIT_FAILURE); 429 } 430 } 431 if (entry_point != env->pc) { 432 uint8_t boot[] = { 433 #if TARGET_BIG_ENDIAN 434 0x60, 0x00, 0x08, /* j 1f */ 435 0x00, /* .literal_position */ 436 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 437 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 438 /* 1: */ 439 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 440 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 441 0x0a, 0x00, 0x00, /* jx a0 */ 442 #else 443 0x06, 0x02, 0x00, /* j 1f */ 444 0x00, /* .literal_position */ 445 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 446 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 447 /* 1: */ 448 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 449 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 450 0xa0, 0x00, 0x00, /* jx a0 */ 451 #endif 452 }; 453 uint32_t entry_pc = tswap32(entry_point); 454 uint32_t entry_a2 = tswap32(tagptr); 455 456 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 457 memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 458 cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 459 } 460 } else { 461 if (flash) { 462 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 463 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 464 uint32_t size = env->config->sysrom.location[0].size; 465 466 if (board->flash->size - board->flash->boot_base < size) { 467 size = board->flash->size - board->flash->boot_base; 468 } 469 470 memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 471 flash_mr, board->flash->boot_base, size); 472 memory_region_add_subregion(system_memory, 473 env->config->sysrom.location[0].addr, 474 flash_io); 475 } else { 476 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 477 system_memory); 478 } 479 } 480 } 481 482 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 483 484 static const hwaddr xtfpga_mmu_io[2] = { 485 0xf0000000, 486 }; 487 488 static const hwaddr xtfpga_nommu_io[2] = { 489 0x90000000, 490 0x70000000, 491 }; 492 493 static const XtfpgaFlashDesc lx60_flash = { 494 .base = 0x08000000, 495 .size = 0x00400000, 496 .sector_size = 0x10000, 497 }; 498 499 static void xtfpga_lx60_init(MachineState *machine) 500 { 501 static const XtfpgaBoardDesc lx60_board = { 502 .flash = &lx60_flash, 503 .sram_size = 0x20000, 504 .io = xtfpga_mmu_io, 505 }; 506 xtfpga_init(&lx60_board, machine); 507 } 508 509 static void xtfpga_lx60_nommu_init(MachineState *machine) 510 { 511 static const XtfpgaBoardDesc lx60_board = { 512 .flash = &lx60_flash, 513 .sram_size = 0x20000, 514 .io = xtfpga_nommu_io, 515 }; 516 xtfpga_init(&lx60_board, machine); 517 } 518 519 static const XtfpgaFlashDesc lx200_flash = { 520 .base = 0x08000000, 521 .size = 0x01000000, 522 .sector_size = 0x20000, 523 }; 524 525 static void xtfpga_lx200_init(MachineState *machine) 526 { 527 static const XtfpgaBoardDesc lx200_board = { 528 .flash = &lx200_flash, 529 .sram_size = 0x2000000, 530 .io = xtfpga_mmu_io, 531 }; 532 xtfpga_init(&lx200_board, machine); 533 } 534 535 static void xtfpga_lx200_nommu_init(MachineState *machine) 536 { 537 static const XtfpgaBoardDesc lx200_board = { 538 .flash = &lx200_flash, 539 .sram_size = 0x2000000, 540 .io = xtfpga_nommu_io, 541 }; 542 xtfpga_init(&lx200_board, machine); 543 } 544 545 static const XtfpgaFlashDesc ml605_flash = { 546 .base = 0x08000000, 547 .size = 0x01000000, 548 .sector_size = 0x20000, 549 }; 550 551 static void xtfpga_ml605_init(MachineState *machine) 552 { 553 static const XtfpgaBoardDesc ml605_board = { 554 .flash = &ml605_flash, 555 .sram_size = 0x2000000, 556 .io = xtfpga_mmu_io, 557 }; 558 xtfpga_init(&ml605_board, machine); 559 } 560 561 static void xtfpga_ml605_nommu_init(MachineState *machine) 562 { 563 static const XtfpgaBoardDesc ml605_board = { 564 .flash = &ml605_flash, 565 .sram_size = 0x2000000, 566 .io = xtfpga_nommu_io, 567 }; 568 xtfpga_init(&ml605_board, machine); 569 } 570 571 static const XtfpgaFlashDesc kc705_flash = { 572 .base = 0x00000000, 573 .size = 0x08000000, 574 .boot_base = 0x06000000, 575 .sector_size = 0x20000, 576 }; 577 578 static void xtfpga_kc705_init(MachineState *machine) 579 { 580 static const XtfpgaBoardDesc kc705_board = { 581 .flash = &kc705_flash, 582 .sram_size = 0x2000000, 583 .io = xtfpga_mmu_io, 584 }; 585 xtfpga_init(&kc705_board, machine); 586 } 587 588 static void xtfpga_kc705_nommu_init(MachineState *machine) 589 { 590 static const XtfpgaBoardDesc kc705_board = { 591 .flash = &kc705_flash, 592 .sram_size = 0x2000000, 593 .io = xtfpga_nommu_io, 594 }; 595 xtfpga_init(&kc705_board, machine); 596 } 597 598 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 599 { 600 MachineClass *mc = MACHINE_CLASS(oc); 601 602 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 603 mc->init = xtfpga_lx60_init; 604 mc->max_cpus = 32; 605 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 606 mc->default_ram_size = 64 * MiB; 607 } 608 609 static const TypeInfo xtfpga_lx60_type = { 610 .name = MACHINE_TYPE_NAME("lx60"), 611 .parent = TYPE_MACHINE, 612 .class_init = xtfpga_lx60_class_init, 613 }; 614 615 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 616 { 617 MachineClass *mc = MACHINE_CLASS(oc); 618 619 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 620 mc->init = xtfpga_lx60_nommu_init; 621 mc->max_cpus = 32; 622 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 623 mc->default_ram_size = 64 * MiB; 624 } 625 626 static const TypeInfo xtfpga_lx60_nommu_type = { 627 .name = MACHINE_TYPE_NAME("lx60-nommu"), 628 .parent = TYPE_MACHINE, 629 .class_init = xtfpga_lx60_nommu_class_init, 630 }; 631 632 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 633 { 634 MachineClass *mc = MACHINE_CLASS(oc); 635 636 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 637 mc->init = xtfpga_lx200_init; 638 mc->max_cpus = 32; 639 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 640 mc->default_ram_size = 96 * MiB; 641 } 642 643 static const TypeInfo xtfpga_lx200_type = { 644 .name = MACHINE_TYPE_NAME("lx200"), 645 .parent = TYPE_MACHINE, 646 .class_init = xtfpga_lx200_class_init, 647 }; 648 649 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 650 { 651 MachineClass *mc = MACHINE_CLASS(oc); 652 653 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 654 mc->init = xtfpga_lx200_nommu_init; 655 mc->max_cpus = 32; 656 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 657 mc->default_ram_size = 96 * MiB; 658 } 659 660 static const TypeInfo xtfpga_lx200_nommu_type = { 661 .name = MACHINE_TYPE_NAME("lx200-nommu"), 662 .parent = TYPE_MACHINE, 663 .class_init = xtfpga_lx200_nommu_class_init, 664 }; 665 666 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 667 { 668 MachineClass *mc = MACHINE_CLASS(oc); 669 670 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 671 mc->init = xtfpga_ml605_init; 672 mc->max_cpus = 32; 673 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 674 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 675 } 676 677 static const TypeInfo xtfpga_ml605_type = { 678 .name = MACHINE_TYPE_NAME("ml605"), 679 .parent = TYPE_MACHINE, 680 .class_init = xtfpga_ml605_class_init, 681 }; 682 683 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 684 { 685 MachineClass *mc = MACHINE_CLASS(oc); 686 687 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 688 mc->init = xtfpga_ml605_nommu_init; 689 mc->max_cpus = 32; 690 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 691 mc->default_ram_size = 256 * MiB; 692 } 693 694 static const TypeInfo xtfpga_ml605_nommu_type = { 695 .name = MACHINE_TYPE_NAME("ml605-nommu"), 696 .parent = TYPE_MACHINE, 697 .class_init = xtfpga_ml605_nommu_class_init, 698 }; 699 700 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 701 { 702 MachineClass *mc = MACHINE_CLASS(oc); 703 704 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 705 mc->init = xtfpga_kc705_init; 706 mc->max_cpus = 32; 707 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 708 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 709 } 710 711 static const TypeInfo xtfpga_kc705_type = { 712 .name = MACHINE_TYPE_NAME("kc705"), 713 .parent = TYPE_MACHINE, 714 .class_init = xtfpga_kc705_class_init, 715 }; 716 717 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 718 { 719 MachineClass *mc = MACHINE_CLASS(oc); 720 721 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 722 mc->init = xtfpga_kc705_nommu_init; 723 mc->max_cpus = 32; 724 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 725 mc->default_ram_size = 256 * MiB; 726 } 727 728 static const TypeInfo xtfpga_kc705_nommu_type = { 729 .name = MACHINE_TYPE_NAME("kc705-nommu"), 730 .parent = TYPE_MACHINE, 731 .class_init = xtfpga_kc705_nommu_class_init, 732 }; 733 734 static void xtfpga_machines_init(void) 735 { 736 type_register_static(&xtfpga_lx60_type); 737 type_register_static(&xtfpga_lx200_type); 738 type_register_static(&xtfpga_ml605_type); 739 type_register_static(&xtfpga_kc705_type); 740 type_register_static(&xtfpga_lx60_nommu_type); 741 type_register_static(&xtfpga_lx200_nommu_type); 742 type_register_static(&xtfpga_ml605_nommu_type); 743 type_register_static(&xtfpga_kc705_nommu_type); 744 } 745 746 type_init(xtfpga_machines_init)