aspeed_smc.c (62142B)
1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "qemu/units.h" 33 #include "trace.h" 34 35 #include "hw/irq.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/ssi/aspeed_smc.h" 38 39 /* CE Type Setting Register */ 40 #define R_CONF (0x00 / 4) 41 #define CONF_LEGACY_DISABLE (1 << 31) 42 #define CONF_ENABLE_W4 20 43 #define CONF_ENABLE_W3 19 44 #define CONF_ENABLE_W2 18 45 #define CONF_ENABLE_W1 17 46 #define CONF_ENABLE_W0 16 47 #define CONF_FLASH_TYPE4 8 48 #define CONF_FLASH_TYPE3 6 49 #define CONF_FLASH_TYPE2 4 50 #define CONF_FLASH_TYPE1 2 51 #define CONF_FLASH_TYPE0 0 52 #define CONF_FLASH_TYPE_NOR 0x0 53 #define CONF_FLASH_TYPE_NAND 0x1 54 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ 55 56 /* CE Control Register */ 57 #define R_CE_CTRL (0x04 / 4) 58 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ 59 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ 60 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ 61 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ 62 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ 63 64 /* Interrupt Control and Status Register */ 65 #define R_INTR_CTRL (0x08 / 4) 66 #define INTR_CTRL_DMA_STATUS (1 << 11) 67 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) 68 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) 69 #define INTR_CTRL_DMA_EN (1 << 3) 70 #define INTR_CTRL_CMD_ABORT_EN (1 << 2) 71 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) 72 73 /* Command Control Register */ 74 #define R_CE_CMD_CTRL (0x0C / 4) 75 #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4 76 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0 77 78 #define aspeed_smc_addr_byte_enabled(s, i) \ 79 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i))))) 80 #define aspeed_smc_data_byte_enabled(s, i) \ 81 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i))))) 82 83 /* CEx Control Register */ 84 #define R_CTRL0 (0x10 / 4) 85 #define CTRL_IO_QPI (1 << 31) 86 #define CTRL_IO_QUAD_DATA (1 << 30) 87 #define CTRL_IO_DUAL_DATA (1 << 29) 88 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ 89 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ 90 #define CTRL_CMD_SHIFT 16 91 #define CTRL_CMD_MASK 0xff 92 #define CTRL_DUMMY_HIGH_SHIFT 14 93 #define CTRL_AST2400_SPI_4BYTE (1 << 13) 94 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 95 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 96 #define CE_CTRL_CLOCK_FREQ(div) \ 97 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 98 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 99 #define CTRL_CE_STOP_ACTIVE (1 << 2) 100 #define CTRL_CMD_MODE_MASK 0x3 101 #define CTRL_READMODE 0x0 102 #define CTRL_FREADMODE 0x1 103 #define CTRL_WRITEMODE 0x2 104 #define CTRL_USERMODE 0x3 105 #define R_CTRL1 (0x14 / 4) 106 #define R_CTRL2 (0x18 / 4) 107 #define R_CTRL3 (0x1C / 4) 108 #define R_CTRL4 (0x20 / 4) 109 110 /* CEx Segment Address Register */ 111 #define R_SEG_ADDR0 (0x30 / 4) 112 #define SEG_END_SHIFT 24 /* 8MB units */ 113 #define SEG_END_MASK 0xff 114 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ 115 #define SEG_START_MASK 0xff 116 #define R_SEG_ADDR1 (0x34 / 4) 117 #define R_SEG_ADDR2 (0x38 / 4) 118 #define R_SEG_ADDR3 (0x3C / 4) 119 #define R_SEG_ADDR4 (0x40 / 4) 120 121 /* Misc Control Register #1 */ 122 #define R_MISC_CTRL1 (0x50 / 4) 123 124 /* SPI dummy cycle data */ 125 #define R_DUMMY_DATA (0x54 / 4) 126 127 /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */ 128 #define R_FMC_WDT2_CTRL (0x64 / 4) 129 #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */ 130 #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) 131 #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */ 132 #define FMC_WDT2_CTRL_EN BIT(0) 133 134 /* DMA Control/Status Register */ 135 #define R_DMA_CTRL (0x80 / 4) 136 #define DMA_CTRL_REQUEST (1 << 31) 137 #define DMA_CTRL_GRANT (1 << 30) 138 #define DMA_CTRL_DELAY_MASK 0xf 139 #define DMA_CTRL_DELAY_SHIFT 8 140 #define DMA_CTRL_FREQ_MASK 0xf 141 #define DMA_CTRL_FREQ_SHIFT 4 142 #define DMA_CTRL_CALIB (1 << 3) 143 #define DMA_CTRL_CKSUM (1 << 2) 144 #define DMA_CTRL_WRITE (1 << 1) 145 #define DMA_CTRL_ENABLE (1 << 0) 146 147 /* DMA Flash Side Address */ 148 #define R_DMA_FLASH_ADDR (0x84 / 4) 149 150 /* DMA DRAM Side Address */ 151 #define R_DMA_DRAM_ADDR (0x88 / 4) 152 153 /* DMA Length Register */ 154 #define R_DMA_LEN (0x8C / 4) 155 156 /* Checksum Calculation Result */ 157 #define R_DMA_CHECKSUM (0x90 / 4) 158 159 /* Read Timing Compensation Register */ 160 #define R_TIMINGS (0x94 / 4) 161 162 /* SPI controller registers and bits (AST2400) */ 163 #define R_SPI_CONF (0x00 / 4) 164 #define SPI_CONF_ENABLE_W0 0 165 #define R_SPI_CTRL0 (0x4 / 4) 166 #define R_SPI_MISC_CTRL (0x10 / 4) 167 #define R_SPI_TIMINGS (0x14 / 4) 168 169 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4) 170 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4) 171 172 /* 173 * DMA DRAM addresses should be 4 bytes aligned and the valid address 174 * range is 0x40000000 - 0x5FFFFFFF (AST2400) 175 * 0x80000000 - 0xBFFFFFFF (AST2500) 176 * 177 * DMA flash addresses should be 4 bytes aligned and the valid address 178 * range is 0x20000000 - 0x2FFFFFFF. 179 * 180 * DMA length is from 4 bytes to 32MB 181 * 0: 4 bytes 182 * 0x7FFFFF: 32M bytes 183 */ 184 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) 185 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) 186 #define DMA_LENGTH(val) ((val) & 0x01FFFFFC) 187 188 /* Flash opcodes. */ 189 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ 190 191 #define SNOOP_OFF 0xFF 192 #define SNOOP_START 0x0 193 194 /* 195 * Default segments mapping addresses and size for each peripheral per 196 * controller. These can be changed when board is initialized with the 197 * Segment Address Registers. 198 */ 199 static const AspeedSegments aspeed_2500_spi1_segments[]; 200 static const AspeedSegments aspeed_2500_spi2_segments[]; 201 202 #define ASPEED_SMC_FEATURE_DMA 0x1 203 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 204 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 205 206 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc) 207 { 208 return !!(asc->features & ASPEED_SMC_FEATURE_DMA); 209 } 210 211 static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc) 212 { 213 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); 214 } 215 216 #define aspeed_smc_error(fmt, ...) \ 217 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__) 218 219 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, 220 const AspeedSegments *new, 221 int cs) 222 { 223 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 224 AspeedSegments seg; 225 int i; 226 227 for (i = 0; i < asc->cs_num_max; i++) { 228 if (i == cs) { 229 continue; 230 } 231 232 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); 233 234 if (new->addr + new->size > seg.addr && 235 new->addr < seg.addr + seg.size) { 236 aspeed_smc_error("new segment CS%d [ 0x%" 237 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " 238 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 239 cs, new->addr, new->addr + new->size, 240 i, seg.addr, seg.addr + seg.size); 241 return true; 242 } 243 } 244 return false; 245 } 246 247 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, 248 uint64_t regval) 249 { 250 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 251 AspeedSMCFlash *fl = &s->flashes[cs]; 252 AspeedSegments seg; 253 254 asc->reg_to_segment(s, regval, &seg); 255 256 memory_region_transaction_begin(); 257 memory_region_set_size(&fl->mmio, seg.size); 258 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); 259 memory_region_set_enabled(&fl->mmio, !!seg.size); 260 memory_region_transaction_commit(); 261 262 if (asc->segment_addr_mask) { 263 regval &= asc->segment_addr_mask; 264 } 265 266 s->regs[R_SEG_ADDR0 + cs] = regval; 267 } 268 269 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, 270 uint64_t new) 271 { 272 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 273 AspeedSegments seg; 274 275 asc->reg_to_segment(s, new, &seg); 276 277 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); 278 279 /* The start address of CS0 is read-only */ 280 if (cs == 0 && seg.addr != asc->flash_window_base) { 281 aspeed_smc_error("Tried to change CS0 start address to 0x%" 282 HWADDR_PRIx, seg.addr); 283 seg.addr = asc->flash_window_base; 284 new = asc->segment_to_reg(s, &seg); 285 } 286 287 /* 288 * The end address of the AST2500 spi controllers is also 289 * read-only. 290 */ 291 if ((asc->segments == aspeed_2500_spi1_segments || 292 asc->segments == aspeed_2500_spi2_segments) && 293 cs == asc->cs_num_max && 294 seg.addr + seg.size != asc->segments[cs].addr + 295 asc->segments[cs].size) { 296 aspeed_smc_error("Tried to change CS%d end address to 0x%" 297 HWADDR_PRIx, cs, seg.addr + seg.size); 298 seg.size = asc->segments[cs].addr + asc->segments[cs].size - 299 seg.addr; 300 new = asc->segment_to_reg(s, &seg); 301 } 302 303 /* Keep the segment in the overall flash window */ 304 if (seg.size && 305 (seg.addr + seg.size <= asc->flash_window_base || 306 seg.addr > asc->flash_window_base + asc->flash_window_size)) { 307 aspeed_smc_error("new segment for CS%d is invalid : " 308 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 309 cs, seg.addr, seg.addr + seg.size); 310 return; 311 } 312 313 /* Check start address vs. alignment */ 314 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { 315 aspeed_smc_error("new segment for CS%d is not " 316 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 317 cs, seg.addr, seg.addr + seg.size); 318 } 319 320 /* And segments should not overlap (in the specs) */ 321 aspeed_smc_flash_overlap(s, &seg, cs); 322 323 /* All should be fine now to move the region */ 324 aspeed_smc_flash_set_segment_region(s, cs, new); 325 } 326 327 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, 328 unsigned size) 329 { 330 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); 331 return 0; 332 } 333 334 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, 335 uint64_t data, unsigned size) 336 { 337 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, 338 addr, size, data); 339 } 340 341 static const MemoryRegionOps aspeed_smc_flash_default_ops = { 342 .read = aspeed_smc_flash_default_read, 343 .write = aspeed_smc_flash_default_write, 344 .endianness = DEVICE_LITTLE_ENDIAN, 345 .valid = { 346 .min_access_size = 1, 347 .max_access_size = 4, 348 }, 349 }; 350 351 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl) 352 { 353 const AspeedSMCState *s = fl->controller; 354 355 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; 356 } 357 358 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl) 359 { 360 const AspeedSMCState *s = fl->controller; 361 362 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); 363 } 364 365 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) 366 { 367 const AspeedSMCState *s = fl->controller; 368 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; 369 370 /* 371 * In read mode, the default SPI command is READ (0x3). In other 372 * modes, the command should necessarily be defined 373 * 374 * TODO: add support for READ4 (0x13) on AST2600 375 */ 376 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { 377 cmd = SPI_OP_READ; 378 } 379 380 if (!cmd) { 381 aspeed_smc_error("no command defined for mode %d", 382 aspeed_smc_flash_mode(fl)); 383 } 384 385 return cmd; 386 } 387 388 static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl) 389 { 390 const AspeedSMCState *s = fl->controller; 391 AspeedSMCClass *asc = fl->asc; 392 393 if (asc->addr_width) { 394 return asc->addr_width(s); 395 } else { 396 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3; 397 } 398 } 399 400 static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) 401 { 402 AspeedSMCState *s = fl->controller; 403 404 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); 405 406 qemu_set_irq(s->cs_lines[fl->cs], unselect); 407 } 408 409 static void aspeed_smc_flash_select(AspeedSMCFlash *fl) 410 { 411 aspeed_smc_flash_do_select(fl, false); 412 } 413 414 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) 415 { 416 aspeed_smc_flash_do_select(fl, true); 417 } 418 419 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, 420 uint32_t addr) 421 { 422 const AspeedSMCState *s = fl->controller; 423 AspeedSMCClass *asc = fl->asc; 424 AspeedSegments seg; 425 426 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); 427 if ((addr % seg.size) != addr) { 428 aspeed_smc_error("invalid address 0x%08x for CS%d segment : " 429 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 430 addr, fl->cs, seg.addr, seg.addr + seg.size); 431 addr %= seg.size; 432 } 433 434 return addr; 435 } 436 437 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl) 438 { 439 const AspeedSMCState *s = fl->controller; 440 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; 441 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; 442 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; 443 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8; 444 445 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) { 446 dummies /= 2; 447 } 448 449 return dummies; 450 } 451 452 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) 453 { 454 const AspeedSMCState *s = fl->controller; 455 uint8_t cmd = aspeed_smc_flash_cmd(fl); 456 int i = aspeed_smc_flash_addr_width(fl); 457 458 /* Flash access can not exceed CS segment */ 459 addr = aspeed_smc_check_segment_addr(fl, addr); 460 461 ssi_transfer(s->spi, cmd); 462 while (i--) { 463 if (aspeed_smc_addr_byte_enabled(s, i)) { 464 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); 465 } 466 } 467 468 /* 469 * Use fake transfers to model dummy bytes. The value should 470 * be configured to some non-zero value in fast read mode and 471 * zero in read mode. But, as the HW allows inconsistent 472 * settings, let's check for fast read mode. 473 */ 474 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { 475 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { 476 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); 477 } 478 } 479 } 480 481 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) 482 { 483 AspeedSMCFlash *fl = opaque; 484 AspeedSMCState *s = fl->controller; 485 uint64_t ret = 0; 486 int i; 487 488 switch (aspeed_smc_flash_mode(fl)) { 489 case CTRL_USERMODE: 490 for (i = 0; i < size; i++) { 491 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); 492 } 493 break; 494 case CTRL_READMODE: 495 case CTRL_FREADMODE: 496 aspeed_smc_flash_select(fl); 497 aspeed_smc_flash_setup(fl, addr); 498 499 for (i = 0; i < size; i++) { 500 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); 501 } 502 503 aspeed_smc_flash_unselect(fl); 504 break; 505 default: 506 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); 507 } 508 509 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, 510 aspeed_smc_flash_mode(fl)); 511 return ret; 512 } 513 514 /* 515 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a 516 * common include header. 517 */ 518 typedef enum { 519 READ = 0x3, READ_4 = 0x13, 520 FAST_READ = 0xb, FAST_READ_4 = 0x0c, 521 DOR = 0x3b, DOR_4 = 0x3c, 522 QOR = 0x6b, QOR_4 = 0x6c, 523 DIOR = 0xbb, DIOR_4 = 0xbc, 524 QIOR = 0xeb, QIOR_4 = 0xec, 525 526 PP = 0x2, PP_4 = 0x12, 527 DPP = 0xa2, 528 QPP = 0x32, QPP_4 = 0x34, 529 } FlashCMD; 530 531 static int aspeed_smc_num_dummies(uint8_t command) 532 { 533 switch (command) { /* check for dummies */ 534 case READ: /* no dummy bytes/cycles */ 535 case PP: 536 case DPP: 537 case QPP: 538 case READ_4: 539 case PP_4: 540 case QPP_4: 541 return 0; 542 case FAST_READ: 543 case DOR: 544 case QOR: 545 case FAST_READ_4: 546 case DOR_4: 547 case QOR_4: 548 return 1; 549 case DIOR: 550 case DIOR_4: 551 return 2; 552 case QIOR: 553 case QIOR_4: 554 return 4; 555 default: 556 return -1; 557 } 558 } 559 560 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, 561 unsigned size) 562 { 563 AspeedSMCState *s = fl->controller; 564 uint8_t addr_width = aspeed_smc_flash_addr_width(fl); 565 566 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies, 567 (uint8_t) data & 0xff); 568 569 if (s->snoop_index == SNOOP_OFF) { 570 return false; /* Do nothing */ 571 572 } else if (s->snoop_index == SNOOP_START) { 573 uint8_t cmd = data & 0xff; 574 int ndummies = aspeed_smc_num_dummies(cmd); 575 576 /* 577 * No dummy cycles are expected with the current command. Turn 578 * off snooping and let the transfer proceed normally. 579 */ 580 if (ndummies <= 0) { 581 s->snoop_index = SNOOP_OFF; 582 return false; 583 } 584 585 s->snoop_dummies = ndummies * 8; 586 587 } else if (s->snoop_index >= addr_width + 1) { 588 589 /* The SPI transfer has reached the dummy cycles sequence */ 590 for (; s->snoop_dummies; s->snoop_dummies--) { 591 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); 592 } 593 594 /* If no more dummy cycles are expected, turn off snooping */ 595 if (!s->snoop_dummies) { 596 s->snoop_index = SNOOP_OFF; 597 } else { 598 s->snoop_index += size; 599 } 600 601 /* 602 * Dummy cycles have been faked already. Ignore the current 603 * SPI transfer 604 */ 605 return true; 606 } 607 608 s->snoop_index += size; 609 return false; 610 } 611 612 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, 613 unsigned size) 614 { 615 AspeedSMCFlash *fl = opaque; 616 AspeedSMCState *s = fl->controller; 617 int i; 618 619 trace_aspeed_smc_flash_write(fl->cs, addr, size, data, 620 aspeed_smc_flash_mode(fl)); 621 622 if (!aspeed_smc_is_writable(fl)) { 623 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); 624 return; 625 } 626 627 switch (aspeed_smc_flash_mode(fl)) { 628 case CTRL_USERMODE: 629 if (aspeed_smc_do_snoop(fl, data, size)) { 630 break; 631 } 632 633 for (i = 0; i < size; i++) { 634 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 635 } 636 break; 637 case CTRL_WRITEMODE: 638 aspeed_smc_flash_select(fl); 639 aspeed_smc_flash_setup(fl, addr); 640 641 for (i = 0; i < size; i++) { 642 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 643 } 644 645 aspeed_smc_flash_unselect(fl); 646 break; 647 default: 648 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); 649 } 650 } 651 652 static const MemoryRegionOps aspeed_smc_flash_ops = { 653 .read = aspeed_smc_flash_read, 654 .write = aspeed_smc_flash_write, 655 .endianness = DEVICE_LITTLE_ENDIAN, 656 .valid = { 657 .min_access_size = 1, 658 .max_access_size = 4, 659 }, 660 }; 661 662 static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) 663 { 664 AspeedSMCState *s = fl->controller; 665 bool unselect; 666 667 /* User mode selects the CS, other modes unselect */ 668 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE; 669 670 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ 671 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && 672 value & CTRL_CE_STOP_ACTIVE) { 673 unselect = true; 674 } 675 676 s->regs[s->r_ctrl0 + fl->cs] = value; 677 678 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; 679 680 aspeed_smc_flash_do_select(fl, unselect); 681 } 682 683 static void aspeed_smc_reset(DeviceState *d) 684 { 685 AspeedSMCState *s = ASPEED_SMC(d); 686 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 687 int i; 688 689 if (asc->resets) { 690 memcpy(s->regs, asc->resets, sizeof s->regs); 691 } else { 692 memset(s->regs, 0, sizeof s->regs); 693 } 694 695 /* Unselect all peripherals */ 696 for (i = 0; i < asc->cs_num_max; ++i) { 697 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; 698 qemu_set_irq(s->cs_lines[i], true); 699 } 700 701 /* setup the default segment register values and regions for all */ 702 for (i = 0; i < asc->cs_num_max; ++i) { 703 aspeed_smc_flash_set_segment_region(s, i, 704 asc->segment_to_reg(s, &asc->segments[i])); 705 } 706 707 s->snoop_index = SNOOP_OFF; 708 s->snoop_dummies = 0; 709 } 710 711 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) 712 { 713 AspeedSMCState *s = ASPEED_SMC(opaque); 714 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque); 715 716 addr >>= 2; 717 718 if (addr == s->r_conf || 719 (addr >= s->r_timings && 720 addr < s->r_timings + asc->nregs_timings) || 721 addr == s->r_ce_ctrl || 722 addr == R_CE_CMD_CTRL || 723 addr == R_INTR_CTRL || 724 addr == R_DUMMY_DATA || 725 (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) || 726 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) || 727 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) || 728 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) || 729 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) || 730 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) || 731 (addr >= R_SEG_ADDR0 && 732 addr < R_SEG_ADDR0 + asc->cs_num_max) || 733 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { 734 735 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); 736 737 return s->regs[addr]; 738 } else { 739 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 740 __func__, addr); 741 return -1; 742 } 743 } 744 745 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) 746 { 747 /* HCLK/1 .. HCLK/16 */ 748 const uint8_t hclk_divisors[] = { 749 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 750 }; 751 int i; 752 753 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { 754 if (hclk_mask == hclk_divisors[i]) { 755 return i + 1; 756 } 757 } 758 759 aspeed_smc_error("invalid HCLK mask %x", hclk_mask); 760 return 0; 761 } 762 763 /* 764 * When doing calibration, the SPI clock rate in the CE0 Control 765 * Register and the read delay cycles in the Read Timing Compensation 766 * Register are set using bit[11:4] of the DMA Control Register. 767 */ 768 static void aspeed_smc_dma_calibration(AspeedSMCState *s) 769 { 770 uint8_t delay = 771 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; 772 uint8_t hclk_mask = 773 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; 774 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); 775 uint32_t hclk_shift = (hclk_div - 1) << 2; 776 uint8_t cs; 777 778 /* 779 * The Read Timing Compensation Register values apply to all CS on 780 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays 781 */ 782 if (hclk_div && hclk_div < 6) { 783 s->regs[s->r_timings] &= ~(0xf << hclk_shift); 784 s->regs[s->r_timings] |= delay << hclk_shift; 785 } 786 787 /* 788 * TODO: compute the CS from the DMA address and the segment 789 * registers. This is not really a problem for now because the 790 * Timing Register values apply to all CS and software uses CS0 to 791 * do calibration. 792 */ 793 cs = 0; 794 s->regs[s->r_ctrl0 + cs] &= 795 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); 796 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); 797 } 798 799 /* 800 * Emulate read errors in the DMA Checksum Register for high 801 * frequencies and optimistic settings of the Read Timing Compensation 802 * Register. This will help in tuning the SPI timing calibration 803 * algorithm. 804 */ 805 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) 806 { 807 uint8_t delay = 808 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; 809 uint8_t hclk_mask = 810 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; 811 812 /* 813 * Typical values of a palmetto-bmc machine. 814 */ 815 switch (aspeed_smc_hclk_divisor(hclk_mask)) { 816 case 4 ... 16: 817 return false; 818 case 3: /* at least one HCLK cycle delay */ 819 return (delay & 0x7) < 1; 820 case 2: /* at least two HCLK cycle delay */ 821 return (delay & 0x7) < 2; 822 case 1: /* (> 100MHz) is above the max freq of the controller */ 823 return true; 824 default: 825 g_assert_not_reached(); 826 } 827 } 828 829 /* 830 * Accumulate the result of the reads to provide a checksum that will 831 * be used to validate the read timing settings. 832 */ 833 static void aspeed_smc_dma_checksum(AspeedSMCState *s) 834 { 835 MemTxResult result; 836 uint32_t data; 837 838 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { 839 aspeed_smc_error("invalid direction for DMA checksum"); 840 return; 841 } 842 843 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { 844 aspeed_smc_dma_calibration(s); 845 } 846 847 while (s->regs[R_DMA_LEN]) { 848 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 849 MEMTXATTRS_UNSPECIFIED, &result); 850 if (result != MEMTX_OK) { 851 aspeed_smc_error("Flash read failed @%08x", 852 s->regs[R_DMA_FLASH_ADDR]); 853 return; 854 } 855 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); 856 857 /* 858 * When the DMA is on-going, the DMA registers are updated 859 * with the current working addresses and length. 860 */ 861 s->regs[R_DMA_CHECKSUM] += data; 862 s->regs[R_DMA_FLASH_ADDR] += 4; 863 s->regs[R_DMA_LEN] -= 4; 864 } 865 866 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { 867 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; 868 } 869 870 } 871 872 static void aspeed_smc_dma_rw(AspeedSMCState *s) 873 { 874 MemTxResult result; 875 uint32_t data; 876 877 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? 878 "write" : "read", 879 s->regs[R_DMA_FLASH_ADDR], 880 s->regs[R_DMA_DRAM_ADDR], 881 s->regs[R_DMA_LEN]); 882 while (s->regs[R_DMA_LEN]) { 883 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { 884 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], 885 MEMTXATTRS_UNSPECIFIED, &result); 886 if (result != MEMTX_OK) { 887 aspeed_smc_error("DRAM read failed @%08x", 888 s->regs[R_DMA_DRAM_ADDR]); 889 return; 890 } 891 892 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 893 data, MEMTXATTRS_UNSPECIFIED, &result); 894 if (result != MEMTX_OK) { 895 aspeed_smc_error("Flash write failed @%08x", 896 s->regs[R_DMA_FLASH_ADDR]); 897 return; 898 } 899 } else { 900 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 901 MEMTXATTRS_UNSPECIFIED, &result); 902 if (result != MEMTX_OK) { 903 aspeed_smc_error("Flash read failed @%08x", 904 s->regs[R_DMA_FLASH_ADDR]); 905 return; 906 } 907 908 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], 909 data, MEMTXATTRS_UNSPECIFIED, &result); 910 if (result != MEMTX_OK) { 911 aspeed_smc_error("DRAM write failed @%08x", 912 s->regs[R_DMA_DRAM_ADDR]); 913 return; 914 } 915 } 916 917 /* 918 * When the DMA is on-going, the DMA registers are updated 919 * with the current working addresses and length. 920 */ 921 s->regs[R_DMA_FLASH_ADDR] += 4; 922 s->regs[R_DMA_DRAM_ADDR] += 4; 923 s->regs[R_DMA_LEN] -= 4; 924 s->regs[R_DMA_CHECKSUM] += data; 925 } 926 } 927 928 static void aspeed_smc_dma_stop(AspeedSMCState *s) 929 { 930 /* 931 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the 932 * engine is idle 933 */ 934 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; 935 s->regs[R_DMA_CHECKSUM] = 0; 936 937 /* 938 * Lower the DMA irq in any case. The IRQ control register could 939 * have been cleared before disabling the DMA. 940 */ 941 qemu_irq_lower(s->irq); 942 } 943 944 /* 945 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA 946 * can start even if the result of the previous was not collected. 947 */ 948 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) 949 { 950 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && 951 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); 952 } 953 954 static void aspeed_smc_dma_done(AspeedSMCState *s) 955 { 956 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; 957 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { 958 qemu_irq_raise(s->irq); 959 } 960 } 961 962 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) 963 { 964 if (!(dma_ctrl & DMA_CTRL_ENABLE)) { 965 s->regs[R_DMA_CTRL] = dma_ctrl; 966 967 aspeed_smc_dma_stop(s); 968 return; 969 } 970 971 if (aspeed_smc_dma_in_progress(s)) { 972 aspeed_smc_error("DMA in progress !"); 973 return; 974 } 975 976 s->regs[R_DMA_CTRL] = dma_ctrl; 977 978 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { 979 aspeed_smc_dma_checksum(s); 980 } else { 981 aspeed_smc_dma_rw(s); 982 } 983 984 aspeed_smc_dma_done(s); 985 } 986 987 static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) 988 { 989 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 990 991 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { 992 return true; 993 } 994 995 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { 996 aspeed_smc_error("DMA not granted"); 997 return false; 998 } 999 1000 return true; 1001 } 1002 1003 static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) 1004 { 1005 /* Preserve DMA bits */ 1006 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1007 1008 if (dma_ctrl == 0xAEED0000) { 1009 /* automatically grant request */ 1010 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1011 return; 1012 } 1013 1014 /* clear request */ 1015 if (dma_ctrl == 0xDEEA0000) { 1016 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1017 return; 1018 } 1019 1020 if (!aspeed_smc_dma_granted(s)) { 1021 aspeed_smc_error("DMA not granted"); 1022 return; 1023 } 1024 1025 aspeed_smc_dma_ctrl(s, dma_ctrl); 1026 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1027 } 1028 1029 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, 1030 unsigned int size) 1031 { 1032 AspeedSMCState *s = ASPEED_SMC(opaque); 1033 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1034 uint32_t value = data; 1035 1036 trace_aspeed_smc_write(addr, size, data); 1037 1038 addr >>= 2; 1039 1040 if (addr == s->r_conf || 1041 (addr >= s->r_timings && 1042 addr < s->r_timings + asc->nregs_timings) || 1043 addr == s->r_ce_ctrl) { 1044 s->regs[addr] = value; 1045 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { 1046 int cs = addr - s->r_ctrl0; 1047 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); 1048 } else if (addr >= R_SEG_ADDR0 && 1049 addr < R_SEG_ADDR0 + asc->cs_num_max) { 1050 int cs = addr - R_SEG_ADDR0; 1051 1052 if (value != s->regs[R_SEG_ADDR0 + cs]) { 1053 aspeed_smc_flash_set_segment(s, cs, value); 1054 } 1055 } else if (addr == R_CE_CMD_CTRL) { 1056 s->regs[addr] = value & 0xff; 1057 } else if (addr == R_DUMMY_DATA) { 1058 s->regs[addr] = value & 0xff; 1059 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) { 1060 s->regs[addr] = value & FMC_WDT2_CTRL_EN; 1061 } else if (addr == R_INTR_CTRL) { 1062 s->regs[addr] = value; 1063 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) { 1064 asc->dma_ctrl(s, value); 1065 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR && 1066 aspeed_smc_dma_granted(s)) { 1067 s->regs[addr] = DMA_DRAM_ADDR(asc, value); 1068 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR && 1069 aspeed_smc_dma_granted(s)) { 1070 s->regs[addr] = DMA_FLASH_ADDR(asc, value); 1071 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN && 1072 aspeed_smc_dma_granted(s)) { 1073 s->regs[addr] = DMA_LENGTH(value); 1074 } else { 1075 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 1076 __func__, addr); 1077 return; 1078 } 1079 } 1080 1081 static const MemoryRegionOps aspeed_smc_ops = { 1082 .read = aspeed_smc_read, 1083 .write = aspeed_smc_write, 1084 .endianness = DEVICE_LITTLE_ENDIAN, 1085 }; 1086 1087 static void aspeed_smc_instance_init(Object *obj) 1088 { 1089 AspeedSMCState *s = ASPEED_SMC(obj); 1090 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1091 int i; 1092 1093 for (i = 0; i < asc->cs_num_max; i++) { 1094 object_initialize_child(obj, "flash[*]", &s->flashes[i], 1095 TYPE_ASPEED_SMC_FLASH); 1096 } 1097 } 1098 1099 /* 1100 * Initialize the custom address spaces for DMAs 1101 */ 1102 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp) 1103 { 1104 if (!s->dram_mr) { 1105 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set"); 1106 return; 1107 } 1108 1109 address_space_init(&s->flash_as, &s->mmio_flash, 1110 TYPE_ASPEED_SMC ".dma-flash"); 1111 address_space_init(&s->dram_as, s->dram_mr, 1112 TYPE_ASPEED_SMC ".dma-dram"); 1113 } 1114 1115 static void aspeed_smc_realize(DeviceState *dev, Error **errp) 1116 { 1117 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1118 AspeedSMCState *s = ASPEED_SMC(dev); 1119 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1120 int i; 1121 hwaddr offset = 0; 1122 1123 /* keep a copy under AspeedSMCState to speed up accesses */ 1124 s->r_conf = asc->r_conf; 1125 s->r_ce_ctrl = asc->r_ce_ctrl; 1126 s->r_ctrl0 = asc->r_ctrl0; 1127 s->r_timings = asc->r_timings; 1128 s->conf_enable_w0 = asc->conf_enable_w0; 1129 1130 /* DMA irq. Keep it first for the initialization in the SoC */ 1131 sysbus_init_irq(sbd, &s->irq); 1132 1133 s->spi = ssi_create_bus(dev, NULL); 1134 1135 /* Setup cs_lines for peripherals */ 1136 s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); 1137 1138 for (i = 0; i < asc->cs_num_max; ++i) { 1139 sysbus_init_irq(sbd, &s->cs_lines[i]); 1140 } 1141 1142 /* The memory region for the controller registers */ 1143 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, 1144 TYPE_ASPEED_SMC, asc->nregs * 4); 1145 sysbus_init_mmio(sbd, &s->mmio); 1146 1147 /* 1148 * The container memory region representing the address space 1149 * window in which the flash modules are mapped. The size and 1150 * address depends on the SoC model and controller type. 1151 */ 1152 memory_region_init(&s->mmio_flash_container, OBJECT(s), 1153 TYPE_ASPEED_SMC ".container", 1154 asc->flash_window_size); 1155 sysbus_init_mmio(sbd, &s->mmio_flash_container); 1156 1157 memory_region_init_io(&s->mmio_flash, OBJECT(s), 1158 &aspeed_smc_flash_default_ops, s, 1159 TYPE_ASPEED_SMC ".flash", 1160 asc->flash_window_size); 1161 memory_region_add_subregion(&s->mmio_flash_container, 0x0, 1162 &s->mmio_flash); 1163 1164 /* 1165 * Let's create a sub memory region for each possible peripheral. All 1166 * have a configurable memory segment in the overall flash mapping 1167 * window of the controller but, there is not necessarily a flash 1168 * module behind to handle the memory accesses. This depends on 1169 * the board configuration. 1170 */ 1171 for (i = 0; i < asc->cs_num_max; ++i) { 1172 AspeedSMCFlash *fl = &s->flashes[i]; 1173 1174 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s), 1175 errp)) { 1176 return; 1177 } 1178 if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) { 1179 return; 1180 } 1181 if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) { 1182 return; 1183 } 1184 1185 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); 1186 offset += asc->segments[i].size; 1187 } 1188 1189 /* DMA support */ 1190 if (aspeed_smc_has_dma(asc)) { 1191 aspeed_smc_dma_setup(s, errp); 1192 } 1193 } 1194 1195 static const VMStateDescription vmstate_aspeed_smc = { 1196 .name = "aspeed.smc", 1197 .version_id = 2, 1198 .minimum_version_id = 2, 1199 .fields = (VMStateField[]) { 1200 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), 1201 VMSTATE_UINT8(snoop_index, AspeedSMCState), 1202 VMSTATE_UINT8(snoop_dummies, AspeedSMCState), 1203 VMSTATE_END_OF_LIST() 1204 } 1205 }; 1206 1207 static Property aspeed_smc_properties[] = { 1208 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), 1209 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, 1210 TYPE_MEMORY_REGION, MemoryRegion *), 1211 DEFINE_PROP_END_OF_LIST(), 1212 }; 1213 1214 static void aspeed_smc_class_init(ObjectClass *klass, void *data) 1215 { 1216 DeviceClass *dc = DEVICE_CLASS(klass); 1217 1218 dc->realize = aspeed_smc_realize; 1219 dc->reset = aspeed_smc_reset; 1220 device_class_set_props(dc, aspeed_smc_properties); 1221 dc->vmsd = &vmstate_aspeed_smc; 1222 } 1223 1224 static const TypeInfo aspeed_smc_info = { 1225 .name = TYPE_ASPEED_SMC, 1226 .parent = TYPE_SYS_BUS_DEVICE, 1227 .instance_init = aspeed_smc_instance_init, 1228 .instance_size = sizeof(AspeedSMCState), 1229 .class_size = sizeof(AspeedSMCClass), 1230 .class_init = aspeed_smc_class_init, 1231 .abstract = true, 1232 }; 1233 1234 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp) 1235 { 1236 AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev); 1237 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs); 1238 1239 if (!s->controller) { 1240 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set"); 1241 return; 1242 } 1243 1244 s->asc = ASPEED_SMC_GET_CLASS(s->controller); 1245 1246 /* 1247 * Use the default segment value to size the memory region. This 1248 * can be changed by FW at runtime. 1249 */ 1250 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops, 1251 s, name, s->asc->segments[s->cs].size); 1252 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 1253 } 1254 1255 static Property aspeed_smc_flash_properties[] = { 1256 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0), 1257 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC, 1258 AspeedSMCState *), 1259 DEFINE_PROP_END_OF_LIST(), 1260 }; 1261 1262 static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data) 1263 { 1264 DeviceClass *dc = DEVICE_CLASS(klass); 1265 1266 dc->desc = "Aspeed SMC Flash device region"; 1267 dc->realize = aspeed_smc_flash_realize; 1268 device_class_set_props(dc, aspeed_smc_flash_properties); 1269 } 1270 1271 static const TypeInfo aspeed_smc_flash_info = { 1272 .name = TYPE_ASPEED_SMC_FLASH, 1273 .parent = TYPE_SYS_BUS_DEVICE, 1274 .instance_size = sizeof(AspeedSMCFlash), 1275 .class_init = aspeed_smc_flash_class_init, 1276 }; 1277 1278 /* 1279 * The Segment Registers of the AST2400 and AST2500 have a 8MB 1280 * unit. The address range of a flash SPI peripheral is encoded with 1281 * absolute addresses which should be part of the overall controller 1282 * window. 1283 */ 1284 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, 1285 const AspeedSegments *seg) 1286 { 1287 uint32_t reg = 0; 1288 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; 1289 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; 1290 return reg; 1291 } 1292 1293 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, 1294 uint32_t reg, AspeedSegments *seg) 1295 { 1296 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; 1297 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; 1298 } 1299 1300 static const AspeedSegments aspeed_2400_smc_segments[] = { 1301 { 0x10000000, 32 * MiB }, 1302 }; 1303 1304 static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data) 1305 { 1306 DeviceClass *dc = DEVICE_CLASS(klass); 1307 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1308 1309 dc->desc = "Aspeed 2400 SMC Controller"; 1310 asc->r_conf = R_CONF; 1311 asc->r_ce_ctrl = R_CE_CTRL; 1312 asc->r_ctrl0 = R_CTRL0; 1313 asc->r_timings = R_TIMINGS; 1314 asc->nregs_timings = 1; 1315 asc->conf_enable_w0 = CONF_ENABLE_W0; 1316 asc->cs_num_max = 1; 1317 asc->segments = aspeed_2400_smc_segments; 1318 asc->flash_window_base = 0x10000000; 1319 asc->flash_window_size = 0x6000000; 1320 asc->features = 0x0; 1321 asc->nregs = ASPEED_SMC_R_SMC_MAX; 1322 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1323 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1324 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1325 } 1326 1327 static const TypeInfo aspeed_2400_smc_info = { 1328 .name = "aspeed.smc-ast2400", 1329 .parent = TYPE_ASPEED_SMC, 1330 .class_init = aspeed_2400_smc_class_init, 1331 }; 1332 1333 static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = { 1334 /* 1335 * CE0 and CE1 types are HW strapped in SCU70. Do it here to 1336 * simplify the model. 1337 */ 1338 [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0, 1339 }; 1340 1341 static const AspeedSegments aspeed_2400_fmc_segments[] = { 1342 { 0x20000000, 64 * MiB }, /* start address is readonly */ 1343 { 0x24000000, 32 * MiB }, 1344 { 0x26000000, 32 * MiB }, 1345 { 0x28000000, 32 * MiB }, 1346 { 0x2A000000, 32 * MiB } 1347 }; 1348 1349 static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data) 1350 { 1351 DeviceClass *dc = DEVICE_CLASS(klass); 1352 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1353 1354 dc->desc = "Aspeed 2400 FMC Controller"; 1355 asc->r_conf = R_CONF; 1356 asc->r_ce_ctrl = R_CE_CTRL; 1357 asc->r_ctrl0 = R_CTRL0; 1358 asc->r_timings = R_TIMINGS; 1359 asc->nregs_timings = 1; 1360 asc->conf_enable_w0 = CONF_ENABLE_W0; 1361 asc->cs_num_max = 5; 1362 asc->segments = aspeed_2400_fmc_segments; 1363 asc->segment_addr_mask = 0xffff0000; 1364 asc->resets = aspeed_2400_fmc_resets; 1365 asc->flash_window_base = 0x20000000; 1366 asc->flash_window_size = 0x10000000; 1367 asc->features = ASPEED_SMC_FEATURE_DMA; 1368 asc->dma_flash_mask = 0x0FFFFFFC; 1369 asc->dma_dram_mask = 0x1FFFFFFC; 1370 asc->nregs = ASPEED_SMC_R_MAX; 1371 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1372 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1373 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1374 } 1375 1376 static const TypeInfo aspeed_2400_fmc_info = { 1377 .name = "aspeed.fmc-ast2400", 1378 .parent = TYPE_ASPEED_SMC, 1379 .class_init = aspeed_2400_fmc_class_init, 1380 }; 1381 1382 static const AspeedSegments aspeed_2400_spi1_segments[] = { 1383 { 0x30000000, 64 * MiB }, 1384 }; 1385 1386 static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s) 1387 { 1388 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3; 1389 } 1390 1391 static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data) 1392 { 1393 DeviceClass *dc = DEVICE_CLASS(klass); 1394 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1395 1396 dc->desc = "Aspeed 2400 SPI1 Controller"; 1397 asc->r_conf = R_SPI_CONF; 1398 asc->r_ce_ctrl = 0xff; 1399 asc->r_ctrl0 = R_SPI_CTRL0; 1400 asc->r_timings = R_SPI_TIMINGS; 1401 asc->nregs_timings = 1; 1402 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; 1403 asc->cs_num_max = 1; 1404 asc->segments = aspeed_2400_spi1_segments; 1405 asc->flash_window_base = 0x30000000; 1406 asc->flash_window_size = 0x10000000; 1407 asc->features = 0x0; 1408 asc->nregs = ASPEED_SMC_R_SPI_MAX; 1409 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1410 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1411 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1412 asc->addr_width = aspeed_2400_spi1_addr_width; 1413 } 1414 1415 static const TypeInfo aspeed_2400_spi1_info = { 1416 .name = "aspeed.spi1-ast2400", 1417 .parent = TYPE_ASPEED_SMC, 1418 .class_init = aspeed_2400_spi1_class_init, 1419 }; 1420 1421 static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = { 1422 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | 1423 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), 1424 }; 1425 1426 static const AspeedSegments aspeed_2500_fmc_segments[] = { 1427 { 0x20000000, 128 * MiB }, /* start address is readonly */ 1428 { 0x28000000, 32 * MiB }, 1429 { 0x2A000000, 32 * MiB }, 1430 }; 1431 1432 static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data) 1433 { 1434 DeviceClass *dc = DEVICE_CLASS(klass); 1435 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1436 1437 dc->desc = "Aspeed 2600 FMC Controller"; 1438 asc->r_conf = R_CONF; 1439 asc->r_ce_ctrl = R_CE_CTRL; 1440 asc->r_ctrl0 = R_CTRL0; 1441 asc->r_timings = R_TIMINGS; 1442 asc->nregs_timings = 1; 1443 asc->conf_enable_w0 = CONF_ENABLE_W0; 1444 asc->cs_num_max = 3; 1445 asc->segments = aspeed_2500_fmc_segments; 1446 asc->segment_addr_mask = 0xffff0000; 1447 asc->resets = aspeed_2500_fmc_resets; 1448 asc->flash_window_base = 0x20000000; 1449 asc->flash_window_size = 0x10000000; 1450 asc->features = ASPEED_SMC_FEATURE_DMA; 1451 asc->dma_flash_mask = 0x0FFFFFFC; 1452 asc->dma_dram_mask = 0x3FFFFFFC; 1453 asc->nregs = ASPEED_SMC_R_MAX; 1454 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1455 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1456 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1457 } 1458 1459 static const TypeInfo aspeed_2500_fmc_info = { 1460 .name = "aspeed.fmc-ast2500", 1461 .parent = TYPE_ASPEED_SMC, 1462 .class_init = aspeed_2500_fmc_class_init, 1463 }; 1464 1465 static const AspeedSegments aspeed_2500_spi1_segments[] = { 1466 { 0x30000000, 32 * MiB }, /* start address is readonly */ 1467 { 0x32000000, 96 * MiB }, /* end address is readonly */ 1468 }; 1469 1470 static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data) 1471 { 1472 DeviceClass *dc = DEVICE_CLASS(klass); 1473 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1474 1475 dc->desc = "Aspeed 2600 SPI1 Controller"; 1476 asc->r_conf = R_CONF; 1477 asc->r_ce_ctrl = R_CE_CTRL; 1478 asc->r_ctrl0 = R_CTRL0; 1479 asc->r_timings = R_TIMINGS; 1480 asc->nregs_timings = 1; 1481 asc->conf_enable_w0 = CONF_ENABLE_W0; 1482 asc->cs_num_max = 2; 1483 asc->segments = aspeed_2500_spi1_segments; 1484 asc->segment_addr_mask = 0xffff0000; 1485 asc->flash_window_base = 0x30000000; 1486 asc->flash_window_size = 0x8000000; 1487 asc->features = 0x0; 1488 asc->nregs = ASPEED_SMC_R_MAX; 1489 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1490 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1491 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1492 } 1493 1494 static const TypeInfo aspeed_2500_spi1_info = { 1495 .name = "aspeed.spi1-ast2500", 1496 .parent = TYPE_ASPEED_SMC, 1497 .class_init = aspeed_2500_spi1_class_init, 1498 }; 1499 1500 static const AspeedSegments aspeed_2500_spi2_segments[] = { 1501 { 0x38000000, 32 * MiB }, /* start address is readonly */ 1502 { 0x3A000000, 96 * MiB }, /* end address is readonly */ 1503 }; 1504 1505 static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data) 1506 { 1507 DeviceClass *dc = DEVICE_CLASS(klass); 1508 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1509 1510 dc->desc = "Aspeed 2600 SPI2 Controller"; 1511 asc->r_conf = R_CONF; 1512 asc->r_ce_ctrl = R_CE_CTRL; 1513 asc->r_ctrl0 = R_CTRL0; 1514 asc->r_timings = R_TIMINGS; 1515 asc->nregs_timings = 1; 1516 asc->conf_enable_w0 = CONF_ENABLE_W0; 1517 asc->cs_num_max = 2; 1518 asc->segments = aspeed_2500_spi2_segments; 1519 asc->segment_addr_mask = 0xffff0000; 1520 asc->flash_window_base = 0x38000000; 1521 asc->flash_window_size = 0x8000000; 1522 asc->features = 0x0; 1523 asc->nregs = ASPEED_SMC_R_MAX; 1524 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1525 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1526 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1527 } 1528 1529 static const TypeInfo aspeed_2500_spi2_info = { 1530 .name = "aspeed.spi2-ast2500", 1531 .parent = TYPE_ASPEED_SMC, 1532 .class_init = aspeed_2500_spi2_class_init, 1533 }; 1534 1535 /* 1536 * The Segment Registers of the AST2600 have a 1MB unit. The address 1537 * range of a flash SPI peripheral is encoded with offsets in the overall 1538 * controller window. The previous SoC AST2400 and AST2500 used 1539 * absolute addresses. Only bits [27:20] are relevant and the end 1540 * address is an upper bound limit. 1541 */ 1542 #define AST2600_SEG_ADDR_MASK 0x0ff00000 1543 1544 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, 1545 const AspeedSegments *seg) 1546 { 1547 uint32_t reg = 0; 1548 1549 /* Disabled segments have a nil register */ 1550 if (!seg->size) { 1551 return 0; 1552 } 1553 1554 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ 1555 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ 1556 return reg; 1557 } 1558 1559 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, 1560 uint32_t reg, AspeedSegments *seg) 1561 { 1562 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; 1563 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; 1564 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1565 1566 if (reg) { 1567 seg->addr = asc->flash_window_base + start_offset; 1568 seg->size = end_offset + MiB - start_offset; 1569 } else { 1570 seg->addr = asc->flash_window_base; 1571 seg->size = 0; 1572 } 1573 } 1574 1575 static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = { 1576 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | 1577 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 | 1578 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2), 1579 }; 1580 1581 static const AspeedSegments aspeed_2600_fmc_segments[] = { 1582 { 0x0, 128 * MiB }, /* start address is readonly */ 1583 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ 1584 { 0x0, 0 }, /* disabled */ 1585 }; 1586 1587 static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data) 1588 { 1589 DeviceClass *dc = DEVICE_CLASS(klass); 1590 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1591 1592 dc->desc = "Aspeed 2600 FMC Controller"; 1593 asc->r_conf = R_CONF; 1594 asc->r_ce_ctrl = R_CE_CTRL; 1595 asc->r_ctrl0 = R_CTRL0; 1596 asc->r_timings = R_TIMINGS; 1597 asc->nregs_timings = 1; 1598 asc->conf_enable_w0 = CONF_ENABLE_W0; 1599 asc->cs_num_max = 3; 1600 asc->segments = aspeed_2600_fmc_segments; 1601 asc->segment_addr_mask = 0x0ff00ff0; 1602 asc->resets = aspeed_2600_fmc_resets; 1603 asc->flash_window_base = 0x20000000; 1604 asc->flash_window_size = 0x10000000; 1605 asc->features = ASPEED_SMC_FEATURE_DMA | 1606 ASPEED_SMC_FEATURE_WDT_CONTROL; 1607 asc->dma_flash_mask = 0x0FFFFFFC; 1608 asc->dma_dram_mask = 0x3FFFFFFC; 1609 asc->nregs = ASPEED_SMC_R_MAX; 1610 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1611 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1612 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1613 } 1614 1615 static const TypeInfo aspeed_2600_fmc_info = { 1616 .name = "aspeed.fmc-ast2600", 1617 .parent = TYPE_ASPEED_SMC, 1618 .class_init = aspeed_2600_fmc_class_init, 1619 }; 1620 1621 static const AspeedSegments aspeed_2600_spi1_segments[] = { 1622 { 0x0, 128 * MiB }, /* start address is readonly */ 1623 { 0x0, 0 }, /* disabled */ 1624 }; 1625 1626 static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data) 1627 { 1628 DeviceClass *dc = DEVICE_CLASS(klass); 1629 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1630 1631 dc->desc = "Aspeed 2600 SPI1 Controller"; 1632 asc->r_conf = R_CONF; 1633 asc->r_ce_ctrl = R_CE_CTRL; 1634 asc->r_ctrl0 = R_CTRL0; 1635 asc->r_timings = R_TIMINGS; 1636 asc->nregs_timings = 2; 1637 asc->conf_enable_w0 = CONF_ENABLE_W0; 1638 asc->cs_num_max = 2; 1639 asc->segments = aspeed_2600_spi1_segments; 1640 asc->segment_addr_mask = 0x0ff00ff0; 1641 asc->flash_window_base = 0x30000000; 1642 asc->flash_window_size = 0x10000000; 1643 asc->features = ASPEED_SMC_FEATURE_DMA | 1644 ASPEED_SMC_FEATURE_DMA_GRANT; 1645 asc->dma_flash_mask = 0x0FFFFFFC; 1646 asc->dma_dram_mask = 0x3FFFFFFC; 1647 asc->nregs = ASPEED_SMC_R_MAX; 1648 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1649 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1650 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1651 } 1652 1653 static const TypeInfo aspeed_2600_spi1_info = { 1654 .name = "aspeed.spi1-ast2600", 1655 .parent = TYPE_ASPEED_SMC, 1656 .class_init = aspeed_2600_spi1_class_init, 1657 }; 1658 1659 static const AspeedSegments aspeed_2600_spi2_segments[] = { 1660 { 0x0, 128 * MiB }, /* start address is readonly */ 1661 { 0x0, 0 }, /* disabled */ 1662 { 0x0, 0 }, /* disabled */ 1663 }; 1664 1665 static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data) 1666 { 1667 DeviceClass *dc = DEVICE_CLASS(klass); 1668 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1669 1670 dc->desc = "Aspeed 2600 SPI2 Controller"; 1671 asc->r_conf = R_CONF; 1672 asc->r_ce_ctrl = R_CE_CTRL; 1673 asc->r_ctrl0 = R_CTRL0; 1674 asc->r_timings = R_TIMINGS; 1675 asc->nregs_timings = 3; 1676 asc->conf_enable_w0 = CONF_ENABLE_W0; 1677 asc->cs_num_max = 3; 1678 asc->segments = aspeed_2600_spi2_segments; 1679 asc->segment_addr_mask = 0x0ff00ff0; 1680 asc->flash_window_base = 0x50000000; 1681 asc->flash_window_size = 0x10000000; 1682 asc->features = ASPEED_SMC_FEATURE_DMA | 1683 ASPEED_SMC_FEATURE_DMA_GRANT; 1684 asc->dma_flash_mask = 0x0FFFFFFC; 1685 asc->dma_dram_mask = 0x3FFFFFFC; 1686 asc->nregs = ASPEED_SMC_R_MAX; 1687 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1688 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1689 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1690 } 1691 1692 static const TypeInfo aspeed_2600_spi2_info = { 1693 .name = "aspeed.spi2-ast2600", 1694 .parent = TYPE_ASPEED_SMC, 1695 .class_init = aspeed_2600_spi2_class_init, 1696 }; 1697 1698 /* 1699 * The FMC Segment Registers of the AST1030 have a 512KB unit. 1700 * Only bits [27:19] are used for decoding. 1701 */ 1702 #define AST1030_SEG_ADDR_MASK 0x0ff80000 1703 1704 static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s, 1705 const AspeedSegments *seg) 1706 { 1707 uint32_t reg = 0; 1708 1709 /* Disabled segments have a nil register */ 1710 if (!seg->size) { 1711 return 0; 1712 } 1713 1714 reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ 1715 reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ 1716 return reg; 1717 } 1718 1719 static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s, 1720 uint32_t reg, AspeedSegments *seg) 1721 { 1722 uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK; 1723 uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK; 1724 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1725 1726 if (reg) { 1727 seg->addr = asc->flash_window_base + start_offset; 1728 seg->size = end_offset + (512 * KiB) - start_offset; 1729 } else { 1730 seg->addr = asc->flash_window_base; 1731 seg->size = 0; 1732 } 1733 } 1734 1735 static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = { 1736 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | 1737 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), 1738 }; 1739 1740 static const AspeedSegments aspeed_1030_fmc_segments[] = { 1741 { 0x0, 128 * MiB }, /* start address is readonly */ 1742 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ 1743 { 0x0, 0 }, /* disabled */ 1744 }; 1745 1746 static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data) 1747 { 1748 DeviceClass *dc = DEVICE_CLASS(klass); 1749 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1750 1751 dc->desc = "Aspeed 1030 FMC Controller"; 1752 asc->r_conf = R_CONF; 1753 asc->r_ce_ctrl = R_CE_CTRL; 1754 asc->r_ctrl0 = R_CTRL0; 1755 asc->r_timings = R_TIMINGS; 1756 asc->nregs_timings = 2; 1757 asc->conf_enable_w0 = CONF_ENABLE_W0; 1758 asc->cs_num_max = 2; 1759 asc->segments = aspeed_1030_fmc_segments; 1760 asc->segment_addr_mask = 0x0ff80ff8; 1761 asc->resets = aspeed_1030_fmc_resets; 1762 asc->flash_window_base = 0x80000000; 1763 asc->flash_window_size = 0x10000000; 1764 asc->features = ASPEED_SMC_FEATURE_DMA; 1765 asc->dma_flash_mask = 0x0FFFFFFC; 1766 asc->dma_dram_mask = 0x000BFFFC; 1767 asc->nregs = ASPEED_SMC_R_MAX; 1768 asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; 1769 asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; 1770 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1771 } 1772 1773 static const TypeInfo aspeed_1030_fmc_info = { 1774 .name = "aspeed.fmc-ast1030", 1775 .parent = TYPE_ASPEED_SMC, 1776 .class_init = aspeed_1030_fmc_class_init, 1777 }; 1778 1779 static const AspeedSegments aspeed_1030_spi1_segments[] = { 1780 { 0x0, 128 * MiB }, /* start address is readonly */ 1781 { 0x0, 0 }, /* disabled */ 1782 }; 1783 1784 static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data) 1785 { 1786 DeviceClass *dc = DEVICE_CLASS(klass); 1787 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1788 1789 dc->desc = "Aspeed 1030 SPI1 Controller"; 1790 asc->r_conf = R_CONF; 1791 asc->r_ce_ctrl = R_CE_CTRL; 1792 asc->r_ctrl0 = R_CTRL0; 1793 asc->r_timings = R_TIMINGS; 1794 asc->nregs_timings = 2; 1795 asc->conf_enable_w0 = CONF_ENABLE_W0; 1796 asc->cs_num_max = 2; 1797 asc->segments = aspeed_1030_spi1_segments; 1798 asc->segment_addr_mask = 0x0ff00ff0; 1799 asc->flash_window_base = 0x90000000; 1800 asc->flash_window_size = 0x10000000; 1801 asc->features = ASPEED_SMC_FEATURE_DMA; 1802 asc->dma_flash_mask = 0x0FFFFFFC; 1803 asc->dma_dram_mask = 0x000BFFFC; 1804 asc->nregs = ASPEED_SMC_R_MAX; 1805 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1806 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1807 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1808 } 1809 1810 static const TypeInfo aspeed_1030_spi1_info = { 1811 .name = "aspeed.spi1-ast1030", 1812 .parent = TYPE_ASPEED_SMC, 1813 .class_init = aspeed_1030_spi1_class_init, 1814 }; 1815 static const AspeedSegments aspeed_1030_spi2_segments[] = { 1816 { 0x0, 128 * MiB }, /* start address is readonly */ 1817 { 0x0, 0 }, /* disabled */ 1818 }; 1819 1820 static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data) 1821 { 1822 DeviceClass *dc = DEVICE_CLASS(klass); 1823 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1824 1825 dc->desc = "Aspeed 1030 SPI2 Controller"; 1826 asc->r_conf = R_CONF; 1827 asc->r_ce_ctrl = R_CE_CTRL; 1828 asc->r_ctrl0 = R_CTRL0; 1829 asc->r_timings = R_TIMINGS; 1830 asc->nregs_timings = 2; 1831 asc->conf_enable_w0 = CONF_ENABLE_W0; 1832 asc->cs_num_max = 2; 1833 asc->segments = aspeed_1030_spi2_segments; 1834 asc->segment_addr_mask = 0x0ff00ff0; 1835 asc->flash_window_base = 0xb0000000; 1836 asc->flash_window_size = 0x10000000; 1837 asc->features = ASPEED_SMC_FEATURE_DMA; 1838 asc->dma_flash_mask = 0x0FFFFFFC; 1839 asc->dma_dram_mask = 0x000BFFFC; 1840 asc->nregs = ASPEED_SMC_R_MAX; 1841 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1842 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1843 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1844 } 1845 1846 static const TypeInfo aspeed_1030_spi2_info = { 1847 .name = "aspeed.spi2-ast1030", 1848 .parent = TYPE_ASPEED_SMC, 1849 .class_init = aspeed_1030_spi2_class_init, 1850 }; 1851 1852 static void aspeed_smc_register_types(void) 1853 { 1854 type_register_static(&aspeed_smc_flash_info); 1855 type_register_static(&aspeed_smc_info); 1856 type_register_static(&aspeed_2400_smc_info); 1857 type_register_static(&aspeed_2400_fmc_info); 1858 type_register_static(&aspeed_2400_spi1_info); 1859 type_register_static(&aspeed_2500_fmc_info); 1860 type_register_static(&aspeed_2500_spi1_info); 1861 type_register_static(&aspeed_2500_spi2_info); 1862 type_register_static(&aspeed_2600_fmc_info); 1863 type_register_static(&aspeed_2600_spi1_info); 1864 type_register_static(&aspeed_2600_spi2_info); 1865 type_register_static(&aspeed_1030_fmc_info); 1866 type_register_static(&aspeed_1030_spi1_info); 1867 type_register_static(&aspeed_1030_spi2_info); 1868 } 1869 1870 type_init(aspeed_smc_register_types)