sun4u.c (27345B)
1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "qemu/datadir.h" 30 #include "cpu.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/pci-host/sabre.h" 37 #include "hw/char/serial.h" 38 #include "hw/char/parallel.h" 39 #include "hw/rtc/m48t59.h" 40 #include "migration/vmstate.h" 41 #include "hw/input/i8042.h" 42 #include "hw/block/fdc.h" 43 #include "net/net.h" 44 #include "qemu/timer.h" 45 #include "sysemu/runstate.h" 46 #include "sysemu/sysemu.h" 47 #include "hw/boards.h" 48 #include "hw/nvram/sun_nvram.h" 49 #include "hw/nvram/chrp_nvram.h" 50 #include "hw/sparc/sparc64.h" 51 #include "hw/nvram/fw_cfg.h" 52 #include "hw/sysbus.h" 53 #include "hw/ide/pci.h" 54 #include "hw/loader.h" 55 #include "hw/fw-path-provider.h" 56 #include "elf.h" 57 #include "trace.h" 58 #include "qom/object.h" 59 60 #define KERNEL_LOAD_ADDR 0x00404000 61 #define CMDLINE_ADDR 0x003ff000 62 #define PROM_SIZE_MAX (4 * MiB) 63 #define PROM_VADDR 0x000ffd00000ULL 64 #define PBM_SPECIAL_BASE 0x1fe00000000ULL 65 #define PBM_MEM_BASE 0x1ff00000000ULL 66 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) 67 #define PROM_FILENAME "openbios-sparc64" 68 #define NVRAM_SIZE 0x2000 69 #define BIOS_CFG_IOPORT 0x510 70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 73 74 #define IVEC_MAX 0x40 75 76 struct hwdef { 77 uint16_t machine_id; 78 uint64_t prom_addr; 79 uint64_t console_serial_base; 80 }; 81 82 struct EbusState { 83 /*< private >*/ 84 PCIDevice parent_obj; 85 86 ISABus *isa_bus; 87 qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; 88 uint64_t console_serial_base; 89 MemoryRegion bar0; 90 MemoryRegion bar1; 91 }; 92 93 #define TYPE_EBUS "ebus" 94 OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS) 95 96 const char *fw_cfg_arch_key_name(uint16_t key) 97 { 98 static const struct { 99 uint16_t key; 100 const char *name; 101 } fw_cfg_arch_wellknown_keys[] = { 102 {FW_CFG_SPARC64_WIDTH, "width"}, 103 {FW_CFG_SPARC64_HEIGHT, "height"}, 104 {FW_CFG_SPARC64_DEPTH, "depth"}, 105 }; 106 107 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 108 if (fw_cfg_arch_wellknown_keys[i].key == key) { 109 return fw_cfg_arch_wellknown_keys[i].name; 110 } 111 } 112 return NULL; 113 } 114 115 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 116 Error **errp) 117 { 118 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 119 } 120 121 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 122 const char *arch, ram_addr_t RAM_size, 123 const char *boot_devices, 124 uint32_t kernel_image, uint32_t kernel_size, 125 const char *cmdline, 126 uint32_t initrd_image, uint32_t initrd_size, 127 uint32_t NVRAM_image, 128 int width, int height, int depth, 129 const uint8_t *macaddr) 130 { 131 unsigned int i; 132 int sysp_end; 133 uint8_t image[0x1ff0]; 134 NvramClass *k = NVRAM_GET_CLASS(nvram); 135 136 memset(image, '\0', sizeof(image)); 137 138 /* OpenBIOS nvram variables partition */ 139 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 140 141 /* Free space partition */ 142 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 143 144 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 145 146 for (i = 0; i < sizeof(image); i++) { 147 (k->write)(nvram, i, image[i]); 148 } 149 150 return 0; 151 } 152 153 static uint64_t sun4u_load_kernel(const char *kernel_filename, 154 const char *initrd_filename, 155 ram_addr_t RAM_size, uint64_t *initrd_size, 156 uint64_t *initrd_addr, uint64_t *kernel_addr, 157 uint64_t *kernel_entry) 158 { 159 int linux_boot; 160 unsigned int i; 161 long kernel_size; 162 uint8_t *ptr; 163 uint64_t kernel_top = 0; 164 165 linux_boot = (kernel_filename != NULL); 166 167 kernel_size = 0; 168 if (linux_boot) { 169 int bswap_needed; 170 171 #ifdef BSWAP_NEEDED 172 bswap_needed = 1; 173 #else 174 bswap_needed = 0; 175 #endif 176 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, 177 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0, 178 0); 179 if (kernel_size < 0) { 180 *kernel_addr = KERNEL_LOAD_ADDR; 181 *kernel_entry = KERNEL_LOAD_ADDR; 182 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 183 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 184 TARGET_PAGE_SIZE); 185 } 186 if (kernel_size < 0) { 187 kernel_size = load_image_targphys(kernel_filename, 188 KERNEL_LOAD_ADDR, 189 RAM_size - KERNEL_LOAD_ADDR); 190 } 191 if (kernel_size < 0) { 192 error_report("could not load kernel '%s'", kernel_filename); 193 exit(1); 194 } 195 /* load initrd above kernel */ 196 *initrd_size = 0; 197 if (initrd_filename && kernel_top) { 198 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 199 200 *initrd_size = load_image_targphys(initrd_filename, 201 *initrd_addr, 202 RAM_size - *initrd_addr); 203 if ((int)*initrd_size < 0) { 204 error_report("could not load initial ram disk '%s'", 205 initrd_filename); 206 exit(1); 207 } 208 } 209 if (*initrd_size > 0) { 210 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 211 ptr = rom_ptr(*kernel_addr + i, 32); 212 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 213 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 214 stl_p(ptr + 28, *initrd_size); 215 break; 216 } 217 } 218 } 219 } 220 return kernel_size; 221 } 222 223 typedef struct ResetData { 224 SPARCCPU *cpu; 225 uint64_t prom_addr; 226 } ResetData; 227 228 #define TYPE_SUN4U_POWER "power" 229 OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER) 230 231 struct PowerDevice { 232 SysBusDevice parent_obj; 233 234 MemoryRegion power_mmio; 235 }; 236 237 /* Power */ 238 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) 239 { 240 return 0; 241 } 242 243 static void power_mem_write(void *opaque, hwaddr addr, 244 uint64_t val, unsigned size) 245 { 246 /* According to a real Ultra 5, bit 24 controls the power */ 247 if (val & 0x1000000) { 248 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 249 } 250 } 251 252 static const MemoryRegionOps power_mem_ops = { 253 .read = power_mem_read, 254 .write = power_mem_write, 255 .endianness = DEVICE_NATIVE_ENDIAN, 256 .valid = { 257 .min_access_size = 4, 258 .max_access_size = 4, 259 }, 260 }; 261 262 static void power_realize(DeviceState *dev, Error **errp) 263 { 264 PowerDevice *d = SUN4U_POWER(dev); 265 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 266 267 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, 268 "power", sizeof(uint32_t)); 269 270 sysbus_init_mmio(sbd, &d->power_mmio); 271 } 272 273 static void power_class_init(ObjectClass *klass, void *data) 274 { 275 DeviceClass *dc = DEVICE_CLASS(klass); 276 277 dc->realize = power_realize; 278 } 279 280 static const TypeInfo power_info = { 281 .name = TYPE_SUN4U_POWER, 282 .parent = TYPE_SYS_BUS_DEVICE, 283 .instance_size = sizeof(PowerDevice), 284 .class_init = power_class_init, 285 }; 286 287 static void ebus_isa_irq_handler(void *opaque, int n, int level) 288 { 289 EbusState *s = EBUS(opaque); 290 qemu_irq irq = s->isa_bus_irqs[n]; 291 292 /* Pass ISA bus IRQs onto their gpio equivalent */ 293 trace_ebus_isa_irq_handler(n, level); 294 if (irq) { 295 qemu_set_irq(irq, level); 296 } 297 } 298 299 /* EBUS (Eight bit bus) bridge */ 300 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 301 { 302 EbusState *s = EBUS(pci_dev); 303 ISADevice *isa_dev; 304 SysBusDevice *sbd; 305 DeviceState *dev; 306 qemu_irq *isa_irq; 307 DriveInfo *fd[MAX_FD]; 308 int i; 309 310 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 311 pci_address_space_io(pci_dev), errp); 312 if (!s->isa_bus) { 313 error_setg(errp, "unable to instantiate EBUS ISA bus"); 314 return; 315 } 316 317 /* ISA bus */ 318 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 319 isa_bus_irqs(s->isa_bus, isa_irq); 320 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", 321 ISA_NUM_IRQS); 322 323 /* Serial ports */ 324 i = 0; 325 if (s->console_serial_base) { 326 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 327 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); 328 i++; 329 } 330 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); 331 332 /* Parallel ports */ 333 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 334 335 /* Keyboard */ 336 isa_create_simple(s->isa_bus, TYPE_I8042); 337 338 /* Floppy */ 339 for (i = 0; i < MAX_FD; i++) { 340 fd[i] = drive_get(IF_FLOPPY, 0, i); 341 } 342 isa_dev = isa_new(TYPE_ISA_FDC); 343 dev = DEVICE(isa_dev); 344 qdev_prop_set_uint32(dev, "dma", -1); 345 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal); 346 isa_fdc_init_drives(isa_dev, fd); 347 348 /* Power */ 349 dev = qdev_new(TYPE_SUN4U_POWER); 350 sbd = SYS_BUS_DEVICE(dev); 351 sysbus_realize_and_unref(sbd, &error_fatal); 352 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 353 sysbus_mmio_get_region(sbd, 0)); 354 355 /* PCI */ 356 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 357 pci_dev->config[0x05] = 0x00; 358 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 359 pci_dev->config[0x07] = 0x03; // status = medium devsel 360 pci_dev->config[0x09] = 0x00; // programming i/f 361 pci_dev->config[0x0D] = 0x0a; // latency_timer 362 363 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 364 0, 0x1000000); 365 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 366 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 367 0, 0x8000); 368 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 369 } 370 371 static Property ebus_properties[] = { 372 DEFINE_PROP_UINT64("console-serial-base", EbusState, 373 console_serial_base, 0), 374 DEFINE_PROP_END_OF_LIST(), 375 }; 376 377 static void ebus_class_init(ObjectClass *klass, void *data) 378 { 379 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 380 DeviceClass *dc = DEVICE_CLASS(klass); 381 382 k->realize = ebus_realize; 383 k->vendor_id = PCI_VENDOR_ID_SUN; 384 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 385 k->revision = 0x01; 386 k->class_id = PCI_CLASS_BRIDGE_OTHER; 387 device_class_set_props(dc, ebus_properties); 388 } 389 390 static const TypeInfo ebus_info = { 391 .name = TYPE_EBUS, 392 .parent = TYPE_PCI_DEVICE, 393 .class_init = ebus_class_init, 394 .instance_size = sizeof(EbusState), 395 .interfaces = (InterfaceInfo[]) { 396 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 397 { }, 398 }, 399 }; 400 401 #define TYPE_OPENPROM "openprom" 402 typedef struct PROMState PROMState; 403 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 404 TYPE_OPENPROM) 405 406 struct PROMState { 407 SysBusDevice parent_obj; 408 409 MemoryRegion prom; 410 }; 411 412 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 413 { 414 hwaddr *base_addr = (hwaddr *)opaque; 415 return addr + *base_addr - PROM_VADDR; 416 } 417 418 /* Boot PROM (OpenBIOS) */ 419 static void prom_init(hwaddr addr, const char *bios_name) 420 { 421 DeviceState *dev; 422 SysBusDevice *s; 423 char *filename; 424 int ret; 425 426 dev = qdev_new(TYPE_OPENPROM); 427 s = SYS_BUS_DEVICE(dev); 428 sysbus_realize_and_unref(s, &error_fatal); 429 430 sysbus_mmio_map(s, 0, addr); 431 432 /* load boot prom */ 433 if (bios_name == NULL) { 434 bios_name = PROM_FILENAME; 435 } 436 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 437 if (filename) { 438 ret = load_elf(filename, NULL, translate_prom_address, &addr, 439 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 440 if (ret < 0 || ret > PROM_SIZE_MAX) { 441 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 442 } 443 g_free(filename); 444 } else { 445 ret = -1; 446 } 447 if (ret < 0 || ret > PROM_SIZE_MAX) { 448 error_report("could not load prom '%s'", bios_name); 449 exit(1); 450 } 451 } 452 453 static void prom_realize(DeviceState *ds, Error **errp) 454 { 455 PROMState *s = OPENPROM(ds); 456 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 457 Error *local_err = NULL; 458 459 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", 460 PROM_SIZE_MAX, &local_err); 461 if (local_err) { 462 error_propagate(errp, local_err); 463 return; 464 } 465 466 vmstate_register_ram_global(&s->prom); 467 memory_region_set_readonly(&s->prom, true); 468 sysbus_init_mmio(dev, &s->prom); 469 } 470 471 static Property prom_properties[] = { 472 {/* end of property list */}, 473 }; 474 475 static void prom_class_init(ObjectClass *klass, void *data) 476 { 477 DeviceClass *dc = DEVICE_CLASS(klass); 478 479 device_class_set_props(dc, prom_properties); 480 dc->realize = prom_realize; 481 } 482 483 static const TypeInfo prom_info = { 484 .name = TYPE_OPENPROM, 485 .parent = TYPE_SYS_BUS_DEVICE, 486 .instance_size = sizeof(PROMState), 487 .class_init = prom_class_init, 488 }; 489 490 491 #define TYPE_SUN4U_MEMORY "memory" 492 typedef struct RamDevice RamDevice; 493 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM, 494 TYPE_SUN4U_MEMORY) 495 496 struct RamDevice { 497 SysBusDevice parent_obj; 498 499 MemoryRegion ram; 500 uint64_t size; 501 }; 502 503 /* System RAM */ 504 static void ram_realize(DeviceState *dev, Error **errp) 505 { 506 RamDevice *d = SUN4U_RAM(dev); 507 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 508 509 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 510 &error_fatal); 511 vmstate_register_ram_global(&d->ram); 512 sysbus_init_mmio(sbd, &d->ram); 513 } 514 515 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 516 { 517 DeviceState *dev; 518 SysBusDevice *s; 519 RamDevice *d; 520 521 /* allocate RAM */ 522 dev = qdev_new(TYPE_SUN4U_MEMORY); 523 s = SYS_BUS_DEVICE(dev); 524 525 d = SUN4U_RAM(dev); 526 d->size = RAM_size; 527 sysbus_realize_and_unref(s, &error_fatal); 528 529 sysbus_mmio_map(s, 0, addr); 530 } 531 532 static Property ram_properties[] = { 533 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 534 DEFINE_PROP_END_OF_LIST(), 535 }; 536 537 static void ram_class_init(ObjectClass *klass, void *data) 538 { 539 DeviceClass *dc = DEVICE_CLASS(klass); 540 541 dc->realize = ram_realize; 542 device_class_set_props(dc, ram_properties); 543 } 544 545 static const TypeInfo ram_info = { 546 .name = TYPE_SUN4U_MEMORY, 547 .parent = TYPE_SYS_BUS_DEVICE, 548 .instance_size = sizeof(RamDevice), 549 .class_init = ram_class_init, 550 }; 551 552 static void sun4uv_init(MemoryRegion *address_space_mem, 553 MachineState *machine, 554 const struct hwdef *hwdef) 555 { 556 SPARCCPU *cpu; 557 Nvram *nvram; 558 unsigned int i; 559 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 560 SabreState *sabre; 561 PCIBus *pci_bus, *pci_busA, *pci_busB; 562 PCIDevice *ebus, *pci_dev; 563 SysBusDevice *s; 564 DeviceState *iommu, *dev; 565 FWCfgState *fw_cfg; 566 NICInfo *nd; 567 MACAddr macaddr; 568 bool onboard_nic; 569 570 /* init CPUs */ 571 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 572 573 /* IOMMU */ 574 iommu = qdev_new(TYPE_SUN4U_IOMMU); 575 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal); 576 577 /* set up devices */ 578 ram_init(0, machine->ram_size); 579 580 prom_init(hwdef->prom_addr, machine->firmware); 581 582 /* Init sabre (PCI host bridge) */ 583 sabre = SABRE(qdev_new(TYPE_SABRE)); 584 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 585 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 586 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu), 587 &error_abort); 588 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); 589 590 /* sabre_config */ 591 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE); 592 /* PCI configuration space */ 593 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL); 594 /* pci_ioport */ 595 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL); 596 597 /* Wire up PCI interrupts to CPU */ 598 for (i = 0; i < IVEC_MAX; i++) { 599 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, 600 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 601 } 602 603 pci_bus = PCI_HOST_BRIDGE(sabre)->bus; 604 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); 605 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); 606 607 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is 608 reserved (leaving no slots free after on-board devices) however slots 609 0-3 are free on busB */ 610 pci_bus->slot_reserved_mask = 0xfffffffc; 611 pci_busA->slot_reserved_mask = 0xfffffff1; 612 pci_busB->slot_reserved_mask = 0xfffffff0; 613 614 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS); 615 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 616 hwdef->console_serial_base); 617 pci_realize_and_unref(ebus, pci_busA, &error_fatal); 618 619 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ 620 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 621 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); 622 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 623 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); 624 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 625 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); 626 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 627 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); 628 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 629 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); 630 631 switch (vga_interface_type) { 632 case VGA_STD: 633 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 634 vga_interface_created = true; 635 break; 636 case VGA_NONE: 637 break; 638 default: 639 abort(); /* Should not happen - types are checked in vl.c already */ 640 } 641 642 memset(&macaddr, 0, sizeof(MACAddr)); 643 onboard_nic = false; 644 for (i = 0; i < nb_nics; i++) { 645 PCIBus *bus; 646 nd = &nd_table[i]; 647 648 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 649 if (!onboard_nic) { 650 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), 651 true, "sunhme"); 652 bus = pci_busA; 653 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 654 onboard_nic = true; 655 } else { 656 pci_dev = pci_new(-1, "sunhme"); 657 bus = pci_busB; 658 } 659 } else { 660 pci_dev = pci_new(-1, nd->model); 661 bus = pci_busB; 662 } 663 664 dev = &pci_dev->qdev; 665 qdev_set_nic_properties(dev, nd); 666 pci_realize_and_unref(pci_dev, bus, &error_fatal); 667 } 668 669 /* If we don't have an onboard NIC, grab a default MAC address so that 670 * we have a valid machine id */ 671 if (!onboard_nic) { 672 qemu_macaddr_default_if_unset(&macaddr); 673 } 674 675 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide"); 676 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 677 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); 678 pci_ide_create_devs(pci_dev); 679 680 /* Map NVRAM into I/O (ebus) space */ 681 dev = qdev_new("sysbus-m48t59"); 682 qdev_prop_set_int32(dev, "base-year", 1968); 683 s = SYS_BUS_DEVICE(dev); 684 sysbus_realize_and_unref(s, &error_fatal); 685 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 686 sysbus_mmio_get_region(s, 0)); 687 nvram = NVRAM(dev); 688 689 initrd_size = 0; 690 initrd_addr = 0; 691 kernel_size = sun4u_load_kernel(machine->kernel_filename, 692 machine->initrd_filename, 693 machine->ram_size, &initrd_size, &initrd_addr, 694 &kernel_addr, &kernel_entry); 695 696 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 697 machine->boot_config.order, 698 kernel_addr, kernel_size, 699 machine->kernel_cmdline, 700 initrd_addr, initrd_size, 701 /* XXX: need an option to load a NVRAM image */ 702 0, 703 graphic_width, graphic_height, graphic_depth, 704 (uint8_t *)&macaddr); 705 706 dev = qdev_new(TYPE_FW_CFG_IO); 707 qdev_prop_set_bit(dev, "dma_enabled", false); 708 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); 709 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 710 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 711 &FW_CFG_IO(dev)->comb_iomem); 712 713 fw_cfg = FW_CFG(dev); 714 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 715 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 716 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 717 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 718 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 719 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 720 if (machine->kernel_cmdline) { 721 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 722 strlen(machine->kernel_cmdline) + 1); 723 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 724 } else { 725 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 726 } 727 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 728 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 729 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); 730 731 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 732 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 733 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 734 735 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 736 } 737 738 enum { 739 sun4u_id = 0, 740 sun4v_id = 64, 741 }; 742 743 /* 744 * Implementation of an interface to adjust firmware path 745 * for the bootindex property handling. 746 */ 747 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, 748 DeviceState *dev) 749 { 750 PCIDevice *pci; 751 752 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { 753 pci = PCI_DEVICE(dev); 754 755 if (PCI_FUNC(pci->devfn)) { 756 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), 757 PCI_FUNC(pci->devfn)); 758 } else { 759 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); 760 } 761 } 762 763 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 764 return g_strdup("disk"); 765 } 766 767 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 768 return g_strdup("cdrom"); 769 } 770 771 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 772 return g_strdup("disk"); 773 } 774 775 return NULL; 776 } 777 778 static const struct hwdef hwdefs[] = { 779 /* Sun4u generic PC-like machine */ 780 { 781 .machine_id = sun4u_id, 782 .prom_addr = 0x1fff0000000ULL, 783 .console_serial_base = 0, 784 }, 785 /* Sun4v generic PC-like machine */ 786 { 787 .machine_id = sun4v_id, 788 .prom_addr = 0x1fff0000000ULL, 789 .console_serial_base = 0, 790 }, 791 }; 792 793 /* Sun4u hardware initialisation */ 794 static void sun4u_init(MachineState *machine) 795 { 796 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 797 } 798 799 /* Sun4v hardware initialisation */ 800 static void sun4v_init(MachineState *machine) 801 { 802 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 803 } 804 805 static void sun4u_class_init(ObjectClass *oc, void *data) 806 { 807 MachineClass *mc = MACHINE_CLASS(oc); 808 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 809 810 mc->desc = "Sun4u platform"; 811 mc->init = sun4u_init; 812 mc->block_default_type = IF_IDE; 813 mc->max_cpus = 1; /* XXX for now */ 814 mc->is_default = true; 815 mc->default_boot_order = "c"; 816 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 817 mc->ignore_boot_device_suffixes = true; 818 mc->default_display = "std"; 819 fwc->get_dev_path = sun4u_fw_dev_path; 820 } 821 822 static const TypeInfo sun4u_type = { 823 .name = MACHINE_TYPE_NAME("sun4u"), 824 .parent = TYPE_MACHINE, 825 .class_init = sun4u_class_init, 826 .interfaces = (InterfaceInfo[]) { 827 { TYPE_FW_PATH_PROVIDER }, 828 { } 829 }, 830 }; 831 832 static void sun4v_class_init(ObjectClass *oc, void *data) 833 { 834 MachineClass *mc = MACHINE_CLASS(oc); 835 836 mc->desc = "Sun4v platform"; 837 mc->init = sun4v_init; 838 mc->block_default_type = IF_IDE; 839 mc->max_cpus = 1; /* XXX for now */ 840 mc->default_boot_order = "c"; 841 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 842 mc->default_display = "std"; 843 } 844 845 static const TypeInfo sun4v_type = { 846 .name = MACHINE_TYPE_NAME("sun4v"), 847 .parent = TYPE_MACHINE, 848 .class_init = sun4v_class_init, 849 }; 850 851 static void sun4u_register_types(void) 852 { 853 type_register_static(&power_info); 854 type_register_static(&ebus_info); 855 type_register_static(&prom_info); 856 type_register_static(&ram_info); 857 858 type_register_static(&sun4u_type); 859 type_register_static(&sun4v_type); 860 } 861 862 type_init(sun4u_register_types)