allwinner-sdhost.c (30529B)
1 /* 2 * Allwinner (sun4i and above) SD Host Controller emulation 3 * 4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "qemu/units.h" 24 #include "qapi/error.h" 25 #include "sysemu/blockdev.h" 26 #include "sysemu/dma.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/irq.h" 29 #include "hw/sd/allwinner-sdhost.h" 30 #include "migration/vmstate.h" 31 #include "trace.h" 32 #include "qom/object.h" 33 34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus" 35 /* This is reusing the SDBus typedef from SD_BUS */ 36 DECLARE_INSTANCE_CHECKER(SDBus, AW_SDHOST_BUS, 37 TYPE_AW_SDHOST_BUS) 38 39 /* SD Host register offsets */ 40 enum { 41 REG_SD_GCTL = 0x00, /* Global Control */ 42 REG_SD_CKCR = 0x04, /* Clock Control */ 43 REG_SD_TMOR = 0x08, /* Timeout */ 44 REG_SD_BWDR = 0x0C, /* Bus Width */ 45 REG_SD_BKSR = 0x10, /* Block Size */ 46 REG_SD_BYCR = 0x14, /* Byte Count */ 47 REG_SD_CMDR = 0x18, /* Command */ 48 REG_SD_CAGR = 0x1C, /* Command Argument */ 49 REG_SD_RESP0 = 0x20, /* Response Zero */ 50 REG_SD_RESP1 = 0x24, /* Response One */ 51 REG_SD_RESP2 = 0x28, /* Response Two */ 52 REG_SD_RESP3 = 0x2C, /* Response Three */ 53 REG_SD_IMKR = 0x30, /* Interrupt Mask */ 54 REG_SD_MISR = 0x34, /* Masked Interrupt Status */ 55 REG_SD_RISR = 0x38, /* Raw Interrupt Status */ 56 REG_SD_STAR = 0x3C, /* Status */ 57 REG_SD_FWLR = 0x40, /* FIFO Water Level */ 58 REG_SD_FUNS = 0x44, /* FIFO Function Select */ 59 REG_SD_DBGC = 0x50, /* Debug Enable */ 60 REG_SD_A12A = 0x58, /* Auto command 12 argument */ 61 REG_SD_NTSR = 0x5C, /* SD NewTiming Set */ 62 REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */ 63 REG_SD_HWRST = 0x78, /* Hardware Reset Register */ 64 REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */ 65 REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ 66 REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ 67 REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ 68 REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/ 69 REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ 70 REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ 71 REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ 72 REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */ 73 REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */ 74 REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */ 75 REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */ 76 REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */ 77 REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */ 78 REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */ 79 REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */ 80 REG_SD_FIFO = 0x200, /* Read/Write FIFO */ 81 }; 82 83 /* SD Host register flags */ 84 enum { 85 SD_GCTL_FIFO_AC_MOD = (1 << 31), 86 SD_GCTL_DDR_MOD_SEL = (1 << 10), 87 SD_GCTL_CD_DBC_ENB = (1 << 8), 88 SD_GCTL_DMA_ENB = (1 << 5), 89 SD_GCTL_INT_ENB = (1 << 4), 90 SD_GCTL_DMA_RST = (1 << 2), 91 SD_GCTL_FIFO_RST = (1 << 1), 92 SD_GCTL_SOFT_RST = (1 << 0), 93 }; 94 95 enum { 96 SD_CMDR_LOAD = (1 << 31), 97 SD_CMDR_CLKCHANGE = (1 << 21), 98 SD_CMDR_WRITE = (1 << 10), 99 SD_CMDR_AUTOSTOP = (1 << 12), 100 SD_CMDR_DATA = (1 << 9), 101 SD_CMDR_RESPONSE_LONG = (1 << 7), 102 SD_CMDR_RESPONSE = (1 << 6), 103 SD_CMDR_CMDID_MASK = (0x3f), 104 }; 105 106 enum { 107 SD_RISR_CARD_REMOVE = (1 << 31), 108 SD_RISR_CARD_INSERT = (1 << 30), 109 SD_RISR_SDIO_INTR = (1 << 16), 110 SD_RISR_AUTOCMD_DONE = (1 << 14), 111 SD_RISR_DATA_COMPLETE = (1 << 3), 112 SD_RISR_CMD_COMPLETE = (1 << 2), 113 SD_RISR_NO_RESPONSE = (1 << 1), 114 }; 115 116 enum { 117 SD_STAR_FIFO_EMPTY = (1 << 2), 118 SD_STAR_CARD_PRESENT = (1 << 8), 119 SD_STAR_FIFO_LEVEL_1 = (1 << 17), 120 }; 121 122 enum { 123 SD_IDST_INT_SUMMARY = (1 << 8), 124 SD_IDST_RECEIVE_IRQ = (1 << 1), 125 SD_IDST_TRANSMIT_IRQ = (1 << 0), 126 SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8), 127 SD_IDST_WR_MASK = (0x3ff), 128 }; 129 130 /* SD Host register reset values */ 131 enum { 132 REG_SD_GCTL_RST = 0x00000300, 133 REG_SD_CKCR_RST = 0x0, 134 REG_SD_TMOR_RST = 0xFFFFFF40, 135 REG_SD_BWDR_RST = 0x0, 136 REG_SD_BKSR_RST = 0x00000200, 137 REG_SD_BYCR_RST = 0x00000200, 138 REG_SD_CMDR_RST = 0x0, 139 REG_SD_CAGR_RST = 0x0, 140 REG_SD_RESP_RST = 0x0, 141 REG_SD_IMKR_RST = 0x0, 142 REG_SD_MISR_RST = 0x0, 143 REG_SD_RISR_RST = 0x0, 144 REG_SD_STAR_RST = 0x00000100, 145 REG_SD_FWLR_RST = 0x000F0000, 146 REG_SD_FUNS_RST = 0x0, 147 REG_SD_DBGC_RST = 0x0, 148 REG_SD_A12A_RST = 0x0000FFFF, 149 REG_SD_NTSR_RST = 0x00000001, 150 REG_SD_SDBG_RST = 0x0, 151 REG_SD_HWRST_RST = 0x00000001, 152 REG_SD_DMAC_RST = 0x0, 153 REG_SD_DLBA_RST = 0x0, 154 REG_SD_IDST_RST = 0x0, 155 REG_SD_IDIE_RST = 0x0, 156 REG_SD_THLDC_RST = 0x0, 157 REG_SD_DSBD_RST = 0x0, 158 REG_SD_RES_CRC_RST = 0x0, 159 REG_SD_DATA_CRC_RST = 0x0, 160 REG_SD_CRC_STA_RST = 0x0, 161 REG_SD_FIFO_RST = 0x0, 162 }; 163 164 /* Data transfer descriptor for DMA */ 165 typedef struct TransferDescriptor { 166 uint32_t status; /* Status flags */ 167 uint32_t size; /* Data buffer size */ 168 uint32_t addr; /* Data buffer address */ 169 uint32_t next; /* Physical address of next descriptor */ 170 } TransferDescriptor; 171 172 /* Data transfer descriptor flags */ 173 enum { 174 DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */ 175 DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */ 176 DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */ 177 DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */ 178 DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */ 179 DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */ 180 DESC_SIZE_MASK = (0xfffffffc) 181 }; 182 183 static void allwinner_sdhost_update_irq(AwSdHostState *s) 184 { 185 uint32_t irq; 186 187 if (s->global_ctl & SD_GCTL_INT_ENB) { 188 irq = s->irq_status & s->irq_mask; 189 } else { 190 irq = 0; 191 } 192 193 trace_allwinner_sdhost_update_irq(irq); 194 qemu_set_irq(s->irq, irq); 195 } 196 197 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s, 198 uint32_t bytes) 199 { 200 if (s->transfer_cnt > bytes) { 201 s->transfer_cnt -= bytes; 202 } else { 203 s->transfer_cnt = 0; 204 } 205 206 if (!s->transfer_cnt) { 207 s->irq_status |= SD_RISR_DATA_COMPLETE; 208 } 209 } 210 211 static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted) 212 { 213 AwSdHostState *s = AW_SDHOST(dev); 214 215 trace_allwinner_sdhost_set_inserted(inserted); 216 217 if (inserted) { 218 s->irq_status |= SD_RISR_CARD_INSERT; 219 s->irq_status &= ~SD_RISR_CARD_REMOVE; 220 s->status |= SD_STAR_CARD_PRESENT; 221 } else { 222 s->irq_status &= ~SD_RISR_CARD_INSERT; 223 s->irq_status |= SD_RISR_CARD_REMOVE; 224 s->status &= ~SD_STAR_CARD_PRESENT; 225 } 226 227 allwinner_sdhost_update_irq(s); 228 } 229 230 static void allwinner_sdhost_send_command(AwSdHostState *s) 231 { 232 SDRequest request; 233 uint8_t resp[16]; 234 int rlen; 235 236 /* Auto clear load flag */ 237 s->command &= ~SD_CMDR_LOAD; 238 239 /* Clock change does not actually interact with the SD bus */ 240 if (!(s->command & SD_CMDR_CLKCHANGE)) { 241 242 /* Prepare request */ 243 request.cmd = s->command & SD_CMDR_CMDID_MASK; 244 request.arg = s->command_arg; 245 246 /* Send request to SD bus */ 247 rlen = sdbus_do_command(&s->sdbus, &request, resp); 248 if (rlen < 0) { 249 goto error; 250 } 251 252 /* If the command has a response, store it in the response registers */ 253 if ((s->command & SD_CMDR_RESPONSE)) { 254 if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) { 255 s->response[0] = ldl_be_p(&resp[0]); 256 s->response[1] = s->response[2] = s->response[3] = 0; 257 258 } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) { 259 s->response[0] = ldl_be_p(&resp[12]); 260 s->response[1] = ldl_be_p(&resp[8]); 261 s->response[2] = ldl_be_p(&resp[4]); 262 s->response[3] = ldl_be_p(&resp[0]); 263 } else { 264 goto error; 265 } 266 } 267 } 268 269 /* Set interrupt status bits */ 270 s->irq_status |= SD_RISR_CMD_COMPLETE; 271 return; 272 273 error: 274 s->irq_status |= SD_RISR_NO_RESPONSE; 275 } 276 277 static void allwinner_sdhost_auto_stop(AwSdHostState *s) 278 { 279 /* 280 * The stop command (CMD12) ensures the SD bus 281 * returns to the transfer state. 282 */ 283 if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) { 284 /* First save current command registers */ 285 uint32_t saved_cmd = s->command; 286 uint32_t saved_arg = s->command_arg; 287 288 /* Prepare stop command (CMD12) */ 289 s->command &= ~SD_CMDR_CMDID_MASK; 290 s->command |= 12; /* CMD12 */ 291 s->command_arg = 0; 292 293 /* Put the command on SD bus */ 294 allwinner_sdhost_send_command(s); 295 296 /* Restore command values */ 297 s->command = saved_cmd; 298 s->command_arg = saved_arg; 299 300 /* Set IRQ status bit for automatic stop done */ 301 s->irq_status |= SD_RISR_AUTOCMD_DONE; 302 } 303 } 304 305 static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s, 306 hwaddr desc_addr, 307 TransferDescriptor *desc, 308 bool is_write, uint32_t max_bytes) 309 { 310 AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s); 311 uint32_t num_done = 0; 312 uint32_t num_bytes = max_bytes; 313 uint8_t buf[1024]; 314 315 /* Read descriptor */ 316 dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc), 317 MEMTXATTRS_UNSPECIFIED); 318 if (desc->size == 0) { 319 desc->size = klass->max_desc_size; 320 } else if (desc->size > klass->max_desc_size) { 321 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size " 322 " is out-of-bounds: %" PRIu32 " > %zu", 323 __func__, desc->size, klass->max_desc_size); 324 desc->size = klass->max_desc_size; 325 } 326 if (desc->size < num_bytes) { 327 num_bytes = desc->size; 328 } 329 330 trace_allwinner_sdhost_process_desc(desc_addr, desc->size, 331 is_write, max_bytes); 332 333 while (num_done < num_bytes) { 334 /* Try to completely fill the local buffer */ 335 uint32_t buf_bytes = num_bytes - num_done; 336 if (buf_bytes > sizeof(buf)) { 337 buf_bytes = sizeof(buf); 338 } 339 340 /* Write to SD bus */ 341 if (is_write) { 342 dma_memory_read(&s->dma_as, 343 (desc->addr & DESC_SIZE_MASK) + num_done, buf, 344 buf_bytes, MEMTXATTRS_UNSPECIFIED); 345 sdbus_write_data(&s->sdbus, buf, buf_bytes); 346 347 /* Read from SD bus */ 348 } else { 349 sdbus_read_data(&s->sdbus, buf, buf_bytes); 350 dma_memory_write(&s->dma_as, 351 (desc->addr & DESC_SIZE_MASK) + num_done, buf, 352 buf_bytes, MEMTXATTRS_UNSPECIFIED); 353 } 354 num_done += buf_bytes; 355 } 356 357 /* Clear hold flag and flush descriptor */ 358 desc->status &= ~DESC_STATUS_HOLD; 359 dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc), 360 MEMTXATTRS_UNSPECIFIED); 361 362 return num_done; 363 } 364 365 static void allwinner_sdhost_dma(AwSdHostState *s) 366 { 367 TransferDescriptor desc; 368 hwaddr desc_addr = s->desc_base; 369 bool is_write = (s->command & SD_CMDR_WRITE); 370 uint32_t bytes_done = 0; 371 372 /* Check if DMA can be performed */ 373 if (s->byte_count == 0 || s->block_size == 0 || 374 !(s->global_ctl & SD_GCTL_DMA_ENB)) { 375 return; 376 } 377 378 /* 379 * For read operations, data must be available on the SD bus 380 * If not, it is an error and we should not act at all 381 */ 382 if (!is_write && !sdbus_data_ready(&s->sdbus)) { 383 return; 384 } 385 386 /* Process the DMA descriptors until all data is copied */ 387 while (s->byte_count > 0) { 388 bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc, 389 is_write, s->byte_count); 390 allwinner_sdhost_update_transfer_cnt(s, bytes_done); 391 392 if (bytes_done <= s->byte_count) { 393 s->byte_count -= bytes_done; 394 } else { 395 s->byte_count = 0; 396 } 397 398 if (desc.status & DESC_STATUS_LAST) { 399 break; 400 } else { 401 desc_addr = desc.next; 402 } 403 } 404 405 /* Raise IRQ to signal DMA is completed */ 406 s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR; 407 408 /* Update DMAC bits */ 409 s->dmac_status |= SD_IDST_INT_SUMMARY; 410 411 if (is_write) { 412 s->dmac_status |= SD_IDST_TRANSMIT_IRQ; 413 } else { 414 s->dmac_status |= SD_IDST_RECEIVE_IRQ; 415 } 416 } 417 418 static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s) 419 { 420 uint32_t res = 0; 421 422 if (sdbus_data_ready(&s->sdbus)) { 423 sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t)); 424 le32_to_cpus(&res); 425 allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); 426 allwinner_sdhost_auto_stop(s); 427 allwinner_sdhost_update_irq(s); 428 } else { 429 qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", 430 __func__); 431 } 432 433 return res; 434 } 435 436 static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, 437 unsigned size) 438 { 439 AwSdHostState *s = AW_SDHOST(opaque); 440 AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s); 441 uint32_t res = 0; 442 443 switch (offset) { 444 case REG_SD_GCTL: /* Global Control */ 445 res = s->global_ctl; 446 break; 447 case REG_SD_CKCR: /* Clock Control */ 448 res = s->clock_ctl; 449 break; 450 case REG_SD_TMOR: /* Timeout */ 451 res = s->timeout; 452 break; 453 case REG_SD_BWDR: /* Bus Width */ 454 res = s->bus_width; 455 break; 456 case REG_SD_BKSR: /* Block Size */ 457 res = s->block_size; 458 break; 459 case REG_SD_BYCR: /* Byte Count */ 460 res = s->byte_count; 461 break; 462 case REG_SD_CMDR: /* Command */ 463 res = s->command; 464 break; 465 case REG_SD_CAGR: /* Command Argument */ 466 res = s->command_arg; 467 break; 468 case REG_SD_RESP0: /* Response Zero */ 469 res = s->response[0]; 470 break; 471 case REG_SD_RESP1: /* Response One */ 472 res = s->response[1]; 473 break; 474 case REG_SD_RESP2: /* Response Two */ 475 res = s->response[2]; 476 break; 477 case REG_SD_RESP3: /* Response Three */ 478 res = s->response[3]; 479 break; 480 case REG_SD_IMKR: /* Interrupt Mask */ 481 res = s->irq_mask; 482 break; 483 case REG_SD_MISR: /* Masked Interrupt Status */ 484 res = s->irq_status & s->irq_mask; 485 break; 486 case REG_SD_RISR: /* Raw Interrupt Status */ 487 res = s->irq_status; 488 break; 489 case REG_SD_STAR: /* Status */ 490 res = s->status; 491 if (sdbus_data_ready(&s->sdbus)) { 492 res |= SD_STAR_FIFO_LEVEL_1; 493 } else { 494 res |= SD_STAR_FIFO_EMPTY; 495 } 496 break; 497 case REG_SD_FWLR: /* FIFO Water Level */ 498 res = s->fifo_wlevel; 499 break; 500 case REG_SD_FUNS: /* FIFO Function Select */ 501 res = s->fifo_func_sel; 502 break; 503 case REG_SD_DBGC: /* Debug Enable */ 504 res = s->debug_enable; 505 break; 506 case REG_SD_A12A: /* Auto command 12 argument */ 507 res = s->auto12_arg; 508 break; 509 case REG_SD_NTSR: /* SD NewTiming Set */ 510 res = s->newtiming_set; 511 break; 512 case REG_SD_SDBG: /* SD newTiming Set Debug */ 513 res = s->newtiming_debug; 514 break; 515 case REG_SD_HWRST: /* Hardware Reset Register */ 516 res = s->hardware_rst; 517 break; 518 case REG_SD_DMAC: /* Internal DMA Controller Control */ 519 res = s->dmac; 520 break; 521 case REG_SD_DLBA: /* Descriptor List Base Address */ 522 res = s->desc_base; 523 break; 524 case REG_SD_IDST: /* Internal DMA Controller Status */ 525 res = s->dmac_status; 526 break; 527 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ 528 res = s->dmac_irq; 529 break; 530 case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */ 531 if (sc->is_sun4i) { 532 res = allwinner_sdhost_fifo_read(s); 533 } else { 534 res = s->card_threshold; 535 } 536 break; 537 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ 538 res = s->startbit_detect; 539 break; 540 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ 541 res = s->response_crc; 542 break; 543 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ 544 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ 545 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ 546 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ 547 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ 548 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ 549 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ 550 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ 551 res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))]; 552 break; 553 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ 554 res = s->status_crc; 555 break; 556 case REG_SD_FIFO: /* Read/Write FIFO */ 557 res = allwinner_sdhost_fifo_read(s); 558 break; 559 default: 560 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" 561 HWADDR_PRIx"\n", __func__, offset); 562 res = 0; 563 break; 564 } 565 566 trace_allwinner_sdhost_read(offset, res, size); 567 return res; 568 } 569 570 static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value) 571 { 572 uint32_t u32 = cpu_to_le32(value); 573 sdbus_write_data(&s->sdbus, &u32, sizeof(u32)); 574 allwinner_sdhost_update_transfer_cnt(s, sizeof(u32)); 575 allwinner_sdhost_auto_stop(s); 576 allwinner_sdhost_update_irq(s); 577 } 578 579 static void allwinner_sdhost_write(void *opaque, hwaddr offset, 580 uint64_t value, unsigned size) 581 { 582 AwSdHostState *s = AW_SDHOST(opaque); 583 AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s); 584 585 trace_allwinner_sdhost_write(offset, value, size); 586 587 switch (offset) { 588 case REG_SD_GCTL: /* Global Control */ 589 s->global_ctl = value; 590 s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST | 591 SD_GCTL_SOFT_RST); 592 allwinner_sdhost_update_irq(s); 593 break; 594 case REG_SD_CKCR: /* Clock Control */ 595 s->clock_ctl = value; 596 break; 597 case REG_SD_TMOR: /* Timeout */ 598 s->timeout = value; 599 break; 600 case REG_SD_BWDR: /* Bus Width */ 601 s->bus_width = value; 602 break; 603 case REG_SD_BKSR: /* Block Size */ 604 s->block_size = value; 605 break; 606 case REG_SD_BYCR: /* Byte Count */ 607 s->byte_count = value; 608 s->transfer_cnt = value; 609 break; 610 case REG_SD_CMDR: /* Command */ 611 s->command = value; 612 if (value & SD_CMDR_LOAD) { 613 allwinner_sdhost_send_command(s); 614 allwinner_sdhost_dma(s); 615 allwinner_sdhost_auto_stop(s); 616 } 617 allwinner_sdhost_update_irq(s); 618 break; 619 case REG_SD_CAGR: /* Command Argument */ 620 s->command_arg = value; 621 break; 622 case REG_SD_RESP0: /* Response Zero */ 623 s->response[0] = value; 624 break; 625 case REG_SD_RESP1: /* Response One */ 626 s->response[1] = value; 627 break; 628 case REG_SD_RESP2: /* Response Two */ 629 s->response[2] = value; 630 break; 631 case REG_SD_RESP3: /* Response Three */ 632 s->response[3] = value; 633 break; 634 case REG_SD_IMKR: /* Interrupt Mask */ 635 s->irq_mask = value; 636 allwinner_sdhost_update_irq(s); 637 break; 638 case REG_SD_MISR: /* Masked Interrupt Status */ 639 case REG_SD_RISR: /* Raw Interrupt Status */ 640 s->irq_status &= ~value; 641 allwinner_sdhost_update_irq(s); 642 break; 643 case REG_SD_STAR: /* Status */ 644 s->status &= ~value; 645 allwinner_sdhost_update_irq(s); 646 break; 647 case REG_SD_FWLR: /* FIFO Water Level */ 648 s->fifo_wlevel = value; 649 break; 650 case REG_SD_FUNS: /* FIFO Function Select */ 651 s->fifo_func_sel = value; 652 break; 653 case REG_SD_DBGC: /* Debug Enable */ 654 s->debug_enable = value; 655 break; 656 case REG_SD_A12A: /* Auto command 12 argument */ 657 s->auto12_arg = value; 658 break; 659 case REG_SD_NTSR: /* SD NewTiming Set */ 660 s->newtiming_set = value; 661 break; 662 case REG_SD_SDBG: /* SD newTiming Set Debug */ 663 s->newtiming_debug = value; 664 break; 665 case REG_SD_HWRST: /* Hardware Reset Register */ 666 s->hardware_rst = value; 667 break; 668 case REG_SD_DMAC: /* Internal DMA Controller Control */ 669 s->dmac = value; 670 allwinner_sdhost_update_irq(s); 671 break; 672 case REG_SD_DLBA: /* Descriptor List Base Address */ 673 s->desc_base = value; 674 break; 675 case REG_SD_IDST: /* Internal DMA Controller Status */ 676 s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK); 677 allwinner_sdhost_update_irq(s); 678 break; 679 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ 680 s->dmac_irq = value; 681 allwinner_sdhost_update_irq(s); 682 break; 683 case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */ 684 if (sc->is_sun4i) { 685 allwinner_sdhost_fifo_write(s, value); 686 } else { 687 s->card_threshold = value; 688 } 689 break; 690 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ 691 s->startbit_detect = value; 692 break; 693 case REG_SD_FIFO: /* Read/Write FIFO */ 694 allwinner_sdhost_fifo_write(s, value); 695 break; 696 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ 697 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ 698 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */ 699 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */ 700 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */ 701 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */ 702 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */ 703 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */ 704 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ 705 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */ 706 break; 707 default: 708 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" 709 HWADDR_PRIx"\n", __func__, offset); 710 break; 711 } 712 } 713 714 static const MemoryRegionOps allwinner_sdhost_ops = { 715 .read = allwinner_sdhost_read, 716 .write = allwinner_sdhost_write, 717 .endianness = DEVICE_NATIVE_ENDIAN, 718 .valid = { 719 .min_access_size = 4, 720 .max_access_size = 4, 721 }, 722 .impl.min_access_size = 4, 723 }; 724 725 static const VMStateDescription vmstate_allwinner_sdhost = { 726 .name = "allwinner-sdhost", 727 .version_id = 1, 728 .minimum_version_id = 1, 729 .fields = (VMStateField[]) { 730 VMSTATE_UINT32(global_ctl, AwSdHostState), 731 VMSTATE_UINT32(clock_ctl, AwSdHostState), 732 VMSTATE_UINT32(timeout, AwSdHostState), 733 VMSTATE_UINT32(bus_width, AwSdHostState), 734 VMSTATE_UINT32(block_size, AwSdHostState), 735 VMSTATE_UINT32(byte_count, AwSdHostState), 736 VMSTATE_UINT32(transfer_cnt, AwSdHostState), 737 VMSTATE_UINT32(command, AwSdHostState), 738 VMSTATE_UINT32(command_arg, AwSdHostState), 739 VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4), 740 VMSTATE_UINT32(irq_mask, AwSdHostState), 741 VMSTATE_UINT32(irq_status, AwSdHostState), 742 VMSTATE_UINT32(status, AwSdHostState), 743 VMSTATE_UINT32(fifo_wlevel, AwSdHostState), 744 VMSTATE_UINT32(fifo_func_sel, AwSdHostState), 745 VMSTATE_UINT32(debug_enable, AwSdHostState), 746 VMSTATE_UINT32(auto12_arg, AwSdHostState), 747 VMSTATE_UINT32(newtiming_set, AwSdHostState), 748 VMSTATE_UINT32(newtiming_debug, AwSdHostState), 749 VMSTATE_UINT32(hardware_rst, AwSdHostState), 750 VMSTATE_UINT32(dmac, AwSdHostState), 751 VMSTATE_UINT32(desc_base, AwSdHostState), 752 VMSTATE_UINT32(dmac_status, AwSdHostState), 753 VMSTATE_UINT32(dmac_irq, AwSdHostState), 754 VMSTATE_UINT32(card_threshold, AwSdHostState), 755 VMSTATE_UINT32(startbit_detect, AwSdHostState), 756 VMSTATE_UINT32(response_crc, AwSdHostState), 757 VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8), 758 VMSTATE_UINT32(status_crc, AwSdHostState), 759 VMSTATE_END_OF_LIST() 760 } 761 }; 762 763 static Property allwinner_sdhost_properties[] = { 764 DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr, 765 TYPE_MEMORY_REGION, MemoryRegion *), 766 DEFINE_PROP_END_OF_LIST(), 767 }; 768 769 static void allwinner_sdhost_init(Object *obj) 770 { 771 AwSdHostState *s = AW_SDHOST(obj); 772 773 qbus_init(&s->sdbus, sizeof(s->sdbus), 774 TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); 775 776 memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s, 777 TYPE_AW_SDHOST, 4 * KiB); 778 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 779 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); 780 } 781 782 static void allwinner_sdhost_realize(DeviceState *dev, Error **errp) 783 { 784 AwSdHostState *s = AW_SDHOST(dev); 785 786 if (!s->dma_mr) { 787 error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set"); 788 return; 789 } 790 791 address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma"); 792 } 793 794 static void allwinner_sdhost_reset(DeviceState *dev) 795 { 796 AwSdHostState *s = AW_SDHOST(dev); 797 798 s->global_ctl = REG_SD_GCTL_RST; 799 s->clock_ctl = REG_SD_CKCR_RST; 800 s->timeout = REG_SD_TMOR_RST; 801 s->bus_width = REG_SD_BWDR_RST; 802 s->block_size = REG_SD_BKSR_RST; 803 s->byte_count = REG_SD_BYCR_RST; 804 s->transfer_cnt = 0; 805 806 s->command = REG_SD_CMDR_RST; 807 s->command_arg = REG_SD_CAGR_RST; 808 809 for (int i = 0; i < ARRAY_SIZE(s->response); i++) { 810 s->response[i] = REG_SD_RESP_RST; 811 } 812 813 s->irq_mask = REG_SD_IMKR_RST; 814 s->irq_status = REG_SD_RISR_RST; 815 s->status = REG_SD_STAR_RST; 816 817 s->fifo_wlevel = REG_SD_FWLR_RST; 818 s->fifo_func_sel = REG_SD_FUNS_RST; 819 s->debug_enable = REG_SD_DBGC_RST; 820 s->auto12_arg = REG_SD_A12A_RST; 821 s->newtiming_set = REG_SD_NTSR_RST; 822 s->newtiming_debug = REG_SD_SDBG_RST; 823 s->hardware_rst = REG_SD_HWRST_RST; 824 s->dmac = REG_SD_DMAC_RST; 825 s->desc_base = REG_SD_DLBA_RST; 826 s->dmac_status = REG_SD_IDST_RST; 827 s->dmac_irq = REG_SD_IDIE_RST; 828 s->card_threshold = REG_SD_THLDC_RST; 829 s->startbit_detect = REG_SD_DSBD_RST; 830 s->response_crc = REG_SD_RES_CRC_RST; 831 832 for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) { 833 s->data_crc[i] = REG_SD_DATA_CRC_RST; 834 } 835 836 s->status_crc = REG_SD_CRC_STA_RST; 837 } 838 839 static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data) 840 { 841 SDBusClass *sbc = SD_BUS_CLASS(klass); 842 843 sbc->set_inserted = allwinner_sdhost_set_inserted; 844 } 845 846 static void allwinner_sdhost_class_init(ObjectClass *klass, void *data) 847 { 848 DeviceClass *dc = DEVICE_CLASS(klass); 849 850 dc->reset = allwinner_sdhost_reset; 851 dc->vmsd = &vmstate_allwinner_sdhost; 852 dc->realize = allwinner_sdhost_realize; 853 device_class_set_props(dc, allwinner_sdhost_properties); 854 } 855 856 static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data) 857 { 858 AwSdHostClass *sc = AW_SDHOST_CLASS(klass); 859 sc->max_desc_size = 8 * KiB; 860 sc->is_sun4i = true; 861 } 862 863 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) 864 { 865 AwSdHostClass *sc = AW_SDHOST_CLASS(klass); 866 sc->max_desc_size = 64 * KiB; 867 sc->is_sun4i = false; 868 } 869 870 static const TypeInfo allwinner_sdhost_info = { 871 .name = TYPE_AW_SDHOST, 872 .parent = TYPE_SYS_BUS_DEVICE, 873 .instance_init = allwinner_sdhost_init, 874 .instance_size = sizeof(AwSdHostState), 875 .class_init = allwinner_sdhost_class_init, 876 .class_size = sizeof(AwSdHostClass), 877 .abstract = true, 878 }; 879 880 static const TypeInfo allwinner_sdhost_sun4i_info = { 881 .name = TYPE_AW_SDHOST_SUN4I, 882 .parent = TYPE_AW_SDHOST, 883 .class_init = allwinner_sdhost_sun4i_class_init, 884 }; 885 886 static const TypeInfo allwinner_sdhost_sun5i_info = { 887 .name = TYPE_AW_SDHOST_SUN5I, 888 .parent = TYPE_AW_SDHOST, 889 .class_init = allwinner_sdhost_sun5i_class_init, 890 }; 891 892 static const TypeInfo allwinner_sdhost_bus_info = { 893 .name = TYPE_AW_SDHOST_BUS, 894 .parent = TYPE_SD_BUS, 895 .instance_size = sizeof(SDBus), 896 .class_init = allwinner_sdhost_bus_class_init, 897 }; 898 899 static void allwinner_sdhost_register_types(void) 900 { 901 type_register_static(&allwinner_sdhost_info); 902 type_register_static(&allwinner_sdhost_sun4i_info); 903 type_register_static(&allwinner_sdhost_sun5i_info); 904 type_register_static(&allwinner_sdhost_bus_info); 905 } 906 907 type_init(allwinner_sdhost_register_types)