rx-gdbsim.c (7121B)
1 /* 2 * RX QEMU GDB simulator 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/cutils.h" 21 #include "qemu/error-report.h" 22 #include "qemu/guest-random.h" 23 #include "qapi/error.h" 24 #include "hw/loader.h" 25 #include "hw/rx/rx62n.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/device_tree.h" 28 #include "sysemu/reset.h" 29 #include "hw/boards.h" 30 #include "qom/object.h" 31 32 /* Same address of GDB integrated simulator */ 33 #define SDRAM_BASE EXT_CS_BASE 34 35 struct RxGdbSimMachineClass { 36 /*< private >*/ 37 MachineClass parent_class; 38 /*< public >*/ 39 const char *mcu_name; 40 uint32_t xtal_freq_hz; 41 }; 42 typedef struct RxGdbSimMachineClass RxGdbSimMachineClass; 43 44 struct RxGdbSimMachineState { 45 /*< private >*/ 46 MachineState parent_obj; 47 /*< public >*/ 48 RX62NState mcu; 49 }; 50 typedef struct RxGdbSimMachineState RxGdbSimMachineState; 51 52 #define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common") 53 54 DECLARE_OBJ_CHECKERS(RxGdbSimMachineState, RxGdbSimMachineClass, 55 RX_GDBSIM_MACHINE, TYPE_RX_GDBSIM_MACHINE) 56 57 58 static void rx_load_image(RXCPU *cpu, const char *filename, 59 uint32_t start, uint32_t size) 60 { 61 static uint32_t extable[32]; 62 long kernel_size; 63 int i; 64 65 kernel_size = load_image_targphys(filename, start, size); 66 if (kernel_size < 0) { 67 fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); 68 exit(1); 69 } 70 cpu->env.pc = start; 71 72 /* setup exception trap trampoline */ 73 /* linux kernel only works little-endian mode */ 74 for (i = 0; i < ARRAY_SIZE(extable); i++) { 75 extable[i] = cpu_to_le32(0x10 + i * 4); 76 } 77 rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_BASE); 78 } 79 80 static void rx_gdbsim_init(MachineState *machine) 81 { 82 MachineClass *mc = MACHINE_GET_CLASS(machine); 83 RxGdbSimMachineState *s = RX_GDBSIM_MACHINE(machine); 84 RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine); 85 MemoryRegion *sysmem = get_system_memory(); 86 const char *kernel_filename = machine->kernel_filename; 87 const char *dtb_filename = machine->dtb; 88 uint8_t rng_seed[32]; 89 90 if (machine->ram_size < mc->default_ram_size) { 91 char *sz = size_to_str(mc->default_ram_size); 92 error_report("Invalid RAM size, should be more than %s", sz); 93 g_free(sz); 94 exit(1); 95 } 96 97 /* Allocate memory space */ 98 memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram); 99 100 /* Initialize MCU */ 101 object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name); 102 object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem), 103 &error_abort); 104 object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", 105 rxc->xtal_freq_hz, &error_abort); 106 object_property_set_bool(OBJECT(&s->mcu), "load-kernel", 107 kernel_filename != NULL, &error_abort); 108 109 if (!kernel_filename) { 110 if (machine->firmware) { 111 rom_add_file_fixed(machine->firmware, RX62N_CFLASH_BASE, 0); 112 } else if (!qtest_enabled()) { 113 error_report("No bios or kernel specified"); 114 exit(1); 115 } 116 } 117 118 qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); 119 120 /* Load kernel and dtb */ 121 if (kernel_filename) { 122 ram_addr_t kernel_offset; 123 124 /* 125 * The kernel image is loaded into 126 * the latter half of the SDRAM space. 127 */ 128 kernel_offset = machine->ram_size / 2; 129 rx_load_image(RX_CPU(first_cpu), kernel_filename, 130 SDRAM_BASE + kernel_offset, kernel_offset); 131 if (dtb_filename) { 132 ram_addr_t dtb_offset; 133 int dtb_size; 134 g_autofree void *dtb = load_device_tree(dtb_filename, &dtb_size); 135 136 if (dtb == NULL) { 137 error_report("Couldn't open dtb file %s", dtb_filename); 138 exit(1); 139 } 140 if (machine->kernel_cmdline && 141 qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", 142 machine->kernel_cmdline) < 0) { 143 error_report("Couldn't set /chosen/bootargs"); 144 exit(1); 145 } 146 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 147 qemu_fdt_setprop(dtb, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 148 /* DTB is located at the end of SDRAM space. */ 149 dtb_offset = ROUND_DOWN(machine->ram_size - dtb_size, 16); 150 rom_add_blob_fixed("dtb", dtb, dtb_size, 151 SDRAM_BASE + dtb_offset); 152 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 153 rom_ptr(SDRAM_BASE + dtb_offset, dtb_size)); 154 /* Set dtb address to R1 */ 155 RX_CPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset; 156 } 157 } 158 } 159 160 static void rx_gdbsim_class_init(ObjectClass *oc, void *data) 161 { 162 MachineClass *mc = MACHINE_CLASS(oc); 163 164 mc->init = rx_gdbsim_init; 165 mc->default_cpu_type = TYPE_RX62N_CPU; 166 mc->default_ram_size = 16 * MiB; 167 mc->default_ram_id = "ext-sdram"; 168 } 169 170 static void rx62n7_class_init(ObjectClass *oc, void *data) 171 { 172 RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); 173 MachineClass *mc = MACHINE_CLASS(oc); 174 175 rxc->mcu_name = TYPE_R5F562N7_MCU; 176 rxc->xtal_freq_hz = 12 * 1000 * 1000; 177 mc->desc = "gdb simulator (R5F562N7 MCU and external RAM)"; 178 }; 179 180 static void rx62n8_class_init(ObjectClass *oc, void *data) 181 { 182 RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); 183 MachineClass *mc = MACHINE_CLASS(oc); 184 185 rxc->mcu_name = TYPE_R5F562N8_MCU; 186 rxc->xtal_freq_hz = 12 * 1000 * 1000; 187 mc->desc = "gdb simulator (R5F562N8 MCU and external RAM)"; 188 }; 189 190 static const TypeInfo rx_gdbsim_types[] = { 191 { 192 .name = MACHINE_TYPE_NAME("gdbsim-r5f562n7"), 193 .parent = TYPE_RX_GDBSIM_MACHINE, 194 .class_init = rx62n7_class_init, 195 }, { 196 .name = MACHINE_TYPE_NAME("gdbsim-r5f562n8"), 197 .parent = TYPE_RX_GDBSIM_MACHINE, 198 .class_init = rx62n8_class_init, 199 }, { 200 .name = TYPE_RX_GDBSIM_MACHINE, 201 .parent = TYPE_MACHINE, 202 .instance_size = sizeof(RxGdbSimMachineState), 203 .class_size = sizeof(RxGdbSimMachineClass), 204 .class_init = rx_gdbsim_class_init, 205 .abstract = true, 206 } 207 }; 208 209 DEFINE_TYPES(rx_gdbsim_types)