opentitan.c (14632B)
1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * Provides a board compatible with the OpenTitan FPGA platform: 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "hw/riscv/opentitan.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/misc/unimp.h" 27 #include "hw/riscv/boot.h" 28 #include "qemu/units.h" 29 #include "sysemu/sysemu.h" 30 31 static const MemMapEntry ibex_memmap[] = { 32 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, 33 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, 34 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, 35 [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, 36 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, 37 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 }, 38 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, 39 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, 40 [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, 41 [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, 42 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, 43 [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 }, 44 [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 }, 45 [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 }, 46 [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 }, 47 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, 48 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, 49 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, 50 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, 51 [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 }, 52 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, 53 [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, 54 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, 55 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, 56 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, 57 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 }, 58 [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, 59 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, 60 [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, 61 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, 62 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, 63 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, 64 [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, 65 [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 }, 66 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, 67 }; 68 69 static void opentitan_board_init(MachineState *machine) 70 { 71 MachineClass *mc = MACHINE_GET_CLASS(machine); 72 const MemMapEntry *memmap = ibex_memmap; 73 OpenTitanState *s = g_new0(OpenTitanState, 1); 74 MemoryRegion *sys_mem = get_system_memory(); 75 76 if (machine->ram_size != mc->default_ram_size) { 77 char *sz = size_to_str(mc->default_ram_size); 78 error_report("Invalid RAM size, should be %s", sz); 79 g_free(sz); 80 exit(EXIT_FAILURE); 81 } 82 83 /* Initialize SoC */ 84 object_initialize_child(OBJECT(machine), "soc", &s->soc, 85 TYPE_RISCV_IBEX_SOC); 86 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 87 88 memory_region_add_subregion(sys_mem, 89 memmap[IBEX_DEV_RAM].base, machine->ram); 90 91 if (machine->firmware) { 92 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); 93 } 94 95 if (machine->kernel_filename) { 96 riscv_load_kernel(machine->kernel_filename, 97 memmap[IBEX_DEV_RAM].base, NULL); 98 } 99 } 100 101 static void opentitan_machine_init(MachineClass *mc) 102 { 103 mc->desc = "RISC-V Board compatible with OpenTitan"; 104 mc->init = opentitan_board_init; 105 mc->max_cpus = 1; 106 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 107 mc->default_ram_id = "riscv.lowrisc.ibex.ram"; 108 mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; 109 } 110 111 DEFINE_MACHINE("opentitan", opentitan_machine_init) 112 113 static void lowrisc_ibex_soc_init(Object *obj) 114 { 115 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 116 117 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 118 119 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); 120 121 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 122 123 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); 124 125 for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { 126 object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], 127 TYPE_IBEX_SPI_HOST); 128 } 129 } 130 131 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 132 { 133 const MemMapEntry *memmap = ibex_memmap; 134 DeviceState *dev; 135 SysBusDevice *busdev; 136 MachineState *ms = MACHINE(qdev_get_machine()); 137 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 138 MemoryRegion *sys_mem = get_system_memory(); 139 int i; 140 141 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 142 &error_abort); 143 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 144 &error_abort); 145 object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec, 146 &error_abort); 147 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); 148 149 /* Boot ROM */ 150 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 151 memmap[IBEX_DEV_ROM].size, &error_fatal); 152 memory_region_add_subregion(sys_mem, 153 memmap[IBEX_DEV_ROM].base, &s->rom); 154 155 /* Flash memory */ 156 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 157 memmap[IBEX_DEV_FLASH].size, &error_fatal); 158 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 159 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, 160 memmap[IBEX_DEV_FLASH_VIRTUAL].size); 161 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 162 &s->flash_mem); 163 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, 164 &s->flash_alias); 165 166 /* PLIC */ 167 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); 168 qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0); 169 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); 170 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); 171 qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00); 172 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); 173 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); 174 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); 175 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); 176 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); 177 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); 178 179 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 180 return; 181 } 182 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 183 184 for (i = 0; i < ms->smp.cpus; i++) { 185 CPUState *cpu = qemu_get_cpu(i); 186 187 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, 188 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 189 } 190 191 /* UART */ 192 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 193 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 194 return; 195 } 196 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 197 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 198 0, qdev_get_gpio_in(DEVICE(&s->plic), 199 IBEX_UART0_TX_WATERMARK_IRQ)); 200 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 201 1, qdev_get_gpio_in(DEVICE(&s->plic), 202 IBEX_UART0_RX_WATERMARK_IRQ)); 203 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 204 2, qdev_get_gpio_in(DEVICE(&s->plic), 205 IBEX_UART0_TX_EMPTY_IRQ)); 206 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 207 3, qdev_get_gpio_in(DEVICE(&s->plic), 208 IBEX_UART0_RX_OVERFLOW_IRQ)); 209 210 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 211 return; 212 } 213 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); 214 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 215 0, qdev_get_gpio_in(DEVICE(&s->plic), 216 IBEX_TIMER_TIMEREXPIRED0_0)); 217 qdev_connect_gpio_out(DEVICE(&s->timer), 0, 218 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), 219 IRQ_M_TIMER)); 220 221 /* SPI-Hosts */ 222 for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) { 223 dev = DEVICE(&(s->spi_host[i])); 224 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) { 225 return; 226 } 227 busdev = SYS_BUS_DEVICE(dev); 228 sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base); 229 230 switch (i) { 231 case OPENTITAN_SPI_HOST0: 232 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), 233 IBEX_SPI_HOST0_ERR_IRQ)); 234 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), 235 IBEX_SPI_HOST0_SPI_EVENT_IRQ)); 236 break; 237 case OPENTITAN_SPI_HOST1: 238 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), 239 IBEX_SPI_HOST1_ERR_IRQ)); 240 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), 241 IBEX_SPI_HOST1_SPI_EVENT_IRQ)); 242 break; 243 } 244 } 245 246 create_unimplemented_device("riscv.lowrisc.ibex.gpio", 247 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 248 create_unimplemented_device("riscv.lowrisc.ibex.spi_device", 249 memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size); 250 create_unimplemented_device("riscv.lowrisc.ibex.i2c", 251 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); 252 create_unimplemented_device("riscv.lowrisc.ibex.pattgen", 253 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); 254 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", 255 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); 256 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", 257 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); 258 create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", 259 memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); 260 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 261 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 262 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 263 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 264 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 265 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 266 create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 267 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 268 create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 269 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); 270 create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 271 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 272 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 273 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 274 create_unimplemented_device("riscv.lowrisc.ibex.aes", 275 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 276 create_unimplemented_device("riscv.lowrisc.ibex.hmac", 277 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 278 create_unimplemented_device("riscv.lowrisc.ibex.kmac", 279 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); 280 create_unimplemented_device("riscv.lowrisc.ibex.keymgr", 281 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); 282 create_unimplemented_device("riscv.lowrisc.ibex.csrng", 283 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); 284 create_unimplemented_device("riscv.lowrisc.ibex.entropy", 285 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); 286 create_unimplemented_device("riscv.lowrisc.ibex.edn0", 287 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); 288 create_unimplemented_device("riscv.lowrisc.ibex.edn1", 289 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); 290 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 291 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 292 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 293 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); 294 create_unimplemented_device("riscv.lowrisc.ibex.otbn", 295 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); 296 create_unimplemented_device("riscv.lowrisc.ibex.peri", 297 memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); 298 } 299 300 static Property lowrisc_ibex_soc_props[] = { 301 DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400), 302 DEFINE_PROP_END_OF_LIST() 303 }; 304 305 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 306 { 307 DeviceClass *dc = DEVICE_CLASS(oc); 308 309 device_class_set_props(dc, lowrisc_ibex_soc_props); 310 dc->realize = lowrisc_ibex_soc_realize; 311 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 312 dc->user_creatable = false; 313 } 314 315 static const TypeInfo lowrisc_ibex_soc_type_info = { 316 .name = TYPE_RISCV_IBEX_SOC, 317 .parent = TYPE_DEVICE, 318 .instance_size = sizeof(LowRISCIbexSoCState), 319 .instance_init = lowrisc_ibex_soc_init, 320 .class_init = lowrisc_ibex_soc_class_init, 321 }; 322 323 static void lowrisc_ibex_soc_register_types(void) 324 { 325 type_register_static(&lowrisc_ibex_soc_type_info); 326 } 327 328 type_init(lowrisc_ibex_soc_register_types)