microchip_pfsoc.c (29231B)
1 /* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 10 * 11 * 0) CLINT (Core Level Interruptor) 12 * 1) PLIC (Platform Level Interrupt Controller) 13 * 2) eNVM (Embedded Non-Volatile Memory) 14 * 3) MMUARTs (Multi-Mode UART) 15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it 16 * 5) SiFive Platform DMA (Direct Memory Access Controller) 17 * 6) GEM (Gigabit Ethernet MAC Controller) 18 * 7) DMC (DDR Memory Controller) 19 * 8) IOSCB modules 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qemu/units.h" 40 #include "qemu/cutils.h" 41 #include "qapi/error.h" 42 #include "hw/boards.h" 43 #include "hw/loader.h" 44 #include "hw/sysbus.h" 45 #include "chardev/char.h" 46 #include "hw/cpu/cluster.h" 47 #include "target/riscv/cpu.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/riscv/boot.h" 50 #include "hw/riscv/riscv_hart.h" 51 #include "hw/riscv/microchip_pfsoc.h" 52 #include "hw/intc/riscv_aclint.h" 53 #include "hw/intc/sifive_plic.h" 54 #include "sysemu/device_tree.h" 55 #include "sysemu/sysemu.h" 56 57 /* 58 * The BIOS image used by this machine is called Hart Software Services (HSS). 59 * See https://github.com/polarfire-soc/hart-software-services 60 */ 61 #define BIOS_FILENAME "hss.bin" 62 #define RESET_VECTOR 0x20220000 63 64 /* CLINT timebase frequency */ 65 #define CLINT_TIMEBASE_FREQ 1000000 66 67 /* GEM version */ 68 #define GEM_REVISION 0x0107010c 69 70 /* 71 * The complete description of the whole PolarFire SoC memory map is scattered 72 * in different documents. There are several places to look at for memory maps: 73 * 74 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 75 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 76 * https://www.microsemi.com/document-portal/doc_download/ 77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 78 * describes the whole picture of the PolarFire SoC memory map. 79 * 80 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 81 * https://www.microsemi.com/document-portal/doc_download/ 82 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 83 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 84 * describes the complete integrated peripherals memory map 85 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 86 * describes the complete IOSCB modules memory maps 87 */ 88 static const MemMapEntry microchip_pfsoc_memmap[] = { 89 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 90 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 91 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 92 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 95 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 96 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 97 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 98 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 99 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 100 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 101 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 102 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 103 [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, 104 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 105 [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, 106 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 107 [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, 108 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 109 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 110 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 111 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 112 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 113 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 114 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 115 [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, 116 [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, 117 [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, 118 [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, 119 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 120 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 121 [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, 122 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 123 [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, 124 [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, 125 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 126 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 127 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 128 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 129 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 130 [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, 131 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 132 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 133 [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, 134 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 135 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 136 [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, 137 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 138 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 139 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 140 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 141 }; 142 143 static void microchip_pfsoc_soc_instance_init(Object *obj) 144 { 145 MachineState *ms = MACHINE(qdev_get_machine()); 146 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 147 148 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 149 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 150 151 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 152 TYPE_RISCV_HART_ARRAY); 153 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 154 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 155 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 156 TYPE_RISCV_CPU_SIFIVE_E51); 157 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 158 159 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 160 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 161 162 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 163 TYPE_RISCV_HART_ARRAY); 164 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 165 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 166 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 167 TYPE_RISCV_CPU_SIFIVE_U54); 168 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 169 170 object_initialize_child(obj, "dma-controller", &s->dma, 171 TYPE_SIFIVE_PDMA); 172 173 object_initialize_child(obj, "sysreg", &s->sysreg, 174 TYPE_MCHP_PFSOC_SYSREG); 175 176 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 177 TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 178 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 179 TYPE_MCHP_PFSOC_DDR_CFG); 180 181 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 182 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 183 184 object_initialize_child(obj, "sd-controller", &s->sdhci, 185 TYPE_CADENCE_SDHCI); 186 187 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 188 } 189 190 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 191 { 192 MachineState *ms = MACHINE(qdev_get_machine()); 193 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 194 const MemMapEntry *memmap = microchip_pfsoc_memmap; 195 MemoryRegion *system_memory = get_system_memory(); 196 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 197 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 198 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 199 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 200 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 201 char *plic_hart_config; 202 NICInfo *nd; 203 int i; 204 205 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 206 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 207 /* 208 * The cluster must be realized after the RISC-V hart array container, 209 * as the container's CPU object is only created on realize, and the 210 * CPU must exist and have been parented into the cluster before the 211 * cluster is realized. 212 */ 213 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 214 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 215 216 /* Reserved Memory at address 0 */ 217 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 218 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 219 memory_region_add_subregion(system_memory, 220 memmap[MICROCHIP_PFSOC_RSVD0].base, 221 rsvd0_mem); 222 223 /* E51 DTIM */ 224 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 225 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 226 memory_region_add_subregion(system_memory, 227 memmap[MICROCHIP_PFSOC_E51_DTIM].base, 228 e51_dtim_mem); 229 230 /* Bus Error Units */ 231 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 232 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 233 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 234 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 235 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 236 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 237 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 238 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 239 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 240 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 241 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 242 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 243 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 244 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 245 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 246 247 /* CLINT */ 248 riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, 249 0, ms->smp.cpus, false); 250 riscv_aclint_mtimer_create( 251 memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, 252 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 253 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 254 CLINT_TIMEBASE_FREQ, false); 255 256 /* L2 cache controller */ 257 create_unimplemented_device("microchip.pfsoc.l2cc", 258 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 259 260 /* 261 * Add L2-LIM at reset size. 262 * This should be reduced in size as the L2 Cache Controller WayEnable 263 * register is incremented. Unfortunately I don't see a nice (or any) way 264 * to handle reducing or blocking out the L2 LIM while still allowing it 265 * be re returned to all enabled after a reset. For the time being, just 266 * leave it enabled all the time. This won't break anything, but will be 267 * too generous to misbehaving guests. 268 */ 269 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 270 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 271 memory_region_add_subregion(system_memory, 272 memmap[MICROCHIP_PFSOC_L2LIM].base, 273 l2lim_mem); 274 275 /* create PLIC hart topology configuration string */ 276 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 277 278 /* PLIC */ 279 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 280 plic_hart_config, ms->smp.cpus, 0, 281 MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 282 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 283 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 284 MICROCHIP_PFSOC_PLIC_PENDING_BASE, 285 MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 286 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 287 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 288 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 289 memmap[MICROCHIP_PFSOC_PLIC].size); 290 g_free(plic_hart_config); 291 292 /* DMA */ 293 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 294 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 295 memmap[MICROCHIP_PFSOC_DMA].base); 296 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 298 qdev_get_gpio_in(DEVICE(s->plic), 299 MICROCHIP_PFSOC_DMA_IRQ0 + i)); 300 } 301 302 /* SYSREG */ 303 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 304 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 305 memmap[MICROCHIP_PFSOC_SYSREG].base); 306 307 /* AXISW */ 308 create_unimplemented_device("microchip.pfsoc.axisw", 309 memmap[MICROCHIP_PFSOC_AXISW].base, 310 memmap[MICROCHIP_PFSOC_AXISW].size); 311 312 /* MPUCFG */ 313 create_unimplemented_device("microchip.pfsoc.mpucfg", 314 memmap[MICROCHIP_PFSOC_MPUCFG].base, 315 memmap[MICROCHIP_PFSOC_MPUCFG].size); 316 317 /* FMETER */ 318 create_unimplemented_device("microchip.pfsoc.fmeter", 319 memmap[MICROCHIP_PFSOC_FMETER].base, 320 memmap[MICROCHIP_PFSOC_FMETER].size); 321 322 /* DDR SGMII PHY */ 323 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 325 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 326 327 /* DDR CFG */ 328 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 330 memmap[MICROCHIP_PFSOC_DDR_CFG].base); 331 332 /* SDHCI */ 333 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 335 memmap[MICROCHIP_PFSOC_EMMC_SD].base); 336 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 337 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 338 339 /* MMUARTs */ 340 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 341 memmap[MICROCHIP_PFSOC_MMUART0].base, 342 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 343 serial_hd(0)); 344 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 345 memmap[MICROCHIP_PFSOC_MMUART1].base, 346 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 347 serial_hd(1)); 348 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 349 memmap[MICROCHIP_PFSOC_MMUART2].base, 350 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 351 serial_hd(2)); 352 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 353 memmap[MICROCHIP_PFSOC_MMUART3].base, 354 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 355 serial_hd(3)); 356 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 357 memmap[MICROCHIP_PFSOC_MMUART4].base, 358 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 359 serial_hd(4)); 360 361 /* Watchdogs */ 362 create_unimplemented_device("microchip.pfsoc.watchdog0", 363 memmap[MICROCHIP_PFSOC_WDOG0].base, 364 memmap[MICROCHIP_PFSOC_WDOG0].size); 365 create_unimplemented_device("microchip.pfsoc.watchdog1", 366 memmap[MICROCHIP_PFSOC_WDOG1].base, 367 memmap[MICROCHIP_PFSOC_WDOG1].size); 368 create_unimplemented_device("microchip.pfsoc.watchdog2", 369 memmap[MICROCHIP_PFSOC_WDOG2].base, 370 memmap[MICROCHIP_PFSOC_WDOG2].size); 371 create_unimplemented_device("microchip.pfsoc.watchdog3", 372 memmap[MICROCHIP_PFSOC_WDOG3].base, 373 memmap[MICROCHIP_PFSOC_WDOG3].size); 374 create_unimplemented_device("microchip.pfsoc.watchdog4", 375 memmap[MICROCHIP_PFSOC_WDOG4].base, 376 memmap[MICROCHIP_PFSOC_WDOG4].size); 377 378 /* SPI */ 379 create_unimplemented_device("microchip.pfsoc.spi0", 380 memmap[MICROCHIP_PFSOC_SPI0].base, 381 memmap[MICROCHIP_PFSOC_SPI0].size); 382 create_unimplemented_device("microchip.pfsoc.spi1", 383 memmap[MICROCHIP_PFSOC_SPI1].base, 384 memmap[MICROCHIP_PFSOC_SPI1].size); 385 386 /* I2C */ 387 create_unimplemented_device("microchip.pfsoc.i2c0", 388 memmap[MICROCHIP_PFSOC_I2C0].base, 389 memmap[MICROCHIP_PFSOC_I2C0].size); 390 create_unimplemented_device("microchip.pfsoc.i2c1", 391 memmap[MICROCHIP_PFSOC_I2C1].base, 392 memmap[MICROCHIP_PFSOC_I2C1].size); 393 394 /* CAN */ 395 create_unimplemented_device("microchip.pfsoc.can0", 396 memmap[MICROCHIP_PFSOC_CAN0].base, 397 memmap[MICROCHIP_PFSOC_CAN0].size); 398 create_unimplemented_device("microchip.pfsoc.can1", 399 memmap[MICROCHIP_PFSOC_CAN1].base, 400 memmap[MICROCHIP_PFSOC_CAN1].size); 401 402 /* USB */ 403 create_unimplemented_device("microchip.pfsoc.usb", 404 memmap[MICROCHIP_PFSOC_USB].base, 405 memmap[MICROCHIP_PFSOC_USB].size); 406 407 /* GEMs */ 408 409 nd = &nd_table[0]; 410 if (nd->used) { 411 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 412 qdev_set_nic_properties(DEVICE(&s->gem0), nd); 413 } 414 nd = &nd_table[1]; 415 if (nd->used) { 416 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 417 qdev_set_nic_properties(DEVICE(&s->gem1), nd); 418 } 419 420 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 421 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 422 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 423 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 424 memmap[MICROCHIP_PFSOC_GEM0].base); 425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 426 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 427 428 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 429 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 430 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 432 memmap[MICROCHIP_PFSOC_GEM1].base); 433 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 434 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 435 436 /* GPIOs */ 437 create_unimplemented_device("microchip.pfsoc.gpio0", 438 memmap[MICROCHIP_PFSOC_GPIO0].base, 439 memmap[MICROCHIP_PFSOC_GPIO0].size); 440 create_unimplemented_device("microchip.pfsoc.gpio1", 441 memmap[MICROCHIP_PFSOC_GPIO1].base, 442 memmap[MICROCHIP_PFSOC_GPIO1].size); 443 create_unimplemented_device("microchip.pfsoc.gpio2", 444 memmap[MICROCHIP_PFSOC_GPIO2].base, 445 memmap[MICROCHIP_PFSOC_GPIO2].size); 446 447 /* eNVM */ 448 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 449 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 450 &error_fatal); 451 memory_region_add_subregion(system_memory, 452 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 453 envm_data); 454 455 /* IOSCB */ 456 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 458 memmap[MICROCHIP_PFSOC_IOSCB].base); 459 460 /* FPGA Fabric */ 461 create_unimplemented_device("microchip.pfsoc.fabricfic3", 462 memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, 463 memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); 464 465 /* QSPI Flash */ 466 memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 467 "microchip.pfsoc.qspi_xip", 468 memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 469 &error_fatal); 470 memory_region_add_subregion(system_memory, 471 memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 472 qspi_xip_mem); 473 } 474 475 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 476 { 477 DeviceClass *dc = DEVICE_CLASS(oc); 478 479 dc->realize = microchip_pfsoc_soc_realize; 480 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 481 dc->user_creatable = false; 482 } 483 484 static const TypeInfo microchip_pfsoc_soc_type_info = { 485 .name = TYPE_MICROCHIP_PFSOC, 486 .parent = TYPE_DEVICE, 487 .instance_size = sizeof(MicrochipPFSoCState), 488 .instance_init = microchip_pfsoc_soc_instance_init, 489 .class_init = microchip_pfsoc_soc_class_init, 490 }; 491 492 static void microchip_pfsoc_soc_register_types(void) 493 { 494 type_register_static(µchip_pfsoc_soc_type_info); 495 } 496 497 type_init(microchip_pfsoc_soc_register_types) 498 499 static void microchip_icicle_kit_machine_init(MachineState *machine) 500 { 501 MachineClass *mc = MACHINE_GET_CLASS(machine); 502 const MemMapEntry *memmap = microchip_pfsoc_memmap; 503 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 504 MemoryRegion *system_memory = get_system_memory(); 505 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 506 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 507 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 508 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 509 uint64_t mem_low_size, mem_high_size; 510 hwaddr firmware_load_addr; 511 const char *firmware_name; 512 bool kernel_as_payload = false; 513 target_ulong firmware_end_addr, kernel_start_addr; 514 uint64_t kernel_entry; 515 uint32_t fdt_load_addr; 516 DriveInfo *dinfo = drive_get(IF_SD, 0, 0); 517 518 /* Sanity check on RAM size */ 519 if (machine->ram_size < mc->default_ram_size) { 520 char *sz = size_to_str(mc->default_ram_size); 521 error_report("Invalid RAM size, should be bigger than %s", sz); 522 g_free(sz); 523 exit(EXIT_FAILURE); 524 } 525 526 /* Initialize SoC */ 527 object_initialize_child(OBJECT(machine), "soc", &s->soc, 528 TYPE_MICROCHIP_PFSOC); 529 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 530 531 /* Split RAM into low and high regions using aliases to machine->ram */ 532 mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; 533 mem_high_size = machine->ram_size - mem_low_size; 534 memory_region_init_alias(mem_low, NULL, 535 "microchip.icicle.kit.ram_low", machine->ram, 536 0, mem_low_size); 537 memory_region_init_alias(mem_high, NULL, 538 "microchip.icicle.kit.ram_high", machine->ram, 539 mem_low_size, mem_high_size); 540 541 /* Register RAM */ 542 memory_region_add_subregion(system_memory, 543 memmap[MICROCHIP_PFSOC_DRAM_LO].base, 544 mem_low); 545 memory_region_add_subregion(system_memory, 546 memmap[MICROCHIP_PFSOC_DRAM_HI].base, 547 mem_high); 548 549 /* Create aliases for the low and high RAM regions */ 550 memory_region_init_alias(mem_low_alias, NULL, 551 "microchip.icicle.kit.ram_low.alias", 552 mem_low, 0, mem_low_size); 553 memory_region_add_subregion(system_memory, 554 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 555 mem_low_alias); 556 memory_region_init_alias(mem_high_alias, NULL, 557 "microchip.icicle.kit.ram_high.alias", 558 mem_high, 0, mem_high_size); 559 memory_region_add_subregion(system_memory, 560 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 561 mem_high_alias); 562 563 /* Attach an SD card */ 564 if (dinfo) { 565 CadenceSDHCIState *sdhci = &(s->soc.sdhci); 566 DeviceState *card = qdev_new(TYPE_SD_CARD); 567 568 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 569 &error_fatal); 570 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 571 } 572 573 /* 574 * We follow the following table to select which payload we execute. 575 * 576 * -bios | -kernel | payload 577 * -------+------------+-------- 578 * N | N | HSS 579 * Y | don't care | HSS 580 * N | Y | kernel 581 * 582 * This ensures backwards compatibility with how we used to expose -bios 583 * to users but allows them to run through direct kernel booting as well. 584 * 585 * When -kernel is used for direct boot, -dtb must be present to provide 586 * a valid device tree for the board, as we don't generate device tree. 587 */ 588 589 if (machine->kernel_filename && machine->dtb) { 590 int fdt_size; 591 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 592 if (!machine->fdt) { 593 error_report("load_device_tree() failed"); 594 exit(1); 595 } 596 597 firmware_name = RISCV64_BIOS_BIN; 598 firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base; 599 kernel_as_payload = true; 600 } 601 602 if (!kernel_as_payload) { 603 firmware_name = BIOS_FILENAME; 604 firmware_load_addr = RESET_VECTOR; 605 } 606 607 /* Load the firmware */ 608 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 609 firmware_load_addr, NULL); 610 611 if (kernel_as_payload) { 612 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 613 firmware_end_addr); 614 615 kernel_entry = riscv_load_kernel(machine->kernel_filename, 616 kernel_start_addr, NULL); 617 618 if (machine->initrd_filename) { 619 hwaddr start; 620 hwaddr end = riscv_load_initrd(machine->initrd_filename, 621 machine->ram_size, kernel_entry, 622 &start); 623 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 624 "linux,initrd-start", start); 625 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 626 "linux,initrd-end", end); 627 } 628 629 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 630 qemu_fdt_setprop_string(machine->fdt, "/chosen", 631 "bootargs", machine->kernel_cmdline); 632 } 633 634 /* Compute the fdt load address in dram */ 635 fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, 636 machine->ram_size, machine->fdt); 637 /* Load the reset vector */ 638 riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, 639 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 640 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 641 kernel_entry, fdt_load_addr); 642 } 643 } 644 645 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 646 { 647 MachineClass *mc = MACHINE_CLASS(oc); 648 649 mc->desc = "Microchip PolarFire SoC Icicle Kit"; 650 mc->init = microchip_icicle_kit_machine_init; 651 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 652 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 653 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 654 mc->default_cpus = mc->min_cpus; 655 mc->default_ram_id = "microchip.icicle.kit.ram"; 656 657 /* 658 * Map 513 MiB high memory, the mimimum required high memory size, because 659 * HSS will do memory test against the high memory address range regardless 660 * of physical memory installed. 661 * 662 * See memory_tests() in mss_ddr.c in the HSS source code. 663 */ 664 mc->default_ram_size = 1537 * MiB; 665 } 666 667 static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 668 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 669 .parent = TYPE_MACHINE, 670 .class_init = microchip_icicle_kit_machine_class_init, 671 .instance_size = sizeof(MicrochipIcicleKitState), 672 }; 673 674 static void microchip_icicle_kit_machine_init_register_types(void) 675 { 676 type_register_static(µchip_icicle_kit_machine_typeinfo); 677 } 678 679 type_init(microchip_icicle_kit_machine_init_register_types)