boot.c (13098B)
1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 return harts->harts[0].env.misa_mxl_max == MXL_RV32; 40 } 41 42 /* 43 * Return the per-socket PLIC hart topology configuration string 44 * (caller must free with g_free()) 45 */ 46 char *riscv_plic_hart_config_string(int hart_count) 47 { 48 g_autofree const char **vals = g_new(const char *, hart_count + 1); 49 int i; 50 51 for (i = 0; i < hart_count; i++) { 52 CPUState *cs = qemu_get_cpu(i); 53 CPURISCVState *env = &RISCV_CPU(cs)->env; 54 55 if (kvm_enabled()) { 56 vals[i] = "S"; 57 } else if (riscv_has_ext(env, RVS)) { 58 vals[i] = "MS"; 59 } else { 60 vals[i] = "M"; 61 } 62 } 63 vals[i] = NULL; 64 65 /* g_strjoinv() obliges us to cast away const here */ 66 return g_strjoinv(",", (char **)vals); 67 } 68 69 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 70 target_ulong firmware_end_addr) { 71 if (riscv_is_32bit(harts)) { 72 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 73 } else { 74 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 75 } 76 } 77 78 target_ulong riscv_find_and_load_firmware(MachineState *machine, 79 const char *default_machine_firmware, 80 hwaddr firmware_load_addr, 81 symbol_fn_t sym_cb) 82 { 83 char *firmware_filename = NULL; 84 target_ulong firmware_end_addr = firmware_load_addr; 85 86 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 87 /* 88 * The user didn't specify -bios, or has specified "-bios default". 89 * That means we are going to load the OpenSBI binary included in 90 * the QEMU source. 91 */ 92 firmware_filename = riscv_find_firmware(default_machine_firmware); 93 } else if (strcmp(machine->firmware, "none")) { 94 firmware_filename = riscv_find_firmware(machine->firmware); 95 } 96 97 if (firmware_filename) { 98 /* If not "none" load the firmware */ 99 firmware_end_addr = riscv_load_firmware(firmware_filename, 100 firmware_load_addr, sym_cb); 101 g_free(firmware_filename); 102 } 103 104 return firmware_end_addr; 105 } 106 107 char *riscv_find_firmware(const char *firmware_filename) 108 { 109 char *filename; 110 111 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 112 if (filename == NULL) { 113 if (!qtest_enabled()) { 114 /* 115 * We only ship OpenSBI binary bios images in the QEMU source. 116 * For machines that use images other than the default bios, 117 * running QEMU test will complain hence let's suppress the error 118 * report for QEMU testing. 119 */ 120 error_report("Unable to load the RISC-V firmware \"%s\"", 121 firmware_filename); 122 exit(1); 123 } 124 } 125 126 return filename; 127 } 128 129 target_ulong riscv_load_firmware(const char *firmware_filename, 130 hwaddr firmware_load_addr, 131 symbol_fn_t sym_cb) 132 { 133 uint64_t firmware_entry, firmware_end; 134 ssize_t firmware_size; 135 136 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 137 &firmware_entry, NULL, &firmware_end, NULL, 138 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 139 return firmware_end; 140 } 141 142 firmware_size = load_image_targphys_as(firmware_filename, 143 firmware_load_addr, 144 current_machine->ram_size, NULL); 145 146 if (firmware_size > 0) { 147 return firmware_load_addr + firmware_size; 148 } 149 150 error_report("could not load firmware '%s'", firmware_filename); 151 exit(1); 152 } 153 154 target_ulong riscv_load_kernel(const char *kernel_filename, 155 target_ulong kernel_start_addr, 156 symbol_fn_t sym_cb) 157 { 158 uint64_t kernel_load_base, kernel_entry; 159 160 /* 161 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 162 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 163 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 164 * the (expected) load address load address. This allows kernels to have 165 * separate SBI and ELF entry points (used by FreeBSD, for example). 166 */ 167 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 168 NULL, &kernel_load_base, NULL, NULL, 0, 169 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 170 return kernel_load_base; 171 } 172 173 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 174 NULL, NULL, NULL) > 0) { 175 return kernel_entry; 176 } 177 178 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 179 current_machine->ram_size, NULL) > 0) { 180 return kernel_start_addr; 181 } 182 183 error_report("could not load kernel '%s'", kernel_filename); 184 exit(1); 185 } 186 187 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 188 uint64_t kernel_entry, hwaddr *start) 189 { 190 ssize_t size; 191 192 /* 193 * We want to put the initrd far enough into RAM that when the 194 * kernel is uncompressed it will not clobber the initrd. However 195 * on boards without much RAM we must ensure that we still leave 196 * enough room for a decent sized initrd, and on boards with large 197 * amounts of RAM we must avoid the initrd being so far up in RAM 198 * that it is outside lowmem and inaccessible to the kernel. 199 * So for boards with less than 256MB of RAM we put the initrd 200 * halfway into RAM, and for boards with 256MB of RAM or more we put 201 * the initrd at 128MB. 202 */ 203 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 204 205 size = load_ramdisk(filename, *start, mem_size - *start); 206 if (size == -1) { 207 size = load_image_targphys(filename, *start, mem_size - *start); 208 if (size == -1) { 209 error_report("could not load ramdisk '%s'", filename); 210 exit(1); 211 } 212 } 213 214 return *start + size; 215 } 216 217 uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 218 { 219 uint64_t temp, fdt_addr; 220 hwaddr dram_end = dram_base + mem_size; 221 int ret, fdtsize = fdt_totalsize(fdt); 222 223 if (fdtsize <= 0) { 224 error_report("invalid device-tree"); 225 exit(1); 226 } 227 228 /* 229 * We should put fdt as far as possible to avoid kernel/initrd overwriting 230 * its content. But it should be addressable by 32 bit system as well. 231 * Thus, put it at an 2MB aligned address that less than fdt size from the 232 * end of dram or 3GB whichever is lesser. 233 */ 234 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 235 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 236 237 ret = fdt_pack(fdt); 238 /* Should only fail if we've built a corrupted tree */ 239 g_assert(ret == 0); 240 /* copy in the device tree */ 241 qemu_fdt_dumpdtb(fdt, fdtsize); 242 243 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 244 &address_space_memory); 245 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 246 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 247 248 return fdt_addr; 249 } 250 251 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 252 hwaddr rom_size, uint32_t reset_vec_size, 253 uint64_t kernel_entry) 254 { 255 struct fw_dynamic_info dinfo; 256 size_t dinfo_len; 257 258 if (sizeof(dinfo.magic) == 4) { 259 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 260 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 261 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 262 dinfo.next_addr = cpu_to_le32(kernel_entry); 263 } else { 264 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 265 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 266 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 267 dinfo.next_addr = cpu_to_le64(kernel_entry); 268 } 269 dinfo.options = 0; 270 dinfo.boot_hart = 0; 271 dinfo_len = sizeof(dinfo); 272 273 /** 274 * copy the dynamic firmware info. This information is specific to 275 * OpenSBI but doesn't break any other firmware as long as they don't 276 * expect any certain value in "a2" register. 277 */ 278 if (dinfo_len > (rom_size - reset_vec_size)) { 279 error_report("not enough space to store dynamic firmware info"); 280 exit(1); 281 } 282 283 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 284 rom_base + reset_vec_size, 285 &address_space_memory); 286 } 287 288 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 289 hwaddr start_addr, 290 hwaddr rom_base, hwaddr rom_size, 291 uint64_t kernel_entry, 292 uint64_t fdt_load_addr) 293 { 294 int i; 295 uint32_t start_addr_hi32 = 0x00000000; 296 uint32_t fdt_load_addr_hi32 = 0x00000000; 297 298 if (!riscv_is_32bit(harts)) { 299 start_addr_hi32 = start_addr >> 32; 300 fdt_load_addr_hi32 = fdt_load_addr >> 32; 301 } 302 /* reset vector */ 303 uint32_t reset_vec[10] = { 304 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 305 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 306 0xf1402573, /* csrr a0, mhartid */ 307 0, 308 0, 309 0x00028067, /* jr t0 */ 310 start_addr, /* start: .dword */ 311 start_addr_hi32, 312 fdt_load_addr, /* fdt_laddr: .dword */ 313 fdt_load_addr_hi32, 314 /* fw_dyn: */ 315 }; 316 if (riscv_is_32bit(harts)) { 317 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 318 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 319 } else { 320 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 321 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 322 } 323 324 /* copy in the reset vector in little_endian byte order */ 325 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 326 reset_vec[i] = cpu_to_le32(reset_vec[i]); 327 } 328 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 329 rom_base, &address_space_memory); 330 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 331 kernel_entry); 332 } 333 334 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 335 { 336 CPUState *cs; 337 338 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 339 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 340 riscv_cpu->env.kernel_addr = kernel_addr; 341 riscv_cpu->env.fdt_addr = fdt_addr; 342 } 343 } 344 345 void riscv_setup_firmware_boot(MachineState *machine) 346 { 347 if (machine->kernel_filename) { 348 FWCfgState *fw_cfg; 349 fw_cfg = fw_cfg_find(); 350 351 assert(fw_cfg); 352 /* 353 * Expose the kernel, the command line, and the initrd in fw_cfg. 354 * We don't process them here at all, it's all left to the 355 * firmware. 356 */ 357 load_image_to_fw_cfg(fw_cfg, 358 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 359 machine->kernel_filename, 360 true); 361 load_image_to_fw_cfg(fw_cfg, 362 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 363 machine->initrd_filename, false); 364 365 if (machine->kernel_cmdline) { 366 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 367 strlen(machine->kernel_cmdline) + 1); 368 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 369 machine->kernel_cmdline); 370 } 371 } 372 }