sam460ex.c (17711B)
1 /* 2 * QEMU aCube Sam460ex board emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2019 BALATON Zoltan 6 * 7 * This file is derived from hw/ppc440_bamboo.c, 8 * the copyright for that material belongs to the original owners. 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/units.h" 16 #include "qemu/datadir.h" 17 #include "qemu/error-report.h" 18 #include "qapi/error.h" 19 #include "hw/boards.h" 20 #include "sysemu/kvm.h" 21 #include "kvm_ppc.h" 22 #include "sysemu/device_tree.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "elf.h" 26 #include "exec/memory.h" 27 #include "ppc440.h" 28 #include "hw/block/flash.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/reset.h" 31 #include "hw/sysbus.h" 32 #include "hw/char/serial.h" 33 #include "hw/i2c/ppc4xx_i2c.h" 34 #include "hw/i2c/smbus_eeprom.h" 35 #include "hw/usb/hcd-ehci.h" 36 #include "hw/ppc/fdt.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/intc/ppc-uic.h" 39 40 #include <libfdt.h> 41 42 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb" 43 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin" 44 /* to extract the official U-Boot bin from the updater: */ 45 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \ 46 if=updater/updater-460 of=u-boot-sam460-20100605.bin */ 47 48 /* from Sam460 U-Boot include/configs/Sam460ex.h */ 49 #define FLASH_BASE 0xfff00000 50 #define FLASH_BASE_H 0x4 51 #define FLASH_SIZE (1 * MiB) 52 #define UBOOT_LOAD_BASE 0xfff80000 53 #define UBOOT_SIZE 0x00080000 54 #define UBOOT_ENTRY 0xfffffffc 55 56 /* from U-Boot */ 57 #define EPAPR_MAGIC (0x45504150) 58 #define KERNEL_ADDR 0x1000000 59 #define FDT_ADDR 0x1800000 60 #define RAMDISK_ADDR 0x1900000 61 62 /* Sam460ex IRQ MAP: 63 IRQ0 = ETH_INT 64 IRQ1 = FPGA_INT 65 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB) 66 IRQ3 = FPGA_INT2 67 IRQ11 = RTC_INT 68 IRQ12 = SM502_INT 69 */ 70 71 #define CPU_FREQ 1150000000 72 #define PLB_FREQ 230000000 73 #define OPB_FREQ 115000000 74 #define EBC_FREQ 115000000 75 #define UART_FREQ 11059200 76 77 struct boot_info { 78 uint32_t dt_base; 79 uint32_t dt_size; 80 uint32_t entry; 81 }; 82 83 static int sam460ex_load_uboot(void) 84 { 85 /* 86 * This first creates 1MiB of flash memory mapped at the end of 87 * the 32-bit address space (0xFFF00000..0xFFFFFFFF). 88 * 89 * If_PFLASH unit 0 is defined, the flash memory is initialized 90 * from that block backend. 91 * 92 * Else, it's initialized to zero. And then 512KiB of ROM get 93 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF), 94 * initialized from u-boot-sam460-20100605.bin. 95 * 96 * This doesn't smell right. 97 * 98 * The physical hardware appears to have 512KiB flash memory. 99 * 100 * TODO Figure out what we really need here, and clean this up. 101 */ 102 103 DriveInfo *dinfo; 104 105 dinfo = drive_get(IF_PFLASH, 0, 0); 106 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), 107 "sam460ex.flash", FLASH_SIZE, 108 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 109 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { 110 error_report("Error registering flash memory"); 111 /* XXX: return an error instead? */ 112 exit(1); 113 } 114 115 if (!dinfo) { 116 /*error_report("No flash image given with the 'pflash' parameter," 117 " using default u-boot image");*/ 118 rom_add_file_fixed(UBOOT_FILENAME, 119 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32), 120 -1); 121 } 122 123 return 0; 124 } 125 126 static int sam460ex_load_device_tree(MachineState *machine, 127 hwaddr addr, 128 hwaddr initrd_base, 129 hwaddr initrd_size) 130 { 131 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(machine->ram_size) }; 132 char *filename; 133 int fdt_size; 134 void *fdt; 135 uint32_t tb_freq = CPU_FREQ; 136 uint32_t clock_freq = CPU_FREQ; 137 int offset; 138 139 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 140 if (!filename) { 141 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE); 142 exit(1); 143 } 144 fdt = load_device_tree(filename, &fdt_size); 145 if (!fdt) { 146 error_report("Couldn't load dtb file `%s'", filename); 147 g_free(filename); 148 exit(1); 149 } 150 g_free(filename); 151 152 /* Manipulate device tree in memory. */ 153 154 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 155 sizeof(mem_reg_property)); 156 157 /* default FDT doesn't have a /chosen node... */ 158 qemu_fdt_add_subnode(fdt, "/chosen"); 159 160 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); 161 162 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 163 (initrd_base + initrd_size)); 164 165 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 166 machine->kernel_cmdline); 167 168 /* Copy data from the host device tree into the guest. Since the guest can 169 * directly access the timebase without host involvement, we must expose 170 * the correct frequencies. */ 171 if (kvm_enabled()) { 172 tb_freq = kvmppc_get_tbfreq(); 173 clock_freq = kvmppc_get_clockfreq(); 174 } 175 176 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 177 clock_freq); 178 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 179 tb_freq); 180 181 /* Remove cpm node if it exists (it is not emulated) */ 182 offset = fdt_path_offset(fdt, "/cpm"); 183 if (offset >= 0) { 184 _FDT(fdt_nop_node(fdt, offset)); 185 } 186 187 /* set serial port clocks */ 188 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550"); 189 while (offset >= 0) { 190 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ)); 191 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550"); 192 } 193 194 /* some more clocks */ 195 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency", 196 PLB_FREQ); 197 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency", 198 OPB_FREQ); 199 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency", 200 EBC_FREQ); 201 202 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 203 204 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 205 machine->fdt = fdt; 206 207 return fdt_size; 208 } 209 210 /* Create reset TLB entries for BookE, mapping only the flash memory. */ 211 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env) 212 { 213 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 214 215 /* on reset the flash is mapped by a shadow TLB, 216 * but since we don't implement them we need to use 217 * the same values U-Boot will use to avoid a fault. 218 */ 219 tlb->attr = 0; 220 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 221 tlb->size = 0x10000000; /* up to 0xffffffff */ 222 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK; 223 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4; 224 tlb->PID = 0; 225 } 226 227 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 228 static void mmubooke_create_initial_mapping(CPUPPCState *env, 229 target_ulong va, 230 hwaddr pa) 231 { 232 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 233 234 tlb->attr = 0; 235 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 236 tlb->size = 1 << 31; /* up to 0x80000000 */ 237 tlb->EPN = va & TARGET_PAGE_MASK; 238 tlb->RPN = pa & TARGET_PAGE_MASK; 239 tlb->PID = 0; 240 } 241 242 static void main_cpu_reset(void *opaque) 243 { 244 PowerPCCPU *cpu = opaque; 245 CPUPPCState *env = &cpu->env; 246 struct boot_info *bi = env->load_info; 247 248 cpu_reset(CPU(cpu)); 249 250 /* either we have a kernel to boot or we jump to U-Boot */ 251 if (bi->entry != UBOOT_ENTRY) { 252 env->gpr[1] = (16 * MiB) - 8; 253 env->gpr[3] = FDT_ADDR; 254 env->nip = bi->entry; 255 256 /* Create a mapping for the kernel. */ 257 mmubooke_create_initial_mapping(env, 0, 0); 258 env->gpr[6] = tswap32(EPAPR_MAGIC); 259 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */ 260 261 } else { 262 env->nip = UBOOT_ENTRY; 263 mmubooke_create_initial_mapping_uboot(env); 264 } 265 } 266 267 static void sam460ex_init(MachineState *machine) 268 { 269 MemoryRegion *address_space_mem = get_system_memory(); 270 MemoryRegion *isa = g_new(MemoryRegion, 1); 271 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); 272 DeviceState *uic[4]; 273 int i; 274 PCIBus *pci_bus; 275 PowerPCCPU *cpu; 276 CPUPPCState *env; 277 I2CBus *i2c; 278 hwaddr entry = UBOOT_ENTRY; 279 target_long initrd_size = 0; 280 DeviceState *dev; 281 SysBusDevice *sbdev; 282 struct boot_info *boot_info; 283 uint8_t *spd_data; 284 int success; 285 286 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 287 env = &cpu->env; 288 if (env->mmu_model != POWERPC_MMU_BOOKE) { 289 error_report("Only MMU model BookE is supported by this machine."); 290 exit(1); 291 } 292 293 qemu_register_reset(main_cpu_reset, cpu); 294 boot_info = g_malloc0(sizeof(*boot_info)); 295 env->load_info = boot_info; 296 297 ppc_booke_timers_init(cpu, CPU_FREQ, 0); 298 ppc_dcr_init(env, NULL, NULL); 299 300 /* PLB arbitrer */ 301 dev = qdev_new(TYPE_PPC4xx_PLB); 302 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 303 object_unref(OBJECT(dev)); 304 305 /* interrupt controllers */ 306 for (i = 0; i < ARRAY_SIZE(uic); i++) { 307 /* 308 * UICs 1, 2 and 3 are cascaded through UIC 0. 309 * input_ints[n] is the interrupt number on UIC 0 which 310 * the INT output of UIC n is connected to. The CINT output 311 * of UIC n connects to input_ints[n] + 1. 312 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's 313 * INT and CINT outputs are connected to the CPU. 314 */ 315 const int input_ints[] = { -1, 30, 10, 16 }; 316 317 uic[i] = qdev_new(TYPE_PPC_UIC); 318 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); 319 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal); 320 object_unref(OBJECT(uic[i])); 321 322 sbdev = SYS_BUS_DEVICE(uic[i]); 323 if (i == 0) { 324 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 325 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT)); 326 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 327 qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT)); 328 } else { 329 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT, 330 qdev_get_gpio_in(uic[0], input_ints[i])); 331 sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT, 332 qdev_get_gpio_in(uic[0], input_ints[i] + 1)); 333 } 334 } 335 336 /* SDRAM controller */ 337 /* The SoC could also handle 4 GiB but firmware does not work with that. */ 338 if (machine->ram_size > 2 * GiB) { 339 error_report("Memory over 2 GiB is not supported"); 340 exit(1); 341 } 342 /* Firmware needs at least 64 MiB */ 343 if (machine->ram_size < 64 * MiB) { 344 error_report("Memory below 64 MiB is not supported"); 345 exit(1); 346 } 347 dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2); 348 object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), 349 &error_abort); 350 /* 351 * Put all RAM on first bank because board has one slot 352 * and firmware only checks that 353 */ 354 object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); 355 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 356 object_unref(OBJECT(dev)); 357 /* FIXME: does 460EX have ECC interrupts? */ 358 /* Enable SDRAM memory regions as we may boot without firmware */ 359 ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev)); 360 361 /* IIC controllers and devices */ 362 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, 363 qdev_get_gpio_in(uic[0], 2)); 364 i2c = PPC4xx_I2C(dev)->bus; 365 /* SPD EEPROM on RAM module */ 366 spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2, 367 machine->ram_size); 368 spd_data[20] = 4; /* SO-DIMM module */ 369 smbus_eeprom_init_one(i2c, 0x50, spd_data); 370 /* RTC */ 371 i2c_slave_create_simple(i2c, "m41t80", 0x68); 372 373 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, 374 qdev_get_gpio_in(uic[0], 3)); 375 376 /* External bus controller */ 377 dev = qdev_new(TYPE_PPC4xx_EBC); 378 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 379 object_unref(OBJECT(dev)); 380 381 /* CPR */ 382 ppc4xx_cpr_init(env); 383 384 /* PLB to AHB bridge */ 385 ppc4xx_ahb_init(env); 386 387 /* System DCRs */ 388 ppc4xx_sdr_init(env); 389 390 /* MAL */ 391 dev = qdev_new(TYPE_PPC4xx_MAL); 392 qdev_prop_set_uint32(dev, "txc-num", 4); 393 qdev_prop_set_uint32(dev, "rxc-num", 16); 394 ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); 395 object_unref(OBJECT(dev)); 396 sbdev = SYS_BUS_DEVICE(dev); 397 for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) { 398 sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i)); 399 } 400 401 /* DMA */ 402 ppc4xx_dma_init(env, 0x200); 403 404 /* 256K of L2 cache as memory */ 405 ppc4xx_l2sram_init(env); 406 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */ 407 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB, 408 &error_abort); 409 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram); 410 411 /* USB */ 412 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, 413 qdev_get_gpio_in(uic[2], 29)); 414 dev = qdev_new("sysbus-ohci"); 415 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 416 qdev_prop_set_uint32(dev, "num-ports", 6); 417 sbdev = SYS_BUS_DEVICE(dev); 418 sysbus_realize_and_unref(sbdev, &error_fatal); 419 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 420 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); 421 usb_create_simple(usb_bus_find(-1), "usb-kbd"); 422 usb_create_simple(usb_bus_find(-1), "usb-mouse"); 423 424 /* PCI bus */ 425 ppc460ex_pcie_init(env); 426 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ 427 dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, 428 qdev_get_gpio_in(uic[1], 0)); 429 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 430 431 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(), 432 0, 0x10000); 433 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa); 434 435 /* PCI devices */ 436 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501"); 437 /* SoC has a single SATA port but we don't emulate that yet 438 * However, firmware and usual clients have driver for SiI311x 439 * so add one for convenience by default */ 440 if (defaults_enabled()) { 441 pci_create_simple(pci_bus, -1, "sii3112"); 442 } 443 444 /* SoC has 4 UARTs 445 * but board has only one wired and two are present in fdt */ 446 if (serial_hd(0) != NULL) { 447 serial_mm_init(address_space_mem, 0x4ef600300, 0, 448 qdev_get_gpio_in(uic[1], 1), 449 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 450 DEVICE_BIG_ENDIAN); 451 } 452 if (serial_hd(1) != NULL) { 453 serial_mm_init(address_space_mem, 0x4ef600400, 0, 454 qdev_get_gpio_in(uic[0], 1), 455 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 456 DEVICE_BIG_ENDIAN); 457 } 458 459 /* Load U-Boot image. */ 460 if (!machine->kernel_filename) { 461 success = sam460ex_load_uboot(); 462 if (success < 0) { 463 error_report("could not load firmware"); 464 exit(1); 465 } 466 } 467 468 /* Load kernel. */ 469 if (machine->kernel_filename) { 470 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 471 success = load_uimage(machine->kernel_filename, &entry, &loadaddr, 472 NULL, NULL, NULL); 473 if (success < 0) { 474 uint64_t elf_entry; 475 476 success = load_elf(machine->kernel_filename, NULL, NULL, NULL, 477 &elf_entry, NULL, NULL, NULL, 478 1, PPC_ELF_MACHINE, 0, 0); 479 entry = elf_entry; 480 } 481 /* XXX try again as binary */ 482 if (success < 0) { 483 error_report("could not load kernel '%s'", 484 machine->kernel_filename); 485 exit(1); 486 } 487 } 488 489 /* Load initrd. */ 490 if (machine->initrd_filename) { 491 initrd_size = load_image_targphys(machine->initrd_filename, 492 RAMDISK_ADDR, 493 machine->ram_size - RAMDISK_ADDR); 494 if (initrd_size < 0) { 495 error_report("could not load ram disk '%s' at %x", 496 machine->initrd_filename, RAMDISK_ADDR); 497 exit(1); 498 } 499 } 500 501 /* If we're loading a kernel directly, we must load the device tree too. */ 502 if (machine->kernel_filename) { 503 int dt_size; 504 505 dt_size = sam460ex_load_device_tree(machine, FDT_ADDR, 506 RAMDISK_ADDR, initrd_size); 507 508 boot_info->dt_base = FDT_ADDR; 509 boot_info->dt_size = dt_size; 510 } 511 512 boot_info->entry = entry; 513 } 514 515 static void sam460ex_machine_init(MachineClass *mc) 516 { 517 mc->desc = "aCube Sam460ex"; 518 mc->init = sam460ex_init; 519 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 520 mc->default_ram_size = 512 * MiB; 521 mc->default_ram_id = "ppc4xx.sdram"; 522 } 523 524 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)