pnv_psi.c (31173B)
1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "target/ppc/cpu.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "sysemu/reset.h" 26 #include "qapi/error.h" 27 #include "monitor/monitor.h" 28 29 30 #include "hw/ppc/fdt.h" 31 #include "hw/ppc/pnv.h" 32 #include "hw/ppc/pnv_xscom.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/ppc/pnv_psi.h" 35 36 #include <libfdt.h> 37 38 #define PSIHB_XSCOM_FIR_RW 0x00 39 #define PSIHB_XSCOM_FIR_AND 0x01 40 #define PSIHB_XSCOM_FIR_OR 0x02 41 #define PSIHB_XSCOM_FIRMASK_RW 0x03 42 #define PSIHB_XSCOM_FIRMASK_AND 0x04 43 #define PSIHB_XSCOM_FIRMASK_OR 0x05 44 #define PSIHB_XSCOM_FIRACT0 0x06 45 #define PSIHB_XSCOM_FIRACT1 0x07 46 47 /* Host Bridge Base Address Register */ 48 #define PSIHB_XSCOM_BAR 0x0a 49 #define PSIHB_BAR_EN 0x0000000000000001ull 50 51 /* FSP Base Address Register */ 52 #define PSIHB_XSCOM_FSPBAR 0x0b 53 54 /* PSI Host Bridge Control/Status Register */ 55 #define PSIHB_XSCOM_CR 0x0e 56 #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull 57 #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull 58 #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull 59 #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull 60 #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull 61 #define PSIHB_CR_FSP_RESET 0x0200000000000000ull 62 #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull 63 #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull 64 #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull 65 #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull 66 #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull 67 /* and more ... */ 68 69 /* PSIHB Status / Error Mask Register */ 70 #define PSIHB_XSCOM_SEMR 0x0f 71 72 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */ 73 #define PSIHB_XSCOM_XIVR_FSP 0x10 74 #define PSIHB_XIVR_SERVER_SH 40 75 #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) 76 #define PSIHB_XIVR_PRIO_SH 32 77 #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) 78 #define PSIHB_XIVR_SRC_SH 29 79 #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) 80 #define PSIHB_XIVR_PENDING 0x01000000ull 81 82 /* PSI Host Bridge Set Control/ Status Register */ 83 #define PSIHB_XSCOM_SCR 0x12 84 85 /* PSI Host Bridge Clear Control/ Status Register */ 86 #define PSIHB_XSCOM_CCR 0x13 87 88 /* DMA Upper Address Register */ 89 #define PSIHB_XSCOM_DMA_UPADD 0x14 90 91 /* Interrupt Status */ 92 #define PSIHB_XSCOM_IRQ_STAT 0x15 93 #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull 94 #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull 95 #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull 96 #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull 97 #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull 98 99 /* remaining XIVR */ 100 #define PSIHB_XSCOM_XIVR_OCC 0x16 101 #define PSIHB_XSCOM_XIVR_FSI 0x17 102 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18 103 #define PSIHB_XSCOM_XIVR_LOCERR 0x19 104 #define PSIHB_XSCOM_XIVR_EXT 0x1a 105 106 /* Interrupt Requester Source Compare Register */ 107 #define PSIHB_XSCOM_IRSN 0x1b 108 #define PSIHB_IRSN_COMP_SH 45 109 #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) 110 #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull 111 #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull 112 #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull 113 #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull 114 #define PSIHB_IRSN_COMPMASK_SH 13 115 #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH) 116 117 #define PSIHB_BAR_MASK 0x0003fffffff00000ull 118 #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull 119 120 #define PSIHB9_BAR_MASK 0x00fffffffff00000ull 121 #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull 122 123 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) 124 125 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) 126 { 127 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); 128 MemoryRegion *sysmem = get_system_memory(); 129 uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; 130 131 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN); 132 133 /* Update MR, always remove it first */ 134 if (old & PSIHB_BAR_EN) { 135 memory_region_del_subregion(sysmem, &psi->regs_mr); 136 } 137 138 /* Then add it back if needed */ 139 if (bar & PSIHB_BAR_EN) { 140 uint64_t addr = bar & ppc->bar_mask; 141 memory_region_add_subregion(sysmem, addr, &psi->regs_mr); 142 } 143 } 144 145 static void pnv_psi_update_fsp_mr(PnvPsi *psi) 146 { 147 /* TODO: Update FSP MR if/when we support FSP BAR */ 148 } 149 150 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) 151 { 152 uint64_t old = psi->regs[PSIHB_XSCOM_CR]; 153 154 psi->regs[PSIHB_XSCOM_CR] = cr; 155 156 /* Check some bit changes */ 157 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { 158 pnv_psi_update_fsp_mr(psi); 159 } 160 } 161 162 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) 163 { 164 ICSState *ics = &PNV8_PSI(psi)->ics; 165 166 /* In this model we ignore the up/down enable bits for now 167 * as SW doesn't use them (other than setting them at boot). 168 * We ignore IRQ_MUX, its meaning isn't clear and we don't use 169 * it and finally we ignore reset (XXX fix that ?) 170 */ 171 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | 172 PSIHB_IRSN_IRQ_MUX | 173 PSIHB_IRSN_IRQ_RESET | 174 PSIHB_IRSN_DOWNSTREAM_EN | 175 PSIHB_IRSN_UPSTREAM_EN); 176 177 /* We ignore the compare mask as well, our ICS emulation is too 178 * simplistic to make any use if it, and we extract the offset 179 * from the compare value 180 */ 181 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; 182 } 183 184 /* 185 * FSP and PSI interrupts are muxed under the same number. 186 */ 187 static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = { 188 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP, 189 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC, 190 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI, 191 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C, 192 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR, 193 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT, 194 }; 195 196 static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = { 197 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR, 198 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT, 199 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT, 200 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT, 201 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT, 202 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT, 203 }; 204 205 static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = { 206 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ, 207 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC, 208 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI, 209 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C, 210 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR, 211 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT, 212 }; 213 214 static void pnv_psi_power8_set_irq(void *opaque, int irq, int state) 215 { 216 PnvPsi *psi = opaque; 217 uint32_t xivr_reg; 218 uint32_t stat_reg; 219 uint32_t src; 220 bool masked; 221 222 xivr_reg = xivr_regs[irq]; 223 stat_reg = stat_regs[irq]; 224 225 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 226 if (state) { 227 psi->regs[stat_reg] |= stat_bits[irq]; 228 /* TODO: optimization, check mask here. That means 229 * re-evaluating when unmasking 230 */ 231 qemu_irq_raise(psi->qirqs[src]); 232 } else { 233 psi->regs[stat_reg] &= ~stat_bits[irq]; 234 235 /* FSP and PSI are muxed so don't lower if either is still set */ 236 if (stat_reg != PSIHB_XSCOM_CR || 237 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { 238 qemu_irq_lower(psi->qirqs[src]); 239 } else { 240 state = true; 241 } 242 } 243 244 /* Note about the emulation of the pending bit: This isn't 245 * entirely correct. The pending bit should be cleared when the 246 * EOI has been received. However, we don't have callbacks on EOI 247 * (especially not under KVM) so no way to emulate that properly, 248 * so instead we just set that bit as the logical "output" of the 249 * XIVR (ie pending & !masked) 250 * 251 * CLG: We could define a new ICS object with a custom eoi() 252 * handler to clear the pending bit. But I am not sure this would 253 * be useful for the software anyhow. 254 */ 255 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; 256 if (state && !masked) { 257 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; 258 } else { 259 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; 260 } 261 } 262 263 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) 264 { 265 ICSState *ics = &PNV8_PSI(psi)->ics; 266 uint16_t server; 267 uint8_t prio; 268 uint8_t src; 269 270 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | 271 (val & (PSIHB_XIVR_SERVER_MSK | 272 PSIHB_XIVR_PRIO_MSK | 273 PSIHB_XIVR_SRC_MSK)); 274 val = psi->regs[reg]; 275 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; 276 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; 277 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 278 279 if (src >= PSI_NUM_INTERRUPTS) { 280 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src); 281 return; 282 } 283 284 /* Remove pending bit if the IRQ is masked */ 285 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { 286 psi->regs[reg] &= ~PSIHB_XIVR_PENDING; 287 } 288 289 /* The low order 2 bits are the link pointer (Type II interrupts). 290 * Shift back to get a valid IRQ server. 291 */ 292 server >>= 2; 293 294 /* Now because of source remapping, weird things can happen 295 * if you change the source number dynamically, our simple ICS 296 * doesn't deal with remapping. So we just poke a different 297 * ICS entry based on what source number was written. This will 298 * do for now but a more accurate implementation would instead 299 * use a fixed server/prio and a remapper of the generated irq. 300 */ 301 ics_write_xive(ics, src, server, prio, prio); 302 } 303 304 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) 305 { 306 uint64_t val = 0xffffffffffffffffull; 307 308 switch (offset) { 309 case PSIHB_XSCOM_FIR_RW: 310 case PSIHB_XSCOM_FIRACT0: 311 case PSIHB_XSCOM_FIRACT1: 312 case PSIHB_XSCOM_BAR: 313 case PSIHB_XSCOM_FSPBAR: 314 case PSIHB_XSCOM_CR: 315 case PSIHB_XSCOM_XIVR_FSP: 316 case PSIHB_XSCOM_XIVR_OCC: 317 case PSIHB_XSCOM_XIVR_FSI: 318 case PSIHB_XSCOM_XIVR_LPCI2C: 319 case PSIHB_XSCOM_XIVR_LOCERR: 320 case PSIHB_XSCOM_XIVR_EXT: 321 case PSIHB_XSCOM_IRQ_STAT: 322 case PSIHB_XSCOM_SEMR: 323 case PSIHB_XSCOM_DMA_UPADD: 324 case PSIHB_XSCOM_IRSN: 325 val = psi->regs[offset]; 326 break; 327 default: 328 qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset); 329 } 330 return val; 331 } 332 333 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, 334 bool mmio) 335 { 336 switch (offset) { 337 case PSIHB_XSCOM_FIR_RW: 338 case PSIHB_XSCOM_FIRACT0: 339 case PSIHB_XSCOM_FIRACT1: 340 case PSIHB_XSCOM_SEMR: 341 case PSIHB_XSCOM_DMA_UPADD: 342 psi->regs[offset] = val; 343 break; 344 case PSIHB_XSCOM_FIR_OR: 345 psi->regs[PSIHB_XSCOM_FIR_RW] |= val; 346 break; 347 case PSIHB_XSCOM_FIR_AND: 348 psi->regs[PSIHB_XSCOM_FIR_RW] &= val; 349 break; 350 case PSIHB_XSCOM_BAR: 351 /* Only XSCOM can write this one */ 352 if (!mmio) { 353 pnv_psi_set_bar(psi, val); 354 } else { 355 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n"); 356 } 357 break; 358 case PSIHB_XSCOM_FSPBAR: 359 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; 360 pnv_psi_update_fsp_mr(psi); 361 break; 362 case PSIHB_XSCOM_CR: 363 pnv_psi_set_cr(psi, val); 364 break; 365 case PSIHB_XSCOM_SCR: 366 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); 367 break; 368 case PSIHB_XSCOM_CCR: 369 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); 370 break; 371 case PSIHB_XSCOM_XIVR_FSP: 372 case PSIHB_XSCOM_XIVR_OCC: 373 case PSIHB_XSCOM_XIVR_FSI: 374 case PSIHB_XSCOM_XIVR_LPCI2C: 375 case PSIHB_XSCOM_XIVR_LOCERR: 376 case PSIHB_XSCOM_XIVR_EXT: 377 pnv_psi_set_xivr(psi, offset, val); 378 break; 379 case PSIHB_XSCOM_IRQ_STAT: 380 /* Read only */ 381 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n"); 382 break; 383 case PSIHB_XSCOM_IRSN: 384 pnv_psi_set_irsn(psi, val); 385 break; 386 default: 387 qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset); 388 } 389 } 390 391 /* 392 * The values of the registers when accessed through the MMIO region 393 * follow the relation : xscom = (mmio + 0x50) >> 3 394 */ 395 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) 396 { 397 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); 398 } 399 400 static void pnv_psi_mmio_write(void *opaque, hwaddr addr, 401 uint64_t val, unsigned size) 402 { 403 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); 404 } 405 406 static const MemoryRegionOps psi_mmio_ops = { 407 .read = pnv_psi_mmio_read, 408 .write = pnv_psi_mmio_write, 409 .endianness = DEVICE_BIG_ENDIAN, 410 .valid = { 411 .min_access_size = 8, 412 .max_access_size = 8, 413 }, 414 .impl = { 415 .min_access_size = 8, 416 .max_access_size = 8, 417 }, 418 }; 419 420 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size) 421 { 422 return pnv_psi_reg_read(opaque, addr >> 3, false); 423 } 424 425 static void pnv_psi_xscom_write(void *opaque, hwaddr addr, 426 uint64_t val, unsigned size) 427 { 428 pnv_psi_reg_write(opaque, addr >> 3, val, false); 429 } 430 431 static const MemoryRegionOps pnv_psi_xscom_ops = { 432 .read = pnv_psi_xscom_read, 433 .write = pnv_psi_xscom_write, 434 .endianness = DEVICE_BIG_ENDIAN, 435 .valid = { 436 .min_access_size = 8, 437 .max_access_size = 8, 438 }, 439 .impl = { 440 .min_access_size = 8, 441 .max_access_size = 8, 442 } 443 }; 444 445 static void pnv_psi_reset(DeviceState *dev) 446 { 447 PnvPsi *psi = PNV_PSI(dev); 448 449 memset(psi->regs, 0x0, sizeof(psi->regs)); 450 451 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; 452 } 453 454 static void pnv_psi_reset_handler(void *dev) 455 { 456 device_cold_reset(DEVICE(dev)); 457 } 458 459 static void pnv_psi_realize(DeviceState *dev, Error **errp) 460 { 461 PnvPsi *psi = PNV_PSI(dev); 462 463 /* Default BAR for MMIO region */ 464 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); 465 466 qemu_register_reset(pnv_psi_reset_handler, dev); 467 } 468 469 static void pnv_psi_power8_instance_init(Object *obj) 470 { 471 Pnv8Psi *psi8 = PNV8_PSI(obj); 472 473 object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS); 474 object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), 475 ICS_PROP_XICS); 476 } 477 478 static const uint8_t irq_to_xivr[] = { 479 PSIHB_XSCOM_XIVR_FSP, 480 PSIHB_XSCOM_XIVR_OCC, 481 PSIHB_XSCOM_XIVR_FSI, 482 PSIHB_XSCOM_XIVR_LPCI2C, 483 PSIHB_XSCOM_XIVR_LOCERR, 484 PSIHB_XSCOM_XIVR_EXT, 485 }; 486 487 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) 488 { 489 PnvPsi *psi = PNV_PSI(dev); 490 ICSState *ics = &PNV8_PSI(psi)->ics; 491 unsigned int i; 492 493 /* Create PSI interrupt control source */ 494 if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, 495 errp)) { 496 return; 497 } 498 if (!qdev_realize(DEVICE(ics), NULL, errp)) { 499 return; 500 } 501 502 for (i = 0; i < ics->nr_irqs; i++) { 503 ics_set_irq_type(ics, i, true); 504 } 505 506 qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs); 507 508 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); 509 510 /* XSCOM region for PSI registers */ 511 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, 512 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); 513 514 /* Initialize MMIO region */ 515 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, 516 "psihb", PNV_PSIHB_SIZE); 517 518 /* Default sources in XIVR */ 519 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { 520 uint8_t xivr = irq_to_xivr[i]; 521 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | 522 ((uint64_t) i << PSIHB_XIVR_SRC_SH); 523 } 524 525 pnv_psi_realize(dev, errp); 526 } 527 528 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 529 { 530 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); 531 char *name; 532 int offset; 533 uint32_t reg[] = { 534 cpu_to_be32(ppc->xscom_pcba), 535 cpu_to_be32(ppc->xscom_size) 536 }; 537 538 name = g_strdup_printf("psihb@%x", ppc->xscom_pcba); 539 offset = fdt_add_subnode(fdt, xscom_offset, name); 540 _FDT(offset); 541 g_free(name); 542 543 _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); 544 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); 545 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); 546 _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, 547 ppc->compat_size)); 548 return 0; 549 } 550 551 static Property pnv_psi_properties[] = { 552 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), 553 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), 554 DEFINE_PROP_END_OF_LIST(), 555 }; 556 557 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) 558 { 559 DeviceClass *dc = DEVICE_CLASS(klass); 560 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 561 static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; 562 563 dc->desc = "PowerNV PSI Controller POWER8"; 564 dc->realize = pnv_psi_power8_realize; 565 566 ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE; 567 ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; 568 ppc->bar_mask = PSIHB_BAR_MASK; 569 ppc->compat = compat; 570 ppc->compat_size = sizeof(compat); 571 } 572 573 static const TypeInfo pnv_psi_power8_info = { 574 .name = TYPE_PNV8_PSI, 575 .parent = TYPE_PNV_PSI, 576 .instance_size = sizeof(Pnv8Psi), 577 .instance_init = pnv_psi_power8_instance_init, 578 .class_init = pnv_psi_power8_class_init, 579 }; 580 581 582 /* Common registers */ 583 584 #define PSIHB9_CR 0x20 585 #define PSIHB9_SEMR 0x28 586 587 /* P9 registers */ 588 589 #define PSIHB9_INTERRUPT_CONTROL 0x58 590 #define PSIHB9_IRQ_METHOD PPC_BIT(0) 591 #define PSIHB9_IRQ_RESET PPC_BIT(1) 592 #define PSIHB9_ESB_CI_BASE 0x60 593 #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47) 594 #define PSIHB9_ESB_CI_VALID PPC_BIT(63) 595 #define PSIHB9_ESB_NOTIF_ADDR 0x68 596 #define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60) 597 #define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63) 598 #define PSIHB9_IVT_OFFSET 0x70 599 #define PSIHB9_IVT_OFF_SHIFT 32 600 601 #define PSIHB9_IRQ_LEVEL 0x78 /* assertion */ 602 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0) 603 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1) 604 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2) 605 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3) 606 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4) 607 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5) 608 #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6) 609 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7) 610 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8) 611 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9) 612 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10) 613 #define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11) 614 #define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12) 615 #define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13) 616 #define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14) 617 #define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15) 618 #define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16) 619 #define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19) 620 621 #define PSIHB9_IRQ_STAT 0x80 /* P bit */ 622 #define PSIHB9_IRQ_STAT_PSI PPC_BIT(0) 623 #define PSIHB9_IRQ_STAT_OCC PPC_BIT(1) 624 #define PSIHB9_IRQ_STAT_FSI PPC_BIT(2) 625 #define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3) 626 #define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4) 627 #define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5) 628 #define PSIHB9_IRQ_STAT_TPM PPC_BIT(6) 629 #define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7) 630 #define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8) 631 #define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9) 632 #define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10) 633 #define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11) 634 #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12) 635 #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13) 636 637 /* P10 register extensions */ 638 639 #define PSIHB10_CR PSIHB9_CR 640 #define PSIHB10_CR_STORE_EOI PPC_BIT(12) 641 642 #define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE 643 #define PSIHB10_ESB_CI_64K PPC_BIT(1) 644 645 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked) 646 { 647 PnvPsi *psi = PNV_PSI(xf); 648 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; 649 bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID; 650 uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID; 651 652 uint32_t offset = 653 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 654 uint64_t data = offset | srcno; 655 MemTxResult result; 656 657 if (pq_checked) { 658 data |= XIVE_TRIGGER_PQ; 659 } 660 661 if (!valid) { 662 return; 663 } 664 665 address_space_stq_be(&address_space_memory, notify_addr, data, 666 MEMTXATTRS_UNSPECIFIED, &result); 667 if (result != MEMTX_OK) { 668 qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%" 669 HWADDR_PRIx "\n", __func__, notif_port); 670 return; 671 } 672 } 673 674 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) 675 { 676 PnvPsi *psi = PNV_PSI(opaque); 677 uint32_t reg = PSIHB_REG(addr); 678 uint64_t val = -1; 679 680 switch (addr) { 681 case PSIHB9_CR: 682 case PSIHB9_SEMR: 683 /* FSP stuff */ 684 case PSIHB9_INTERRUPT_CONTROL: 685 case PSIHB9_ESB_CI_BASE: 686 case PSIHB9_ESB_NOTIF_ADDR: 687 case PSIHB9_IVT_OFFSET: 688 val = psi->regs[reg]; 689 break; 690 default: 691 qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr); 692 } 693 694 return val; 695 } 696 697 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, 698 uint64_t val, unsigned size) 699 { 700 PnvPsi *psi = PNV_PSI(opaque); 701 Pnv9Psi *psi9 = PNV9_PSI(psi); 702 uint32_t reg = PSIHB_REG(addr); 703 MemoryRegion *sysmem = get_system_memory(); 704 705 switch (addr) { 706 case PSIHB9_CR: 707 if (val & PSIHB10_CR_STORE_EOI) { 708 psi9->source.esb_flags |= XIVE_SRC_STORE_EOI; 709 } else { 710 psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI; 711 } 712 break; 713 714 case PSIHB9_SEMR: 715 /* FSP stuff */ 716 break; 717 case PSIHB9_INTERRUPT_CONTROL: 718 if (val & PSIHB9_IRQ_RESET) { 719 device_cold_reset(DEVICE(&psi9->source)); 720 } 721 psi->regs[reg] = val; 722 break; 723 724 case PSIHB9_ESB_CI_BASE: 725 if (val & PSIHB10_ESB_CI_64K) { 726 psi9->source.esb_shift = XIVE_ESB_64K; 727 } else { 728 psi9->source.esb_shift = XIVE_ESB_4K; 729 } 730 if (!(val & PSIHB9_ESB_CI_VALID)) { 731 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { 732 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio); 733 } 734 } else { 735 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { 736 hwaddr addr = val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K); 737 memory_region_add_subregion(sysmem, addr, 738 &psi9->source.esb_mmio); 739 } 740 } 741 psi->regs[reg] = val; 742 break; 743 744 case PSIHB9_ESB_NOTIF_ADDR: 745 psi->regs[reg] = val; 746 break; 747 case PSIHB9_IVT_OFFSET: 748 psi->regs[reg] = val; 749 break; 750 default: 751 qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr); 752 } 753 } 754 755 static const MemoryRegionOps pnv_psi_p9_mmio_ops = { 756 .read = pnv_psi_p9_mmio_read, 757 .write = pnv_psi_p9_mmio_write, 758 .endianness = DEVICE_BIG_ENDIAN, 759 .valid = { 760 .min_access_size = 8, 761 .max_access_size = 8, 762 }, 763 .impl = { 764 .min_access_size = 8, 765 .max_access_size = 8, 766 }, 767 }; 768 769 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size) 770 { 771 /* No read are expected */ 772 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr); 773 return -1; 774 } 775 776 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, 777 uint64_t val, unsigned size) 778 { 779 PnvPsi *psi = PNV_PSI(opaque); 780 781 /* XSCOM is only used to set the PSIHB MMIO region */ 782 switch (addr >> 3) { 783 case PSIHB_XSCOM_BAR: 784 pnv_psi_set_bar(psi, val); 785 break; 786 default: 787 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n", 788 addr); 789 } 790 } 791 792 static const MemoryRegionOps pnv_psi_p9_xscom_ops = { 793 .read = pnv_psi_p9_xscom_read, 794 .write = pnv_psi_p9_xscom_write, 795 .endianness = DEVICE_BIG_ENDIAN, 796 .valid = { 797 .min_access_size = 8, 798 .max_access_size = 8, 799 }, 800 .impl = { 801 .min_access_size = 8, 802 .max_access_size = 8, 803 } 804 }; 805 806 static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) 807 { 808 PnvPsi *psi = opaque; 809 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; 810 811 if (irq_method & PSIHB9_IRQ_METHOD) { 812 qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); 813 return; 814 } 815 816 /* Update LSI levels */ 817 if (state) { 818 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); 819 } else { 820 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); 821 } 822 823 qemu_set_irq(psi->qirqs[irq], state); 824 } 825 826 static void pnv_psi_power9_reset(DeviceState *dev) 827 { 828 Pnv9Psi *psi = PNV9_PSI(dev); 829 830 pnv_psi_reset(dev); 831 832 if (memory_region_is_mapped(&psi->source.esb_mmio)) { 833 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio); 834 } 835 } 836 837 static void pnv_psi_power9_instance_init(Object *obj) 838 { 839 Pnv9Psi *psi = PNV9_PSI(obj); 840 841 object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE); 842 object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift"); 843 } 844 845 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) 846 { 847 PnvPsi *psi = PNV_PSI(dev); 848 XiveSource *xsrc = &PNV9_PSI(psi)->source; 849 int i; 850 851 object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS, 852 &error_fatal); 853 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); 854 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 855 return; 856 } 857 858 for (i = 0; i < xsrc->nr_irqs; i++) { 859 xive_source_irq_set_lsi(xsrc, i); 860 } 861 862 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); 863 864 qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs); 865 866 /* XSCOM region for PSI registers */ 867 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops, 868 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); 869 870 /* MMIO region for PSI registers */ 871 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, 872 "psihb", PNV9_PSIHB_SIZE); 873 874 pnv_psi_realize(dev, errp); 875 } 876 877 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) 878 { 879 DeviceClass *dc = DEVICE_CLASS(klass); 880 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 881 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); 882 static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x"; 883 884 dc->desc = "PowerNV PSI Controller POWER9"; 885 dc->realize = pnv_psi_power9_realize; 886 dc->reset = pnv_psi_power9_reset; 887 888 ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; 889 ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; 890 ppc->bar_mask = PSIHB9_BAR_MASK; 891 ppc->compat = compat; 892 ppc->compat_size = sizeof(compat); 893 894 xfc->notify = pnv_psi_notify; 895 } 896 897 static const TypeInfo pnv_psi_power9_info = { 898 .name = TYPE_PNV9_PSI, 899 .parent = TYPE_PNV_PSI, 900 .instance_size = sizeof(Pnv9Psi), 901 .instance_init = pnv_psi_power9_instance_init, 902 .class_init = pnv_psi_power9_class_init, 903 .interfaces = (InterfaceInfo[]) { 904 { TYPE_XIVE_NOTIFIER }, 905 { }, 906 }, 907 }; 908 909 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) 910 { 911 DeviceClass *dc = DEVICE_CLASS(klass); 912 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 913 static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x"; 914 915 dc->desc = "PowerNV PSI Controller POWER10"; 916 917 ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; 918 ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; 919 ppc->compat = compat; 920 ppc->compat_size = sizeof(compat); 921 } 922 923 static const TypeInfo pnv_psi_power10_info = { 924 .name = TYPE_PNV10_PSI, 925 .parent = TYPE_PNV9_PSI, 926 .class_init = pnv_psi_power10_class_init, 927 }; 928 929 static void pnv_psi_class_init(ObjectClass *klass, void *data) 930 { 931 DeviceClass *dc = DEVICE_CLASS(klass); 932 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 933 934 xdc->dt_xscom = pnv_psi_dt_xscom; 935 936 dc->desc = "PowerNV PSI Controller"; 937 device_class_set_props(dc, pnv_psi_properties); 938 dc->reset = pnv_psi_reset; 939 dc->user_creatable = false; 940 } 941 942 static const TypeInfo pnv_psi_info = { 943 .name = TYPE_PNV_PSI, 944 .parent = TYPE_DEVICE, 945 .instance_size = sizeof(PnvPsi), 946 .class_init = pnv_psi_class_init, 947 .class_size = sizeof(PnvPsiClass), 948 .abstract = true, 949 .interfaces = (InterfaceInfo[]) { 950 { TYPE_PNV_XSCOM_INTERFACE }, 951 { } 952 } 953 }; 954 955 static void pnv_psi_register_types(void) 956 { 957 type_register_static(&pnv_psi_info); 958 type_register_static(&pnv_psi_power8_info); 959 type_register_static(&pnv_psi_power9_info); 960 type_register_static(&pnv_psi_power10_info); 961 } 962 963 type_init(pnv_psi_register_types); 964 965 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon) 966 { 967 PnvPsi *psi = PNV_PSI(psi9); 968 969 uint32_t offset = 970 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 971 972 monitor_printf(mon, "PSIHB Source %08x .. %08x\n", 973 offset, offset + psi9->source.nr_irqs - 1); 974 xive_source_pic_print_info(&psi9->source, offset, mon); 975 }