uninorth.c (18246B)
1 /* 2 * QEMU Uninorth PCI host (for all Mac99 and newer machines) 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/qdev-properties.h" 28 #include "qemu/module.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/pci-host/uninorth.h" 32 #include "trace.h" 33 34 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) 35 { 36 return (irq_num + (pci_dev->devfn >> 3)) & 3; 37 } 38 39 static void pci_unin_set_irq(void *opaque, int irq_num, int level) 40 { 41 UNINHostState *s = opaque; 42 43 trace_unin_set_irq(irq_num, level); 44 qemu_set_irq(s->irqs[irq_num], level); 45 } 46 47 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) 48 { 49 uint32_t retval; 50 51 if (reg & (1u << 31)) { 52 /* XXX OpenBIOS compatibility hack */ 53 retval = reg | (addr & 3); 54 } else if (reg & 1) { 55 /* CFA1 style */ 56 retval = (reg & ~7u) | (addr & 7); 57 } else { 58 uint32_t slot, func; 59 60 /* Grab CFA0 style values */ 61 slot = ctz32(reg & 0xfffff800); 62 if (slot == 32) { 63 slot = -1; /* XXX: should this be 0? */ 64 } 65 func = PCI_FUNC(reg >> 8); 66 67 /* ... and then convert them to x86 format */ 68 /* config pointer */ 69 retval = (reg & (0xff - 7)) | (addr & 7); 70 /* slot, fn */ 71 retval |= PCI_DEVFN(slot, func) << 8; 72 } 73 74 trace_unin_get_config_reg(reg, addr, retval); 75 76 return retval; 77 } 78 79 static void unin_data_write(void *opaque, hwaddr addr, 80 uint64_t val, unsigned len) 81 { 82 UNINHostState *s = opaque; 83 PCIHostState *phb = PCI_HOST_BRIDGE(s); 84 trace_unin_data_write(addr, len, val); 85 pci_data_write(phb->bus, 86 unin_get_config_reg(phb->config_reg, addr), 87 val, len); 88 } 89 90 static uint64_t unin_data_read(void *opaque, hwaddr addr, 91 unsigned len) 92 { 93 UNINHostState *s = opaque; 94 PCIHostState *phb = PCI_HOST_BRIDGE(s); 95 uint32_t val; 96 97 val = pci_data_read(phb->bus, 98 unin_get_config_reg(phb->config_reg, addr), 99 len); 100 trace_unin_data_read(addr, len, val); 101 return val; 102 } 103 104 static const MemoryRegionOps unin_data_ops = { 105 .read = unin_data_read, 106 .write = unin_data_write, 107 .endianness = DEVICE_LITTLE_ENDIAN, 108 }; 109 110 static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev) 111 { 112 UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); 113 114 return g_strdup_printf("%x", s->ofw_addr); 115 } 116 117 static void pci_unin_main_realize(DeviceState *dev, Error **errp) 118 { 119 UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); 120 PCIHostState *h = PCI_HOST_BRIDGE(dev); 121 122 h->bus = pci_register_root_bus(dev, NULL, 123 pci_unin_set_irq, pci_unin_map_irq, 124 s, 125 &s->pci_mmio, 126 &s->pci_io, 127 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); 128 129 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); 130 131 /* DEC 21154 bridge */ 132 #if 0 133 /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */ 134 pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154"); 135 #endif 136 } 137 138 static void pci_unin_main_init(Object *obj) 139 { 140 UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); 141 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 142 PCIHostState *h = PCI_HOST_BRIDGE(obj); 143 144 /* Use values found on a real PowerMac */ 145 /* Uninorth main bus */ 146 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 147 obj, "unin-pci-conf-idx", 0x1000); 148 memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, 149 "unin-pci-conf-data", 0x1000); 150 151 memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", 152 0x100000000ULL); 153 memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, 154 "unin-pci-isa-mmio", 0x00800000); 155 156 memory_region_init_alias(&s->pci_hole, OBJECT(s), 157 "unin-pci-hole", &s->pci_mmio, 158 0x80000000ULL, 0x10000000ULL); 159 160 sysbus_init_mmio(sbd, &h->conf_mem); 161 sysbus_init_mmio(sbd, &h->data_mem); 162 sysbus_init_mmio(sbd, &s->pci_hole); 163 sysbus_init_mmio(sbd, &s->pci_io); 164 165 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 166 } 167 168 static void pci_u3_agp_realize(DeviceState *dev, Error **errp) 169 { 170 UNINHostState *s = U3_AGP_HOST_BRIDGE(dev); 171 PCIHostState *h = PCI_HOST_BRIDGE(dev); 172 173 h->bus = pci_register_root_bus(dev, NULL, 174 pci_unin_set_irq, pci_unin_map_irq, 175 s, 176 &s->pci_mmio, 177 &s->pci_io, 178 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); 179 180 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); 181 } 182 183 static void pci_u3_agp_init(Object *obj) 184 { 185 UNINHostState *s = U3_AGP_HOST_BRIDGE(obj); 186 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 187 PCIHostState *h = PCI_HOST_BRIDGE(obj); 188 189 /* Uninorth U3 AGP bus */ 190 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 191 obj, "unin-pci-conf-idx", 0x1000); 192 memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, 193 "unin-pci-conf-data", 0x1000); 194 195 memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", 196 0x100000000ULL); 197 memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, 198 "unin-pci-isa-mmio", 0x00800000); 199 200 memory_region_init_alias(&s->pci_hole, OBJECT(s), 201 "unin-pci-hole", &s->pci_mmio, 202 0x80000000ULL, 0x70000000ULL); 203 204 sysbus_init_mmio(sbd, &h->conf_mem); 205 sysbus_init_mmio(sbd, &h->data_mem); 206 sysbus_init_mmio(sbd, &s->pci_hole); 207 sysbus_init_mmio(sbd, &s->pci_io); 208 209 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 210 } 211 212 static void pci_unin_agp_realize(DeviceState *dev, Error **errp) 213 { 214 UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); 215 PCIHostState *h = PCI_HOST_BRIDGE(dev); 216 217 h->bus = pci_register_root_bus(dev, NULL, 218 pci_unin_set_irq, pci_unin_map_irq, 219 s, 220 &s->pci_mmio, 221 &s->pci_io, 222 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); 223 224 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); 225 } 226 227 static void pci_unin_agp_init(Object *obj) 228 { 229 UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); 230 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 231 PCIHostState *h = PCI_HOST_BRIDGE(obj); 232 233 /* Uninorth AGP bus */ 234 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 235 obj, "unin-agp-conf-idx", 0x1000); 236 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, 237 obj, "unin-agp-conf-data", 0x1000); 238 239 sysbus_init_mmio(sbd, &h->conf_mem); 240 sysbus_init_mmio(sbd, &h->data_mem); 241 242 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 243 } 244 245 static void pci_unin_internal_realize(DeviceState *dev, Error **errp) 246 { 247 UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev); 248 PCIHostState *h = PCI_HOST_BRIDGE(dev); 249 250 h->bus = pci_register_root_bus(dev, NULL, 251 pci_unin_set_irq, pci_unin_map_irq, 252 s, 253 &s->pci_mmio, 254 &s->pci_io, 255 PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); 256 257 pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); 258 } 259 260 static void pci_unin_internal_init(Object *obj) 261 { 262 UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); 263 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 264 PCIHostState *h = PCI_HOST_BRIDGE(obj); 265 266 /* Uninorth internal bus */ 267 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 268 obj, "unin-pci-conf-idx", 0x1000); 269 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, 270 obj, "unin-pci-conf-data", 0x1000); 271 272 sysbus_init_mmio(sbd, &h->conf_mem); 273 sysbus_init_mmio(sbd, &h->data_mem); 274 275 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 276 } 277 278 static void unin_main_pci_host_realize(PCIDevice *d, Error **errp) 279 { 280 /* cache_line_size */ 281 d->config[0x0C] = 0x08; 282 /* latency_timer */ 283 d->config[0x0D] = 0x10; 284 /* capabilities_pointer */ 285 d->config[0x34] = 0x00; 286 287 /* 288 * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI 289 * memory space with base 0x80000000, size 0x10000000 for Apple's 290 * AppleMacRiscPCI driver 291 */ 292 d->config[0x48] = 0x0; 293 d->config[0x49] = 0x0; 294 d->config[0x4a] = 0x0; 295 d->config[0x4b] = 0x1; 296 } 297 298 static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp) 299 { 300 /* cache_line_size */ 301 d->config[0x0C] = 0x08; 302 /* latency_timer */ 303 d->config[0x0D] = 0x10; 304 /* capabilities_pointer 305 d->config[0x34] = 0x80; */ 306 } 307 308 static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp) 309 { 310 /* cache line size */ 311 d->config[0x0C] = 0x08; 312 /* latency timer */ 313 d->config[0x0D] = 0x10; 314 } 315 316 static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp) 317 { 318 /* cache_line_size */ 319 d->config[0x0C] = 0x08; 320 /* latency_timer */ 321 d->config[0x0D] = 0x10; 322 /* capabilities_pointer */ 323 d->config[0x34] = 0x00; 324 } 325 326 static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) 327 { 328 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 329 DeviceClass *dc = DEVICE_CLASS(klass); 330 331 k->realize = unin_main_pci_host_realize; 332 k->vendor_id = PCI_VENDOR_ID_APPLE; 333 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI; 334 k->revision = 0x00; 335 k->class_id = PCI_CLASS_BRIDGE_HOST; 336 /* 337 * PCI-facing part of the host bridge, not usable without the 338 * host-facing part, which can't be device_add'ed, yet. 339 */ 340 dc->user_creatable = false; 341 } 342 343 static const TypeInfo unin_main_pci_host_info = { 344 .name = "uni-north-pci", 345 .parent = TYPE_PCI_DEVICE, 346 .instance_size = sizeof(PCIDevice), 347 .class_init = unin_main_pci_host_class_init, 348 .interfaces = (InterfaceInfo[]) { 349 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 350 { }, 351 }, 352 }; 353 354 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) 355 { 356 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 357 DeviceClass *dc = DEVICE_CLASS(klass); 358 359 k->realize = u3_agp_pci_host_realize; 360 k->vendor_id = PCI_VENDOR_ID_APPLE; 361 k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP; 362 k->revision = 0x00; 363 k->class_id = PCI_CLASS_BRIDGE_HOST; 364 /* 365 * PCI-facing part of the host bridge, not usable without the 366 * host-facing part, which can't be device_add'ed, yet. 367 */ 368 dc->user_creatable = false; 369 } 370 371 static const TypeInfo u3_agp_pci_host_info = { 372 .name = "u3-agp", 373 .parent = TYPE_PCI_DEVICE, 374 .instance_size = sizeof(PCIDevice), 375 .class_init = u3_agp_pci_host_class_init, 376 .interfaces = (InterfaceInfo[]) { 377 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 378 { }, 379 }, 380 }; 381 382 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) 383 { 384 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 385 DeviceClass *dc = DEVICE_CLASS(klass); 386 387 k->realize = unin_agp_pci_host_realize; 388 k->vendor_id = PCI_VENDOR_ID_APPLE; 389 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP; 390 k->revision = 0x00; 391 k->class_id = PCI_CLASS_BRIDGE_HOST; 392 /* 393 * PCI-facing part of the host bridge, not usable without the 394 * host-facing part, which can't be device_add'ed, yet. 395 */ 396 dc->user_creatable = false; 397 } 398 399 static const TypeInfo unin_agp_pci_host_info = { 400 .name = "uni-north-agp", 401 .parent = TYPE_PCI_DEVICE, 402 .instance_size = sizeof(PCIDevice), 403 .class_init = unin_agp_pci_host_class_init, 404 .interfaces = (InterfaceInfo[]) { 405 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 406 { }, 407 }, 408 }; 409 410 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) 411 { 412 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 413 DeviceClass *dc = DEVICE_CLASS(klass); 414 415 k->realize = unin_internal_pci_host_realize; 416 k->vendor_id = PCI_VENDOR_ID_APPLE; 417 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI; 418 k->revision = 0x00; 419 k->class_id = PCI_CLASS_BRIDGE_HOST; 420 /* 421 * PCI-facing part of the host bridge, not usable without the 422 * host-facing part, which can't be device_add'ed, yet. 423 */ 424 dc->user_creatable = false; 425 } 426 427 static const TypeInfo unin_internal_pci_host_info = { 428 .name = "uni-north-internal-pci", 429 .parent = TYPE_PCI_DEVICE, 430 .instance_size = sizeof(PCIDevice), 431 .class_init = unin_internal_pci_host_class_init, 432 .interfaces = (InterfaceInfo[]) { 433 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 434 { }, 435 }, 436 }; 437 438 static Property pci_unin_main_pci_host_props[] = { 439 DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1), 440 DEFINE_PROP_END_OF_LIST() 441 }; 442 443 static void pci_unin_main_class_init(ObjectClass *klass, void *data) 444 { 445 DeviceClass *dc = DEVICE_CLASS(klass); 446 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 447 448 dc->realize = pci_unin_main_realize; 449 device_class_set_props(dc, pci_unin_main_pci_host_props); 450 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 451 dc->fw_name = "pci"; 452 sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address; 453 } 454 455 static const TypeInfo pci_unin_main_info = { 456 .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE, 457 .parent = TYPE_PCI_HOST_BRIDGE, 458 .instance_size = sizeof(UNINHostState), 459 .instance_init = pci_unin_main_init, 460 .class_init = pci_unin_main_class_init, 461 }; 462 463 static void pci_u3_agp_class_init(ObjectClass *klass, void *data) 464 { 465 DeviceClass *dc = DEVICE_CLASS(klass); 466 467 dc->realize = pci_u3_agp_realize; 468 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 469 } 470 471 static const TypeInfo pci_u3_agp_info = { 472 .name = TYPE_U3_AGP_HOST_BRIDGE, 473 .parent = TYPE_PCI_HOST_BRIDGE, 474 .instance_size = sizeof(UNINHostState), 475 .instance_init = pci_u3_agp_init, 476 .class_init = pci_u3_agp_class_init, 477 }; 478 479 static void pci_unin_agp_class_init(ObjectClass *klass, void *data) 480 { 481 DeviceClass *dc = DEVICE_CLASS(klass); 482 483 dc->realize = pci_unin_agp_realize; 484 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 485 } 486 487 static const TypeInfo pci_unin_agp_info = { 488 .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE, 489 .parent = TYPE_PCI_HOST_BRIDGE, 490 .instance_size = sizeof(UNINHostState), 491 .instance_init = pci_unin_agp_init, 492 .class_init = pci_unin_agp_class_init, 493 }; 494 495 static void pci_unin_internal_class_init(ObjectClass *klass, void *data) 496 { 497 DeviceClass *dc = DEVICE_CLASS(klass); 498 499 dc->realize = pci_unin_internal_realize; 500 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 501 } 502 503 static const TypeInfo pci_unin_internal_info = { 504 .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE, 505 .parent = TYPE_PCI_HOST_BRIDGE, 506 .instance_size = sizeof(UNINHostState), 507 .instance_init = pci_unin_internal_init, 508 .class_init = pci_unin_internal_class_init, 509 }; 510 511 /* UniN device */ 512 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 513 unsigned size) 514 { 515 trace_unin_write(addr, value); 516 } 517 518 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 519 { 520 uint32_t value; 521 522 switch (addr) { 523 case 0: 524 value = UNINORTH_VERSION_10A; 525 break; 526 default: 527 value = 0; 528 } 529 530 trace_unin_read(addr, value); 531 532 return value; 533 } 534 535 static const MemoryRegionOps unin_ops = { 536 .read = unin_read, 537 .write = unin_write, 538 .endianness = DEVICE_BIG_ENDIAN, 539 }; 540 541 static void unin_init(Object *obj) 542 { 543 UNINState *s = UNI_NORTH(obj); 544 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 545 546 memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000); 547 548 sysbus_init_mmio(sbd, &s->mem); 549 } 550 551 static void unin_class_init(ObjectClass *klass, void *data) 552 { 553 DeviceClass *dc = DEVICE_CLASS(klass); 554 555 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 556 } 557 558 static const TypeInfo unin_info = { 559 .name = TYPE_UNI_NORTH, 560 .parent = TYPE_SYS_BUS_DEVICE, 561 .instance_size = sizeof(UNINState), 562 .instance_init = unin_init, 563 .class_init = unin_class_init, 564 }; 565 566 static void unin_register_types(void) 567 { 568 type_register_static(&unin_main_pci_host_info); 569 type_register_static(&u3_agp_pci_host_info); 570 type_register_static(&unin_agp_pci_host_info); 571 type_register_static(&unin_internal_pci_host_info); 572 573 type_register_static(&pci_unin_main_info); 574 type_register_static(&pci_u3_agp_info); 575 type_register_static(&pci_unin_agp_info); 576 type_register_static(&pci_unin_internal_info); 577 578 type_register_static(&unin_info); 579 } 580 581 type_init(unin_register_types)