pnv_phb.c (10527B)
1 /* 2 * QEMU PowerPC PowerNV Proxy PHB model 3 * 4 * Copyright (c) 2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/visitor.h" 13 #include "qapi/error.h" 14 #include "hw/pci-host/pnv_phb.h" 15 #include "hw/pci-host/pnv_phb3.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv.h" 18 #include "hw/qdev-properties.h" 19 #include "qom/object.h" 20 #include "sysemu/sysemu.h" 21 22 23 /* 24 * Set the QOM parent and parent bus of an object child. If the device 25 * state associated with the child has an id, use it as QOM id. 26 * Otherwise use object_typename[index] as QOM id. 27 * 28 * This helper does both operations at the same time because seting 29 * a new QOM child will erase the bus parent of the device. This happens 30 * because object_unparent() will call object_property_del_child(), 31 * which in turn calls the property release callback prop->release if 32 * it's defined. In our case this callback is set to 33 * object_finalize_child_property(), which was assigned during the 34 * first object_property_add_child() call. This callback will end up 35 * calling device_unparent(), and this function removes the device 36 * from its parent bus. 37 * 38 * The QOM and parent bus to be set aren´t necessarily related, so 39 * let's receive both as arguments. 40 */ 41 static bool pnv_parent_fixup(Object *parent, BusState *parent_bus, 42 Object *child, int index, 43 Error **errp) 44 { 45 g_autofree char *default_id = 46 g_strdup_printf("%s[%d]", object_get_typename(child), index); 47 const char *dev_id = DEVICE(child)->id; 48 49 if (child->parent == parent) { 50 return true; 51 } 52 53 object_ref(child); 54 object_unparent(child); 55 object_property_add_child(parent, dev_id ? dev_id : default_id, child); 56 object_unref(child); 57 58 if (!qdev_set_parent_bus(DEVICE(child), parent_bus, errp)) { 59 return false; 60 } 61 62 return true; 63 } 64 65 /* 66 * User created devices won't have the initial setup that default 67 * devices have. This setup consists of assigning a parent device 68 * (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent 69 * of the PHB. 70 */ 71 static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp) 72 { 73 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 74 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); 75 Object *parent = NULL; 76 77 if (!chip) { 78 error_setg(errp, "invalid chip id: %d", phb->chip_id); 79 return false; 80 } 81 82 parent = pnv_chip_add_phb(chip, phb, errp); 83 if (!parent) { 84 return false; 85 } 86 87 /* 88 * Reparent user created devices to the chip to build 89 * correctly the device tree. pnv_xscom_dt() needs every 90 * PHB to be a child of the chip to build the DT correctly. 91 */ 92 if (!pnv_parent_fixup(parent, qdev_get_parent_bus(DEVICE(chip)), 93 OBJECT(phb), phb->phb_id, errp)) { 94 return false; 95 } 96 97 return true; 98 } 99 100 static void pnv_phb_realize(DeviceState *dev, Error **errp) 101 { 102 PnvPHB *phb = PNV_PHB(dev); 103 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 104 g_autofree char *phb_typename = NULL; 105 106 if (!phb->version) { 107 error_setg(errp, "version not specified"); 108 return; 109 } 110 111 switch (phb->version) { 112 case 3: 113 phb_typename = g_strdup(TYPE_PNV_PHB3); 114 break; 115 case 4: 116 phb_typename = g_strdup(TYPE_PNV_PHB4); 117 break; 118 case 5: 119 phb_typename = g_strdup(TYPE_PNV_PHB5); 120 break; 121 default: 122 g_assert_not_reached(); 123 } 124 125 phb->backend = object_new(phb_typename); 126 object_property_add_child(OBJECT(dev), "phb-backend", phb->backend); 127 128 /* Passthrough child device properties to the proxy device */ 129 object_property_set_uint(phb->backend, "index", phb->phb_id, errp); 130 object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp); 131 object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp); 132 133 /* 134 * Handle user created devices. User devices will not have a 135 * pointer to a chip (PHB3) and a PEC (PHB4/5). 136 */ 137 if (!phb->chip && !phb->pec) { 138 if (!pnv_phb_user_device_init(phb, errp)) { 139 return; 140 } 141 } 142 143 if (phb->version == 3) { 144 object_property_set_link(phb->backend, "chip", 145 OBJECT(phb->chip), errp); 146 } else { 147 object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp); 148 } 149 150 if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) { 151 return; 152 } 153 154 if (phb->version == 3) { 155 pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend)); 156 } else { 157 pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); 158 } 159 160 if (defaults_enabled()) { 161 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); 162 163 pci_realize_and_unref(root, pci->bus, errp); 164 } 165 } 166 167 static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, 168 PCIBus *rootbus) 169 { 170 PnvPHB *phb = PNV_PHB(host_bridge); 171 172 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", 173 phb->chip_id, phb->phb_id); 174 return phb->bus_path; 175 } 176 177 static Property pnv_phb_properties[] = { 178 DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), 179 DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), 180 DEFINE_PROP_UINT32("version", PnvPHB, version, 0), 181 182 DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), 183 184 DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, 185 PnvPhb4PecState *), 186 187 DEFINE_PROP_END_OF_LIST(), 188 }; 189 190 static void pnv_phb_class_init(ObjectClass *klass, void *data) 191 { 192 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 193 DeviceClass *dc = DEVICE_CLASS(klass); 194 195 hc->root_bus_path = pnv_phb_root_bus_path; 196 dc->realize = pnv_phb_realize; 197 device_class_set_props(dc, pnv_phb_properties); 198 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 199 dc->user_creatable = true; 200 } 201 202 static void pnv_phb_root_port_reset(DeviceState *dev) 203 { 204 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 205 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 206 PCIDevice *d = PCI_DEVICE(dev); 207 uint8_t *conf = d->config; 208 209 rpc->parent_reset(dev); 210 211 if (phb_rp->version == 3) { 212 return; 213 } 214 215 /* PHB4 and later requires these extra reset steps */ 216 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 217 PCI_IO_RANGE_MASK & 0xff); 218 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 219 PCI_IO_RANGE_MASK & 0xff); 220 pci_set_word(conf + PCI_MEMORY_BASE, 0); 221 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); 222 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); 223 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); 224 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ 225 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); 226 pci_config_set_interrupt_pin(conf, 0); 227 } 228 229 static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) 230 { 231 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 232 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 233 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev)); 234 PCIDevice *pci = PCI_DEVICE(dev); 235 uint16_t device_id = 0; 236 Error *local_err = NULL; 237 int chip_id, index; 238 239 /* 240 * 'index' will be used both as a PCIE slot value and to calculate 241 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 242 * root port. 243 */ 244 chip_id = object_property_get_int(OBJECT(bus), "chip-id", &local_err); 245 if (local_err) { 246 error_propagate(errp, local_err); 247 return; 248 } 249 index = object_property_get_int(OBJECT(bus), "phb-id", &local_err); 250 if (local_err) { 251 error_propagate(errp, local_err); 252 return; 253 } 254 255 /* Set unique chassis/slot values for the root port */ 256 qdev_prop_set_uint8(dev, "chassis", chip_id); 257 qdev_prop_set_uint16(dev, "slot", index); 258 259 /* 260 * User created root ports are QOM parented to one of 261 * the peripheral containers but it's already at the right 262 * parent bus. Change the QOM parent to be the same as the 263 * parent bus it's already assigned to. 264 */ 265 if (!pnv_parent_fixup(OBJECT(bus), BUS(bus), OBJECT(dev), 266 index, errp)) { 267 return; 268 } 269 270 rpc->parent_realize(dev, &local_err); 271 if (local_err) { 272 error_propagate(errp, local_err); 273 return; 274 } 275 276 switch (phb_rp->version) { 277 case 3: 278 device_id = PNV_PHB3_DEVICE_ID; 279 break; 280 case 4: 281 device_id = PNV_PHB4_DEVICE_ID; 282 break; 283 case 5: 284 device_id = PNV_PHB5_DEVICE_ID; 285 break; 286 default: 287 g_assert_not_reached(); 288 } 289 290 pci_config_set_device_id(pci->config, device_id); 291 pci_config_set_interrupt_pin(pci->config, 0); 292 } 293 294 static Property pnv_phb_root_port_properties[] = { 295 DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0), 296 297 DEFINE_PROP_END_OF_LIST(), 298 }; 299 300 static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) 301 { 302 DeviceClass *dc = DEVICE_CLASS(klass); 303 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 304 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); 305 306 dc->desc = "IBM PHB PCIE Root Port"; 307 308 device_class_set_props(dc, pnv_phb_root_port_properties); 309 device_class_set_parent_realize(dc, pnv_phb_root_port_realize, 310 &rpc->parent_realize); 311 device_class_set_parent_reset(dc, pnv_phb_root_port_reset, 312 &rpc->parent_reset); 313 dc->reset = &pnv_phb_root_port_reset; 314 dc->user_creatable = true; 315 316 k->vendor_id = PCI_VENDOR_ID_IBM; 317 /* device_id will be written during realize() */ 318 k->device_id = 0; 319 k->revision = 0; 320 321 rpc->exp_offset = 0x48; 322 rpc->aer_offset = 0x100; 323 } 324 325 static const TypeInfo pnv_phb_type_info = { 326 .name = TYPE_PNV_PHB, 327 .parent = TYPE_PCIE_HOST_BRIDGE, 328 .instance_size = sizeof(PnvPHB), 329 .class_init = pnv_phb_class_init, 330 }; 331 332 static const TypeInfo pnv_phb_root_port_info = { 333 .name = TYPE_PNV_PHB_ROOT_PORT, 334 .parent = TYPE_PCIE_ROOT_PORT, 335 .instance_size = sizeof(PnvPHBRootPort), 336 .class_init = pnv_phb_root_port_class_init, 337 }; 338 339 static void pnv_phb_register_types(void) 340 { 341 type_register_static(&pnv_phb_type_info); 342 type_register_static(&pnv_phb_root_port_info); 343 } 344 345 type_init(pnv_phb_register_types)