rtl8139.c (99686B)
1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 53 #include "qemu/osdep.h" 54 #include <zlib.h> 55 56 #include "hw/pci/pci.h" 57 #include "hw/qdev-properties.h" 58 #include "migration/vmstate.h" 59 #include "sysemu/dma.h" 60 #include "qemu/module.h" 61 #include "qemu/timer.h" 62 #include "net/net.h" 63 #include "net/eth.h" 64 #include "sysemu/sysemu.h" 65 #include "qom/object.h" 66 67 /* debug RTL8139 card */ 68 //#define DEBUG_RTL8139 1 69 70 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ 71 72 #define SET_MASKED(input, mask, curr) \ 73 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 74 75 /* arg % size for size which is a power of 2 */ 76 #define MOD2(input, size) \ 77 ( ( input ) & ( size - 1 ) ) 78 79 #define ETHER_TYPE_LEN 2 80 81 #define VLAN_TCI_LEN 2 82 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 83 84 #if defined (DEBUG_RTL8139) 85 # define DPRINTF(fmt, ...) \ 86 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 87 #else 88 static inline G_GNUC_PRINTF(1, 2) int DPRINTF(const char *fmt, ...) 89 { 90 return 0; 91 } 92 #endif 93 94 #define TYPE_RTL8139 "rtl8139" 95 96 OBJECT_DECLARE_SIMPLE_TYPE(RTL8139State, RTL8139) 97 98 /* Symbolic offsets to registers. */ 99 enum RTL8139_registers { 100 MAC0 = 0, /* Ethernet hardware address. */ 101 MAR0 = 8, /* Multicast filter. */ 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 103 /* Dump Tally Conter control register(64bit). C+ mode only */ 104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 105 RxBuf = 0x30, 106 ChipCmd = 0x37, 107 RxBufPtr = 0x38, 108 RxBufAddr = 0x3A, 109 IntrMask = 0x3C, 110 IntrStatus = 0x3E, 111 TxConfig = 0x40, 112 RxConfig = 0x44, 113 Timer = 0x48, /* A general-purpose counter. */ 114 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 115 Cfg9346 = 0x50, 116 Config0 = 0x51, 117 Config1 = 0x52, 118 FlashReg = 0x54, 119 MediaStatus = 0x58, 120 Config3 = 0x59, 121 Config4 = 0x5A, /* absent on RTL-8139A */ 122 HltClk = 0x5B, 123 MultiIntr = 0x5C, 124 PCIRevisionID = 0x5E, 125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 126 BasicModeCtrl = 0x62, 127 BasicModeStatus = 0x64, 128 NWayAdvert = 0x66, 129 NWayLPAR = 0x68, 130 NWayExpansion = 0x6A, 131 /* Undocumented registers, but required for proper operation. */ 132 FIFOTMS = 0x70, /* FIFO Control and test. */ 133 CSCR = 0x74, /* Chip Status and Configuration Register. */ 134 PARA78 = 0x78, 135 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 136 Config5 = 0xD8, /* absent on RTL-8139A */ 137 /* C+ mode */ 138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 144 TxThresh = 0xEC, /* Early Tx threshold */ 145 }; 146 147 enum ClearBitMasks { 148 MultiIntrClear = 0xF000, 149 ChipCmdClear = 0xE2, 150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 151 }; 152 153 enum ChipCmdBits { 154 CmdReset = 0x10, 155 CmdRxEnb = 0x08, 156 CmdTxEnb = 0x04, 157 RxBufEmpty = 0x01, 158 }; 159 160 /* C+ mode */ 161 enum CplusCmdBits { 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 164 CPlusRxEnb = 0x0002, 165 CPlusTxEnb = 0x0001, 166 }; 167 168 /* Interrupt register bits, using my own meaningful names. */ 169 enum IntrStatusBits { 170 PCIErr = 0x8000, 171 PCSTimeout = 0x4000, 172 RxFIFOOver = 0x40, 173 RxUnderrun = 0x20, /* Packet Underrun / Link Change */ 174 RxOverflow = 0x10, 175 TxErr = 0x08, 176 TxOK = 0x04, 177 RxErr = 0x02, 178 RxOK = 0x01, 179 180 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 181 }; 182 183 enum TxStatusBits { 184 TxHostOwns = 0x2000, 185 TxUnderrun = 0x4000, 186 TxStatOK = 0x8000, 187 TxOutOfWindow = 0x20000000, 188 TxAborted = 0x40000000, 189 TxCarrierLost = 0x80000000, 190 }; 191 enum RxStatusBits { 192 RxMulticast = 0x8000, 193 RxPhysical = 0x4000, 194 RxBroadcast = 0x2000, 195 RxBadSymbol = 0x0020, 196 RxRunt = 0x0010, 197 RxTooLong = 0x0008, 198 RxCRCErr = 0x0004, 199 RxBadAlign = 0x0002, 200 RxStatusOK = 0x0001, 201 }; 202 203 /* Bits in RxConfig. */ 204 enum rx_mode_bits { 205 AcceptErr = 0x20, 206 AcceptRunt = 0x10, 207 AcceptBroadcast = 0x08, 208 AcceptMulticast = 0x04, 209 AcceptMyPhys = 0x02, 210 AcceptAllPhys = 0x01, 211 }; 212 213 /* Bits in TxConfig. */ 214 enum tx_config_bits { 215 216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 217 TxIFGShift = 24, 218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 222 223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 225 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 228 229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 230 }; 231 232 233 /* Transmit Status of All Descriptors (TSAD) Register */ 234 enum TSAD_bits { 235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 251 }; 252 253 254 /* Bits in Config1 */ 255 enum Config1Bits { 256 Cfg1_PM_Enable = 0x01, 257 Cfg1_VPD_Enable = 0x02, 258 Cfg1_PIO = 0x04, 259 Cfg1_MMIO = 0x08, 260 LWAKE = 0x10, /* not on 8139, 8139A */ 261 Cfg1_Driver_Load = 0x20, 262 Cfg1_LED0 = 0x40, 263 Cfg1_LED1 = 0x80, 264 SLEEP = (1 << 1), /* only on 8139, 8139A */ 265 PWRDN = (1 << 0), /* only on 8139, 8139A */ 266 }; 267 268 /* Bits in Config3 */ 269 enum Config3Bits { 270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 278 }; 279 280 /* Bits in Config4 */ 281 enum Config4Bits { 282 LWPTN = (1 << 2), /* not on 8139, 8139A */ 283 }; 284 285 /* Bits in Config5 */ 286 enum Config5Bits { 287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 294 }; 295 296 enum RxConfigBits { 297 /* rx fifo threshold */ 298 RxCfgFIFOShift = 13, 299 RxCfgFIFONone = (7 << RxCfgFIFOShift), 300 301 /* Max DMA burst */ 302 RxCfgDMAShift = 8, 303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 304 305 /* rx ring buffer length */ 306 RxCfgRcv8K = 0, 307 RxCfgRcv16K = (1 << 11), 308 RxCfgRcv32K = (1 << 12), 309 RxCfgRcv64K = (1 << 11) | (1 << 12), 310 311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 312 RxNoWrap = (1 << 7), 313 }; 314 315 /* Twister tuning parameters from RealTek. 316 Completely undocumented, but required to tune bad links on some boards. */ 317 /* 318 enum CSCRBits { 319 CSCR_LinkOKBit = 0x0400, 320 CSCR_LinkChangeBit = 0x0800, 321 CSCR_LinkStatusBits = 0x0f000, 322 CSCR_LinkDownOffCmd = 0x003c0, 323 CSCR_LinkDownCmd = 0x0f3c0, 324 */ 325 enum CSCRBits { 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 335 }; 336 337 enum Cfg9346Bits { 338 Cfg9346_Normal = 0x00, 339 Cfg9346_Autoload = 0x40, 340 Cfg9346_Programming = 0x80, 341 Cfg9346_ConfigWrite = 0xC0, 342 }; 343 344 typedef enum { 345 CH_8139 = 0, 346 CH_8139_K, 347 CH_8139A, 348 CH_8139A_G, 349 CH_8139B, 350 CH_8130, 351 CH_8139C, 352 CH_8100, 353 CH_8100B_8139D, 354 CH_8101, 355 } chip_t; 356 357 enum chip_flags { 358 HasHltClk = (1 << 0), 359 HasLWake = (1 << 1), 360 }; 361 362 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 363 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 364 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 365 366 #define RTL8139_PCI_REVID_8139 0x10 367 #define RTL8139_PCI_REVID_8139CPLUS 0x20 368 369 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 370 371 /* Size is 64 * 16bit words */ 372 #define EEPROM_9346_ADDR_BITS 6 373 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 374 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 375 376 enum Chip9346Operation 377 { 378 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 379 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 380 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 381 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 382 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 383 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 384 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 385 }; 386 387 enum Chip9346Mode 388 { 389 Chip9346_none = 0, 390 Chip9346_enter_command_mode, 391 Chip9346_read_command, 392 Chip9346_data_read, /* from output register */ 393 Chip9346_data_write, /* to input register, then to contents at specified address */ 394 Chip9346_data_write_all, /* to input register, then filling contents */ 395 }; 396 397 typedef struct EEprom9346 398 { 399 uint16_t contents[EEPROM_9346_SIZE]; 400 int mode; 401 uint32_t tick; 402 uint8_t address; 403 uint16_t input; 404 uint16_t output; 405 406 uint8_t eecs; 407 uint8_t eesk; 408 uint8_t eedi; 409 uint8_t eedo; 410 } EEprom9346; 411 412 typedef struct RTL8139TallyCounters 413 { 414 /* Tally counters */ 415 uint64_t TxOk; 416 uint64_t RxOk; 417 uint64_t TxERR; 418 uint32_t RxERR; 419 uint16_t MissPkt; 420 uint16_t FAE; 421 uint32_t Tx1Col; 422 uint32_t TxMCol; 423 uint64_t RxOkPhy; 424 uint64_t RxOkBrd; 425 uint32_t RxOkMul; 426 uint16_t TxAbt; 427 uint16_t TxUndrn; 428 } RTL8139TallyCounters; 429 430 /* Clears all tally counters */ 431 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 432 433 struct RTL8139State { 434 /*< private >*/ 435 PCIDevice parent_obj; 436 /*< public >*/ 437 438 uint8_t phys[8]; /* mac address */ 439 uint8_t mult[8]; /* multicast mask array */ 440 441 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 442 uint32_t TxAddr[4]; /* TxAddr0 */ 443 uint32_t RxBuf; /* Receive buffer */ 444 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 445 uint32_t RxBufPtr; 446 uint32_t RxBufAddr; 447 448 uint16_t IntrStatus; 449 uint16_t IntrMask; 450 451 uint32_t TxConfig; 452 uint32_t RxConfig; 453 uint32_t RxMissed; 454 455 uint16_t CSCR; 456 457 uint8_t Cfg9346; 458 uint8_t Config0; 459 uint8_t Config1; 460 uint8_t Config3; 461 uint8_t Config4; 462 uint8_t Config5; 463 464 uint8_t clock_enabled; 465 uint8_t bChipCmdState; 466 467 uint16_t MultiIntr; 468 469 uint16_t BasicModeCtrl; 470 uint16_t BasicModeStatus; 471 uint16_t NWayAdvert; 472 uint16_t NWayLPAR; 473 uint16_t NWayExpansion; 474 475 uint16_t CpCmd; 476 uint8_t TxThresh; 477 478 NICState *nic; 479 NICConf conf; 480 481 /* C ring mode */ 482 uint32_t currTxDesc; 483 484 /* C+ mode */ 485 uint32_t cplus_enabled; 486 487 uint32_t currCPlusRxDesc; 488 uint32_t currCPlusTxDesc; 489 490 uint32_t RxRingAddrLO; 491 uint32_t RxRingAddrHI; 492 493 EEprom9346 eeprom; 494 495 uint32_t TCTR; 496 uint32_t TimerInt; 497 int64_t TCTR_base; 498 499 /* Tally counters */ 500 RTL8139TallyCounters tally_counters; 501 502 /* Non-persistent data */ 503 uint8_t *cplus_txbuffer; 504 int cplus_txbuffer_len; 505 int cplus_txbuffer_offset; 506 507 /* PCI interrupt timer */ 508 QEMUTimer *timer; 509 510 MemoryRegion bar_io; 511 MemoryRegion bar_mem; 512 513 /* Support migration to/from old versions */ 514 int rtl8139_mmio_io_addr_dummy; 515 }; 516 517 /* Writes tally counters to memory via DMA */ 518 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 519 520 static void rtl8139_set_next_tctr_time(RTL8139State *s); 521 522 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 523 { 524 DPRINTF("eeprom command 0x%02x\n", command); 525 526 switch (command & Chip9346_op_mask) 527 { 528 case Chip9346_op_read: 529 { 530 eeprom->address = command & EEPROM_9346_ADDR_MASK; 531 eeprom->output = eeprom->contents[eeprom->address]; 532 eeprom->eedo = 0; 533 eeprom->tick = 0; 534 eeprom->mode = Chip9346_data_read; 535 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 536 eeprom->address, eeprom->output); 537 } 538 break; 539 540 case Chip9346_op_write: 541 { 542 eeprom->address = command & EEPROM_9346_ADDR_MASK; 543 eeprom->input = 0; 544 eeprom->tick = 0; 545 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 546 DPRINTF("eeprom begin write to address 0x%02x\n", 547 eeprom->address); 548 } 549 break; 550 default: 551 eeprom->mode = Chip9346_none; 552 switch (command & Chip9346_op_ext_mask) 553 { 554 case Chip9346_op_write_enable: 555 DPRINTF("eeprom write enabled\n"); 556 break; 557 case Chip9346_op_write_all: 558 DPRINTF("eeprom begin write all\n"); 559 break; 560 case Chip9346_op_write_disable: 561 DPRINTF("eeprom write disabled\n"); 562 break; 563 } 564 break; 565 } 566 } 567 568 static void prom9346_shift_clock(EEprom9346 *eeprom) 569 { 570 int bit = eeprom->eedi?1:0; 571 572 ++ eeprom->tick; 573 574 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 575 eeprom->eedo); 576 577 switch (eeprom->mode) 578 { 579 case Chip9346_enter_command_mode: 580 if (bit) 581 { 582 eeprom->mode = Chip9346_read_command; 583 eeprom->tick = 0; 584 eeprom->input = 0; 585 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 586 } 587 break; 588 589 case Chip9346_read_command: 590 eeprom->input = (eeprom->input << 1) | (bit & 1); 591 if (eeprom->tick == 8) 592 { 593 prom9346_decode_command(eeprom, eeprom->input & 0xff); 594 } 595 break; 596 597 case Chip9346_data_read: 598 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 599 eeprom->output <<= 1; 600 if (eeprom->tick == 16) 601 { 602 #if 1 603 // the FreeBSD drivers (rl and re) don't explicitly toggle 604 // CS between reads (or does setting Cfg9346 to 0 count too?), 605 // so we need to enter wait-for-command state here 606 eeprom->mode = Chip9346_enter_command_mode; 607 eeprom->input = 0; 608 eeprom->tick = 0; 609 610 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 611 #else 612 // original behaviour 613 ++eeprom->address; 614 eeprom->address &= EEPROM_9346_ADDR_MASK; 615 eeprom->output = eeprom->contents[eeprom->address]; 616 eeprom->tick = 0; 617 618 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 619 eeprom->address, eeprom->output); 620 #endif 621 } 622 break; 623 624 case Chip9346_data_write: 625 eeprom->input = (eeprom->input << 1) | (bit & 1); 626 if (eeprom->tick == 16) 627 { 628 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 629 eeprom->address, eeprom->input); 630 631 eeprom->contents[eeprom->address] = eeprom->input; 632 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 633 eeprom->tick = 0; 634 eeprom->input = 0; 635 } 636 break; 637 638 case Chip9346_data_write_all: 639 eeprom->input = (eeprom->input << 1) | (bit & 1); 640 if (eeprom->tick == 16) 641 { 642 int i; 643 for (i = 0; i < EEPROM_9346_SIZE; i++) 644 { 645 eeprom->contents[i] = eeprom->input; 646 } 647 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 648 649 eeprom->mode = Chip9346_enter_command_mode; 650 eeprom->tick = 0; 651 eeprom->input = 0; 652 } 653 break; 654 655 default: 656 break; 657 } 658 } 659 660 static int prom9346_get_wire(RTL8139State *s) 661 { 662 EEprom9346 *eeprom = &s->eeprom; 663 if (!eeprom->eecs) 664 return 0; 665 666 return eeprom->eedo; 667 } 668 669 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 670 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 671 { 672 EEprom9346 *eeprom = &s->eeprom; 673 uint8_t old_eecs = eeprom->eecs; 674 uint8_t old_eesk = eeprom->eesk; 675 676 eeprom->eecs = eecs; 677 eeprom->eesk = eesk; 678 eeprom->eedi = eedi; 679 680 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 681 eeprom->eesk, eeprom->eedi, eeprom->eedo); 682 683 if (!old_eecs && eecs) 684 { 685 /* Synchronize start */ 686 eeprom->tick = 0; 687 eeprom->input = 0; 688 eeprom->output = 0; 689 eeprom->mode = Chip9346_enter_command_mode; 690 691 DPRINTF("=== eeprom: begin access, enter command mode\n"); 692 } 693 694 if (!eecs) 695 { 696 DPRINTF("=== eeprom: end access\n"); 697 return; 698 } 699 700 if (!old_eesk && eesk) 701 { 702 /* SK front rules */ 703 prom9346_shift_clock(eeprom); 704 } 705 } 706 707 static void rtl8139_update_irq(RTL8139State *s) 708 { 709 PCIDevice *d = PCI_DEVICE(s); 710 int isr; 711 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 712 713 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 714 s->IntrMask); 715 716 pci_set_irq(d, (isr != 0)); 717 } 718 719 static int rtl8139_RxWrap(RTL8139State *s) 720 { 721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 722 return (s->RxConfig & (1 << 7)); 723 } 724 725 static int rtl8139_receiver_enabled(RTL8139State *s) 726 { 727 return s->bChipCmdState & CmdRxEnb; 728 } 729 730 static int rtl8139_transmitter_enabled(RTL8139State *s) 731 { 732 return s->bChipCmdState & CmdTxEnb; 733 } 734 735 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 736 { 737 return s->CpCmd & CPlusRxEnb; 738 } 739 740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 741 { 742 return s->CpCmd & CPlusTxEnb; 743 } 744 745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 746 { 747 PCIDevice *d = PCI_DEVICE(s); 748 749 if (s->RxBufAddr + size > s->RxBufferSize) 750 { 751 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 752 753 /* write packet data */ 754 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 755 { 756 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 757 758 if (size > wrapped) 759 { 760 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 761 buf, size-wrapped); 762 } 763 764 /* reset buffer pointer */ 765 s->RxBufAddr = 0; 766 767 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 768 buf + (size-wrapped), wrapped); 769 770 s->RxBufAddr = wrapped; 771 772 return; 773 } 774 } 775 776 /* non-wrapping path or overwrapping enabled */ 777 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); 778 779 s->RxBufAddr += size; 780 } 781 782 #define MIN_BUF_SIZE 60 783 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 784 { 785 return low | ((uint64_t)high << 32); 786 } 787 788 /* Workaround for buggy guest driver such as linux who allocates rx 789 * rings after the receiver were enabled. */ 790 static bool rtl8139_cp_rx_valid(RTL8139State *s) 791 { 792 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); 793 } 794 795 static bool rtl8139_can_receive(NetClientState *nc) 796 { 797 RTL8139State *s = qemu_get_nic_opaque(nc); 798 int avail; 799 800 /* Receive (drop) packets if card is disabled. */ 801 if (!s->clock_enabled) { 802 return true; 803 } 804 if (!rtl8139_receiver_enabled(s)) { 805 return true; 806 } 807 808 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { 809 /* ??? Flow control not implemented in c+ mode. 810 This is a hack to work around slirp deficiencies anyway. */ 811 return true; 812 } 813 814 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 815 s->RxBufferSize); 816 return avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow); 817 } 818 819 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 820 { 821 RTL8139State *s = qemu_get_nic_opaque(nc); 822 PCIDevice *d = PCI_DEVICE(s); 823 /* size is the length of the buffer passed to the driver */ 824 size_t size = size_; 825 const uint8_t *dot1q_buf = NULL; 826 827 uint32_t packet_header = 0; 828 829 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; 830 static const uint8_t broadcast_macaddr[6] = 831 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 832 833 DPRINTF(">>> received len=%zu\n", size); 834 835 /* test if board clock is stopped */ 836 if (!s->clock_enabled) 837 { 838 DPRINTF("stopped ==========================\n"); 839 return -1; 840 } 841 842 /* first check if receiver is enabled */ 843 844 if (!rtl8139_receiver_enabled(s)) 845 { 846 DPRINTF("receiver disabled ================\n"); 847 return -1; 848 } 849 850 /* XXX: check this */ 851 if (s->RxConfig & AcceptAllPhys) { 852 /* promiscuous: receive all */ 853 DPRINTF(">>> packet received in promiscuous mode\n"); 854 855 } else { 856 if (!memcmp(buf, broadcast_macaddr, 6)) { 857 /* broadcast address */ 858 if (!(s->RxConfig & AcceptBroadcast)) 859 { 860 DPRINTF(">>> broadcast packet rejected\n"); 861 862 /* update tally counter */ 863 ++s->tally_counters.RxERR; 864 865 return size; 866 } 867 868 packet_header |= RxBroadcast; 869 870 DPRINTF(">>> broadcast packet received\n"); 871 872 /* update tally counter */ 873 ++s->tally_counters.RxOkBrd; 874 875 } else if (buf[0] & 0x01) { 876 /* multicast */ 877 if (!(s->RxConfig & AcceptMulticast)) 878 { 879 DPRINTF(">>> multicast packet rejected\n"); 880 881 /* update tally counter */ 882 ++s->tally_counters.RxERR; 883 884 return size; 885 } 886 887 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 888 889 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 890 { 891 DPRINTF(">>> multicast address mismatch\n"); 892 893 /* update tally counter */ 894 ++s->tally_counters.RxERR; 895 896 return size; 897 } 898 899 packet_header |= RxMulticast; 900 901 DPRINTF(">>> multicast packet received\n"); 902 903 /* update tally counter */ 904 ++s->tally_counters.RxOkMul; 905 906 } else if (s->phys[0] == buf[0] && 907 s->phys[1] == buf[1] && 908 s->phys[2] == buf[2] && 909 s->phys[3] == buf[3] && 910 s->phys[4] == buf[4] && 911 s->phys[5] == buf[5]) { 912 /* match */ 913 if (!(s->RxConfig & AcceptMyPhys)) 914 { 915 DPRINTF(">>> rejecting physical address matching packet\n"); 916 917 /* update tally counter */ 918 ++s->tally_counters.RxERR; 919 920 return size; 921 } 922 923 packet_header |= RxPhysical; 924 925 DPRINTF(">>> physical address matching packet received\n"); 926 927 /* update tally counter */ 928 ++s->tally_counters.RxOkPhy; 929 930 } else { 931 932 DPRINTF(">>> unknown packet\n"); 933 934 /* update tally counter */ 935 ++s->tally_counters.RxERR; 936 937 return size; 938 } 939 } 940 941 /* if too small buffer, then expand it 942 * Include some tailroom in case a vlan tag is later removed. */ 943 if (size < MIN_BUF_SIZE + VLAN_HLEN) { 944 memcpy(buf1, buf, size); 945 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); 946 buf = buf1; 947 if (size < MIN_BUF_SIZE) { 948 size = MIN_BUF_SIZE; 949 } 950 } 951 952 if (rtl8139_cp_receiver_enabled(s)) 953 { 954 if (!rtl8139_cp_rx_valid(s)) { 955 return size; 956 } 957 958 DPRINTF("in C+ Rx mode ================\n"); 959 960 /* begin C+ receiver mode */ 961 962 /* w0 ownership flag */ 963 #define CP_RX_OWN (1<<31) 964 /* w0 end of ring flag */ 965 #define CP_RX_EOR (1<<30) 966 /* w0 bits 0...12 : buffer size */ 967 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 968 /* w1 tag available flag */ 969 #define CP_RX_TAVA (1<<16) 970 /* w1 bits 0...15 : VLAN tag */ 971 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 972 /* w2 low 32bit of Rx buffer ptr */ 973 /* w3 high 32bit of Rx buffer ptr */ 974 975 int descriptor = s->currCPlusRxDesc; 976 dma_addr_t cplus_rx_ring_desc; 977 978 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 979 cplus_rx_ring_desc += 16 * descriptor; 980 981 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 982 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 983 s->RxRingAddrLO, cplus_rx_ring_desc); 984 985 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 986 987 pci_dma_read(d, cplus_rx_ring_desc, &val, 4); 988 rxdw0 = le32_to_cpu(val); 989 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); 990 rxdw1 = le32_to_cpu(val); 991 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); 992 rxbufLO = le32_to_cpu(val); 993 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); 994 rxbufHI = le32_to_cpu(val); 995 996 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 997 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 998 999 if (!(rxdw0 & CP_RX_OWN)) 1000 { 1001 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 1002 descriptor); 1003 1004 s->IntrStatus |= RxOverflow; 1005 ++s->RxMissed; 1006 1007 /* update tally counter */ 1008 ++s->tally_counters.RxERR; 1009 ++s->tally_counters.MissPkt; 1010 1011 rtl8139_update_irq(s); 1012 return size_; 1013 } 1014 1015 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1016 1017 /* write VLAN info to descriptor variables. */ 1018 if (s->CpCmd & CPlusRxVLAN && 1019 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) { 1020 dot1q_buf = &buf[ETH_ALEN * 2]; 1021 size -= VLAN_HLEN; 1022 /* if too small buffer, use the tailroom added duing expansion */ 1023 if (size < MIN_BUF_SIZE) { 1024 size = MIN_BUF_SIZE; 1025 } 1026 1027 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1028 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1029 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]); 1030 1031 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1032 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN])); 1033 } else { 1034 /* reset VLAN tag flag */ 1035 rxdw1 &= ~CP_RX_TAVA; 1036 } 1037 1038 /* TODO: scatter the packet over available receive ring descriptors space */ 1039 1040 if (size+4 > rx_space) 1041 { 1042 DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n", 1043 descriptor, rx_space, size); 1044 1045 s->IntrStatus |= RxOverflow; 1046 ++s->RxMissed; 1047 1048 /* update tally counter */ 1049 ++s->tally_counters.RxERR; 1050 ++s->tally_counters.MissPkt; 1051 1052 rtl8139_update_irq(s); 1053 return size_; 1054 } 1055 1056 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1057 1058 /* receive/copy to target memory */ 1059 if (dot1q_buf) { 1060 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN); 1061 pci_dma_write(d, rx_addr + 2 * ETH_ALEN, 1062 buf + 2 * ETH_ALEN + VLAN_HLEN, 1063 size - 2 * ETH_ALEN); 1064 } else { 1065 pci_dma_write(d, rx_addr, buf, size); 1066 } 1067 1068 if (s->CpCmd & CPlusRxChkSum) 1069 { 1070 /* do some packet checksumming */ 1071 } 1072 1073 /* write checksum */ 1074 val = cpu_to_le32(crc32(0, buf, size_)); 1075 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); 1076 1077 /* first segment of received packet flag */ 1078 #define CP_RX_STATUS_FS (1<<29) 1079 /* last segment of received packet flag */ 1080 #define CP_RX_STATUS_LS (1<<28) 1081 /* multicast packet flag */ 1082 #define CP_RX_STATUS_MAR (1<<26) 1083 /* physical-matching packet flag */ 1084 #define CP_RX_STATUS_PAM (1<<25) 1085 /* broadcast packet flag */ 1086 #define CP_RX_STATUS_BAR (1<<24) 1087 /* runt packet flag */ 1088 #define CP_RX_STATUS_RUNT (1<<19) 1089 /* crc error flag */ 1090 #define CP_RX_STATUS_CRC (1<<18) 1091 /* IP checksum error flag */ 1092 #define CP_RX_STATUS_IPF (1<<15) 1093 /* UDP checksum error flag */ 1094 #define CP_RX_STATUS_UDPF (1<<14) 1095 /* TCP checksum error flag */ 1096 #define CP_RX_STATUS_TCPF (1<<13) 1097 1098 /* transfer ownership to target */ 1099 rxdw0 &= ~CP_RX_OWN; 1100 1101 /* set first segment bit */ 1102 rxdw0 |= CP_RX_STATUS_FS; 1103 1104 /* set last segment bit */ 1105 rxdw0 |= CP_RX_STATUS_LS; 1106 1107 /* set received packet type flags */ 1108 if (packet_header & RxBroadcast) 1109 rxdw0 |= CP_RX_STATUS_BAR; 1110 if (packet_header & RxMulticast) 1111 rxdw0 |= CP_RX_STATUS_MAR; 1112 if (packet_header & RxPhysical) 1113 rxdw0 |= CP_RX_STATUS_PAM; 1114 1115 /* set received size */ 1116 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1117 rxdw0 |= (size+4); 1118 1119 /* update ring data */ 1120 val = cpu_to_le32(rxdw0); 1121 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1122 val = cpu_to_le32(rxdw1); 1123 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1124 1125 /* update tally counter */ 1126 ++s->tally_counters.RxOk; 1127 1128 /* seek to next Rx descriptor */ 1129 if (rxdw0 & CP_RX_EOR) 1130 { 1131 s->currCPlusRxDesc = 0; 1132 } 1133 else 1134 { 1135 ++s->currCPlusRxDesc; 1136 } 1137 1138 DPRINTF("done C+ Rx mode ----------------\n"); 1139 1140 } 1141 else 1142 { 1143 DPRINTF("in ring Rx mode ================\n"); 1144 1145 /* begin ring receiver mode */ 1146 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1147 1148 /* if receiver buffer is empty then avail == 0 */ 1149 1150 #define RX_ALIGN(x) (((x) + 3) & ~0x3) 1151 1152 if (avail != 0 && RX_ALIGN(size + 8) >= avail) 1153 { 1154 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1155 "read 0x%04x === available 0x%04x need 0x%04zx\n", 1156 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1157 1158 s->IntrStatus |= RxOverflow; 1159 ++s->RxMissed; 1160 rtl8139_update_irq(s); 1161 return 0; 1162 } 1163 1164 packet_header |= RxStatusOK; 1165 1166 packet_header |= (((size+4) << 16) & 0xffff0000); 1167 1168 /* write header */ 1169 uint32_t val = cpu_to_le32(packet_header); 1170 1171 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1172 1173 rtl8139_write_buffer(s, buf, size); 1174 1175 /* write checksum */ 1176 val = cpu_to_le32(crc32(0, buf, size)); 1177 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1178 1179 /* correct buffer write pointer */ 1180 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); 1181 1182 /* now we can signal we have received something */ 1183 1184 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1185 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1186 } 1187 1188 s->IntrStatus |= RxOK; 1189 1190 if (do_interrupt) 1191 { 1192 rtl8139_update_irq(s); 1193 } 1194 1195 return size_; 1196 } 1197 1198 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1199 { 1200 return rtl8139_do_receive(nc, buf, size, 1); 1201 } 1202 1203 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1204 { 1205 s->RxBufferSize = bufferSize; 1206 s->RxBufPtr = 0; 1207 s->RxBufAddr = 0; 1208 } 1209 1210 static void rtl8139_reset_phy(RTL8139State *s) 1211 { 1212 s->BasicModeStatus = 0x7809; 1213 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1214 /* preserve link state */ 1215 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; 1216 1217 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1218 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1219 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1220 1221 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1222 } 1223 1224 static void rtl8139_reset(DeviceState *d) 1225 { 1226 RTL8139State *s = RTL8139(d); 1227 int i; 1228 1229 /* restore MAC address */ 1230 memcpy(s->phys, s->conf.macaddr.a, 6); 1231 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 1232 1233 /* reset interrupt mask */ 1234 s->IntrStatus = 0; 1235 s->IntrMask = 0; 1236 1237 rtl8139_update_irq(s); 1238 1239 /* mark all status registers as owned by host */ 1240 for (i = 0; i < 4; ++i) 1241 { 1242 s->TxStatus[i] = TxHostOwns; 1243 } 1244 1245 s->currTxDesc = 0; 1246 s->currCPlusRxDesc = 0; 1247 s->currCPlusTxDesc = 0; 1248 1249 s->RxRingAddrLO = 0; 1250 s->RxRingAddrHI = 0; 1251 1252 s->RxBuf = 0; 1253 1254 rtl8139_reset_rxring(s, 8192); 1255 1256 /* ACK the reset */ 1257 s->TxConfig = 0; 1258 1259 #if 0 1260 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1261 s->clock_enabled = 0; 1262 #else 1263 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1264 s->clock_enabled = 1; 1265 #endif 1266 1267 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1268 1269 /* set initial state data */ 1270 s->Config0 = 0x0; /* No boot ROM */ 1271 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1272 s->Config3 = 0x1; /* fast back-to-back compatible */ 1273 s->Config5 = 0x0; 1274 1275 s->CpCmd = 0x0; /* reset C+ mode */ 1276 s->cplus_enabled = 0; 1277 1278 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1279 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1280 s->BasicModeCtrl = 0x1000; // autonegotiation 1281 1282 rtl8139_reset_phy(s); 1283 1284 /* also reset timer and disable timer interrupt */ 1285 s->TCTR = 0; 1286 s->TimerInt = 0; 1287 s->TCTR_base = 0; 1288 rtl8139_set_next_tctr_time(s); 1289 1290 /* reset tally counters */ 1291 RTL8139TallyCounters_clear(&s->tally_counters); 1292 } 1293 1294 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1295 { 1296 counters->TxOk = 0; 1297 counters->RxOk = 0; 1298 counters->TxERR = 0; 1299 counters->RxERR = 0; 1300 counters->MissPkt = 0; 1301 counters->FAE = 0; 1302 counters->Tx1Col = 0; 1303 counters->TxMCol = 0; 1304 counters->RxOkPhy = 0; 1305 counters->RxOkBrd = 0; 1306 counters->RxOkMul = 0; 1307 counters->TxAbt = 0; 1308 counters->TxUndrn = 0; 1309 } 1310 1311 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1312 { 1313 PCIDevice *d = PCI_DEVICE(s); 1314 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1315 uint16_t val16; 1316 uint32_t val32; 1317 uint64_t val64; 1318 1319 val64 = cpu_to_le64(tally_counters->TxOk); 1320 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); 1321 1322 val64 = cpu_to_le64(tally_counters->RxOk); 1323 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); 1324 1325 val64 = cpu_to_le64(tally_counters->TxERR); 1326 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); 1327 1328 val32 = cpu_to_le32(tally_counters->RxERR); 1329 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); 1330 1331 val16 = cpu_to_le16(tally_counters->MissPkt); 1332 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); 1333 1334 val16 = cpu_to_le16(tally_counters->FAE); 1335 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); 1336 1337 val32 = cpu_to_le32(tally_counters->Tx1Col); 1338 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); 1339 1340 val32 = cpu_to_le32(tally_counters->TxMCol); 1341 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); 1342 1343 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1344 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); 1345 1346 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1347 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); 1348 1349 val32 = cpu_to_le32(tally_counters->RxOkMul); 1350 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); 1351 1352 val16 = cpu_to_le16(tally_counters->TxAbt); 1353 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); 1354 1355 val16 = cpu_to_le16(tally_counters->TxUndrn); 1356 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); 1357 } 1358 1359 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1360 { 1361 DeviceState *d = DEVICE(s); 1362 1363 val &= 0xff; 1364 1365 DPRINTF("ChipCmd write val=0x%08x\n", val); 1366 1367 if (val & CmdReset) 1368 { 1369 DPRINTF("ChipCmd reset\n"); 1370 rtl8139_reset(d); 1371 } 1372 if (val & CmdRxEnb) 1373 { 1374 DPRINTF("ChipCmd enable receiver\n"); 1375 1376 s->currCPlusRxDesc = 0; 1377 } 1378 if (val & CmdTxEnb) 1379 { 1380 DPRINTF("ChipCmd enable transmitter\n"); 1381 1382 s->currCPlusTxDesc = 0; 1383 } 1384 1385 /* mask unwritable bits */ 1386 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1387 1388 /* Deassert reset pin before next read */ 1389 val &= ~CmdReset; 1390 1391 s->bChipCmdState = val; 1392 } 1393 1394 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1395 { 1396 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1397 1398 if (unread != 0) 1399 { 1400 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1401 return 0; 1402 } 1403 1404 DPRINTF("receiver buffer is empty\n"); 1405 1406 return 1; 1407 } 1408 1409 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1410 { 1411 uint32_t ret = s->bChipCmdState; 1412 1413 if (rtl8139_RxBufferEmpty(s)) 1414 ret |= RxBufEmpty; 1415 1416 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1417 1418 return ret; 1419 } 1420 1421 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1422 { 1423 val &= 0xffff; 1424 1425 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1426 1427 s->cplus_enabled = 1; 1428 1429 /* mask unwritable bits */ 1430 val = SET_MASKED(val, 0xff84, s->CpCmd); 1431 1432 s->CpCmd = val; 1433 } 1434 1435 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1436 { 1437 uint32_t ret = s->CpCmd; 1438 1439 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1440 1441 return ret; 1442 } 1443 1444 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1445 { 1446 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1447 } 1448 1449 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1450 { 1451 uint32_t ret = 0; 1452 1453 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1454 1455 return ret; 1456 } 1457 1458 static int rtl8139_config_writable(RTL8139State *s) 1459 { 1460 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) 1461 { 1462 return 1; 1463 } 1464 1465 DPRINTF("Configuration registers are write-protected\n"); 1466 1467 return 0; 1468 } 1469 1470 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1471 { 1472 val &= 0xffff; 1473 1474 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1475 1476 /* mask unwritable bits */ 1477 uint32_t mask = 0xccff; 1478 1479 if (1 || !rtl8139_config_writable(s)) 1480 { 1481 /* Speed setting and autonegotiation enable bits are read-only */ 1482 mask |= 0x3000; 1483 /* Duplex mode setting is read-only */ 1484 mask |= 0x0100; 1485 } 1486 1487 if (val & 0x8000) { 1488 /* Reset PHY */ 1489 rtl8139_reset_phy(s); 1490 } 1491 1492 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1493 1494 s->BasicModeCtrl = val; 1495 } 1496 1497 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1498 { 1499 uint32_t ret = s->BasicModeCtrl; 1500 1501 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1502 1503 return ret; 1504 } 1505 1506 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1507 { 1508 val &= 0xffff; 1509 1510 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1511 1512 /* mask unwritable bits */ 1513 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1514 1515 s->BasicModeStatus = val; 1516 } 1517 1518 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1519 { 1520 uint32_t ret = s->BasicModeStatus; 1521 1522 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1523 1524 return ret; 1525 } 1526 1527 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1528 { 1529 DeviceState *d = DEVICE(s); 1530 1531 val &= 0xff; 1532 1533 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1534 1535 /* mask unwritable bits */ 1536 val = SET_MASKED(val, 0x31, s->Cfg9346); 1537 1538 uint32_t opmode = val & 0xc0; 1539 uint32_t eeprom_val = val & 0xf; 1540 1541 if (opmode == 0x80) { 1542 /* eeprom access */ 1543 int eecs = (eeprom_val & 0x08)?1:0; 1544 int eesk = (eeprom_val & 0x04)?1:0; 1545 int eedi = (eeprom_val & 0x02)?1:0; 1546 prom9346_set_wire(s, eecs, eesk, eedi); 1547 } else if (opmode == 0x40) { 1548 /* Reset. */ 1549 val = 0; 1550 rtl8139_reset(d); 1551 } 1552 1553 s->Cfg9346 = val; 1554 } 1555 1556 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1557 { 1558 uint32_t ret = s->Cfg9346; 1559 1560 uint32_t opmode = ret & 0xc0; 1561 1562 if (opmode == 0x80) 1563 { 1564 /* eeprom access */ 1565 int eedo = prom9346_get_wire(s); 1566 if (eedo) 1567 { 1568 ret |= 0x01; 1569 } 1570 else 1571 { 1572 ret &= ~0x01; 1573 } 1574 } 1575 1576 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1577 1578 return ret; 1579 } 1580 1581 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1582 { 1583 val &= 0xff; 1584 1585 DPRINTF("Config0 write val=0x%02x\n", val); 1586 1587 if (!rtl8139_config_writable(s)) { 1588 return; 1589 } 1590 1591 /* mask unwritable bits */ 1592 val = SET_MASKED(val, 0xf8, s->Config0); 1593 1594 s->Config0 = val; 1595 } 1596 1597 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1598 { 1599 uint32_t ret = s->Config0; 1600 1601 DPRINTF("Config0 read val=0x%02x\n", ret); 1602 1603 return ret; 1604 } 1605 1606 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1607 { 1608 val &= 0xff; 1609 1610 DPRINTF("Config1 write val=0x%02x\n", val); 1611 1612 if (!rtl8139_config_writable(s)) { 1613 return; 1614 } 1615 1616 /* mask unwritable bits */ 1617 val = SET_MASKED(val, 0xC, s->Config1); 1618 1619 s->Config1 = val; 1620 } 1621 1622 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1623 { 1624 uint32_t ret = s->Config1; 1625 1626 DPRINTF("Config1 read val=0x%02x\n", ret); 1627 1628 return ret; 1629 } 1630 1631 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1632 { 1633 val &= 0xff; 1634 1635 DPRINTF("Config3 write val=0x%02x\n", val); 1636 1637 if (!rtl8139_config_writable(s)) { 1638 return; 1639 } 1640 1641 /* mask unwritable bits */ 1642 val = SET_MASKED(val, 0x8F, s->Config3); 1643 1644 s->Config3 = val; 1645 } 1646 1647 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1648 { 1649 uint32_t ret = s->Config3; 1650 1651 DPRINTF("Config3 read val=0x%02x\n", ret); 1652 1653 return ret; 1654 } 1655 1656 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1657 { 1658 val &= 0xff; 1659 1660 DPRINTF("Config4 write val=0x%02x\n", val); 1661 1662 if (!rtl8139_config_writable(s)) { 1663 return; 1664 } 1665 1666 /* mask unwritable bits */ 1667 val = SET_MASKED(val, 0x0a, s->Config4); 1668 1669 s->Config4 = val; 1670 } 1671 1672 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1673 { 1674 uint32_t ret = s->Config4; 1675 1676 DPRINTF("Config4 read val=0x%02x\n", ret); 1677 1678 return ret; 1679 } 1680 1681 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1682 { 1683 val &= 0xff; 1684 1685 DPRINTF("Config5 write val=0x%02x\n", val); 1686 1687 /* mask unwritable bits */ 1688 val = SET_MASKED(val, 0x80, s->Config5); 1689 1690 s->Config5 = val; 1691 } 1692 1693 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1694 { 1695 uint32_t ret = s->Config5; 1696 1697 DPRINTF("Config5 read val=0x%02x\n", ret); 1698 1699 return ret; 1700 } 1701 1702 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1703 { 1704 if (!rtl8139_transmitter_enabled(s)) 1705 { 1706 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1707 return; 1708 } 1709 1710 DPRINTF("TxConfig write val=0x%08x\n", val); 1711 1712 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1713 1714 s->TxConfig = val; 1715 } 1716 1717 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1718 { 1719 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1720 1721 uint32_t tc = s->TxConfig; 1722 tc &= 0xFFFFFF00; 1723 tc |= (val & 0x000000FF); 1724 rtl8139_TxConfig_write(s, tc); 1725 } 1726 1727 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1728 { 1729 uint32_t ret = s->TxConfig; 1730 1731 DPRINTF("TxConfig read val=0x%04x\n", ret); 1732 1733 return ret; 1734 } 1735 1736 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1737 { 1738 DPRINTF("RxConfig write val=0x%08x\n", val); 1739 1740 /* mask unwritable bits */ 1741 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1742 1743 s->RxConfig = val; 1744 1745 /* reset buffer size and read/write pointers */ 1746 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1747 1748 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1749 } 1750 1751 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1752 { 1753 uint32_t ret = s->RxConfig; 1754 1755 DPRINTF("RxConfig read val=0x%08x\n", ret); 1756 1757 return ret; 1758 } 1759 1760 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1761 int do_interrupt, const uint8_t *dot1q_buf) 1762 { 1763 struct iovec *iov = NULL; 1764 struct iovec vlan_iov[3]; 1765 1766 if (!size) 1767 { 1768 DPRINTF("+++ empty ethernet frame\n"); 1769 return; 1770 } 1771 1772 if (dot1q_buf && size >= ETH_ALEN * 2) { 1773 iov = (struct iovec[3]) { 1774 { .iov_base = buf, .iov_len = ETH_ALEN * 2 }, 1775 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1776 { .iov_base = buf + ETH_ALEN * 2, 1777 .iov_len = size - ETH_ALEN * 2 }, 1778 }; 1779 1780 memcpy(vlan_iov, iov, sizeof(vlan_iov)); 1781 iov = vlan_iov; 1782 } 1783 1784 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1785 { 1786 size_t buf2_size; 1787 uint8_t *buf2; 1788 1789 if (iov) { 1790 buf2_size = iov_size(iov, 3); 1791 buf2 = g_malloc(buf2_size); 1792 iov_to_buf(iov, 3, 0, buf2, buf2_size); 1793 buf = buf2; 1794 } 1795 1796 DPRINTF("+++ transmit loopback mode\n"); 1797 qemu_receive_packet(qemu_get_queue(s->nic), buf, size); 1798 1799 if (iov) { 1800 g_free(buf2); 1801 } 1802 } 1803 else 1804 { 1805 if (iov) { 1806 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); 1807 } else { 1808 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 1809 } 1810 } 1811 } 1812 1813 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1814 { 1815 if (!rtl8139_transmitter_enabled(s)) 1816 { 1817 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1818 "disabled\n", descriptor); 1819 return 0; 1820 } 1821 1822 if (s->TxStatus[descriptor] & TxHostOwns) 1823 { 1824 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1825 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1826 return 0; 1827 } 1828 1829 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1830 1831 PCIDevice *d = PCI_DEVICE(s); 1832 int txsize = s->TxStatus[descriptor] & 0x1fff; 1833 uint8_t txbuffer[0x2000]; 1834 1835 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1836 txsize, s->TxAddr[descriptor]); 1837 1838 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); 1839 1840 /* Mark descriptor as transferred */ 1841 s->TxStatus[descriptor] |= TxHostOwns; 1842 s->TxStatus[descriptor] |= TxStatOK; 1843 1844 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1845 1846 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1847 descriptor); 1848 1849 /* update interrupt */ 1850 s->IntrStatus |= TxOK; 1851 rtl8139_update_irq(s); 1852 1853 return 1; 1854 } 1855 1856 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1857 1858 /* produces ones' complement sum of data */ 1859 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1860 { 1861 uint32_t result = 0; 1862 1863 for (; len > 1; data+=2, len-=2) 1864 { 1865 result += *(uint16_t*)data; 1866 } 1867 1868 /* add the remainder byte */ 1869 if (len) 1870 { 1871 uint8_t odd[2] = {*data, 0}; 1872 result += *(uint16_t*)odd; 1873 } 1874 1875 while (result>>16) 1876 result = (result & 0xffff) + (result >> 16); 1877 1878 return result; 1879 } 1880 1881 static uint16_t ip_checksum(void *data, size_t len) 1882 { 1883 return ~ones_complement_sum((uint8_t*)data, len); 1884 } 1885 1886 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1887 { 1888 if (!rtl8139_transmitter_enabled(s)) 1889 { 1890 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1891 return 0; 1892 } 1893 1894 if (!rtl8139_cp_transmitter_enabled(s)) 1895 { 1896 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1897 return 0 ; 1898 } 1899 1900 PCIDevice *d = PCI_DEVICE(s); 1901 int descriptor = s->currCPlusTxDesc; 1902 1903 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1904 1905 /* Normal priority ring */ 1906 cplus_tx_ring_desc += 16 * descriptor; 1907 1908 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1909 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1910 s->TxAddr[0], cplus_tx_ring_desc); 1911 1912 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1913 1914 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1915 txdw0 = le32_to_cpu(val); 1916 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1917 txdw1 = le32_to_cpu(val); 1918 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1919 txbufLO = le32_to_cpu(val); 1920 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1921 txbufHI = le32_to_cpu(val); 1922 1923 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1924 txdw0, txdw1, txbufLO, txbufHI); 1925 1926 /* w0 ownership flag */ 1927 #define CP_TX_OWN (1<<31) 1928 /* w0 end of ring flag */ 1929 #define CP_TX_EOR (1<<30) 1930 /* first segment of received packet flag */ 1931 #define CP_TX_FS (1<<29) 1932 /* last segment of received packet flag */ 1933 #define CP_TX_LS (1<<28) 1934 /* large send packet flag */ 1935 #define CP_TX_LGSEN (1<<27) 1936 /* large send MSS mask, bits 16...26 */ 1937 #define CP_TC_LGSEN_MSS_SHIFT 16 1938 #define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1) 1939 1940 /* IP checksum offload flag */ 1941 #define CP_TX_IPCS (1<<18) 1942 /* UDP checksum offload flag */ 1943 #define CP_TX_UDPCS (1<<17) 1944 /* TCP checksum offload flag */ 1945 #define CP_TX_TCPCS (1<<16) 1946 1947 /* w0 bits 0...15 : buffer size */ 1948 #define CP_TX_BUFFER_SIZE (1<<16) 1949 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 1950 /* w1 add tag flag */ 1951 #define CP_TX_TAGC (1<<17) 1952 /* w1 bits 0...15 : VLAN tag (big endian) */ 1953 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 1954 /* w2 low 32bit of Rx buffer ptr */ 1955 /* w3 high 32bit of Rx buffer ptr */ 1956 1957 /* set after transmission */ 1958 /* FIFO underrun flag */ 1959 #define CP_TX_STATUS_UNF (1<<25) 1960 /* transmit error summary flag, valid if set any of three below */ 1961 #define CP_TX_STATUS_TES (1<<23) 1962 /* out-of-window collision flag */ 1963 #define CP_TX_STATUS_OWC (1<<22) 1964 /* link failure flag */ 1965 #define CP_TX_STATUS_LNKF (1<<21) 1966 /* excessive collisions flag */ 1967 #define CP_TX_STATUS_EXC (1<<20) 1968 1969 if (!(txdw0 & CP_TX_OWN)) 1970 { 1971 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 1972 return 0 ; 1973 } 1974 1975 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 1976 1977 if (txdw0 & CP_TX_FS) 1978 { 1979 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 1980 "descriptor\n", descriptor); 1981 1982 /* reset internal buffer offset */ 1983 s->cplus_txbuffer_offset = 0; 1984 } 1985 1986 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 1987 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 1988 1989 /* make sure we have enough space to assemble the packet */ 1990 if (!s->cplus_txbuffer) 1991 { 1992 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 1993 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 1994 s->cplus_txbuffer_offset = 0; 1995 1996 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 1997 s->cplus_txbuffer_len); 1998 } 1999 2000 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 2001 { 2002 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 2003 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 2004 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 2005 "length to %d\n", txsize); 2006 } 2007 2008 /* append more data to the packet */ 2009 2010 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 2011 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2012 s->cplus_txbuffer_offset); 2013 2014 pci_dma_read(d, tx_addr, 2015 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2016 s->cplus_txbuffer_offset += txsize; 2017 2018 /* seek to next Rx descriptor */ 2019 if (txdw0 & CP_TX_EOR) 2020 { 2021 s->currCPlusTxDesc = 0; 2022 } 2023 else 2024 { 2025 ++s->currCPlusTxDesc; 2026 if (s->currCPlusTxDesc >= 64) 2027 s->currCPlusTxDesc = 0; 2028 } 2029 2030 /* Build the Tx Status Descriptor */ 2031 uint32_t tx_status = txdw0; 2032 2033 /* transfer ownership to target */ 2034 tx_status &= ~CP_TX_OWN; 2035 2036 /* reset error indicator bits */ 2037 tx_status &= ~CP_TX_STATUS_UNF; 2038 tx_status &= ~CP_TX_STATUS_TES; 2039 tx_status &= ~CP_TX_STATUS_OWC; 2040 tx_status &= ~CP_TX_STATUS_LNKF; 2041 tx_status &= ~CP_TX_STATUS_EXC; 2042 2043 /* update ring data */ 2044 val = cpu_to_le32(tx_status); 2045 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2046 2047 /* Now decide if descriptor being processed is holding the last segment of packet */ 2048 if (txdw0 & CP_TX_LS) 2049 { 2050 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2051 uint16_t *dot1q_buffer; 2052 2053 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2054 descriptor); 2055 2056 /* can transfer fully assembled packet */ 2057 2058 uint8_t *saved_buffer = s->cplus_txbuffer; 2059 int saved_size = s->cplus_txbuffer_offset; 2060 int saved_buffer_len = s->cplus_txbuffer_len; 2061 2062 /* create vlan tag */ 2063 if (txdw1 & CP_TX_TAGC) { 2064 /* the vlan tag is in BE byte order in the descriptor 2065 * BE + le_to_cpu() + ~swap()~ = cpu */ 2066 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2067 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2068 2069 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2070 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN); 2071 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2072 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2073 } else { 2074 dot1q_buffer = NULL; 2075 } 2076 2077 /* reset the card space to protect from recursive call */ 2078 s->cplus_txbuffer = NULL; 2079 s->cplus_txbuffer_offset = 0; 2080 s->cplus_txbuffer_len = 0; 2081 2082 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2083 { 2084 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2085 2086 /* Large enough for Ethernet and IP headers? */ 2087 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) { 2088 goto skip_offload; 2089 } 2090 2091 /* ip packet header */ 2092 struct ip_header *ip = NULL; 2093 int hlen = 0; 2094 uint8_t ip_protocol = 0; 2095 uint16_t ip_data_len = 0; 2096 2097 uint8_t *eth_payload_data = NULL; 2098 size_t eth_payload_len = 0; 2099 2100 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2101 if (proto != ETH_P_IP) 2102 { 2103 goto skip_offload; 2104 } 2105 2106 DPRINTF("+++ C+ mode has IP packet\n"); 2107 2108 /* Note on memory alignment: eth_payload_data is 16-bit aligned 2109 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is 2110 * even. 32-bit accesses must use ldl/stl wrappers to avoid 2111 * unaligned accesses. 2112 */ 2113 eth_payload_data = saved_buffer + ETH_HLEN; 2114 eth_payload_len = saved_size - ETH_HLEN; 2115 2116 ip = (struct ip_header*)eth_payload_data; 2117 2118 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2119 DPRINTF("+++ C+ mode packet has bad IP version %d " 2120 "expected %d\n", IP_HEADER_VERSION(ip), 2121 IP_HEADER_VERSION_4); 2122 goto skip_offload; 2123 } 2124 2125 hlen = IP_HDR_GET_LEN(ip); 2126 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) { 2127 goto skip_offload; 2128 } 2129 2130 ip_protocol = ip->ip_p; 2131 2132 ip_data_len = be16_to_cpu(ip->ip_len); 2133 if (ip_data_len < hlen || ip_data_len > eth_payload_len) { 2134 goto skip_offload; 2135 } 2136 ip_data_len -= hlen; 2137 2138 if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & CP_TX_IPCS)) 2139 { 2140 DPRINTF("+++ C+ mode need IP checksum\n"); 2141 2142 ip->ip_sum = 0; 2143 ip->ip_sum = ip_checksum(ip, hlen); 2144 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2145 hlen, ip->ip_sum); 2146 } 2147 2148 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2149 { 2150 /* Large enough for the TCP header? */ 2151 if (ip_data_len < sizeof(tcp_header)) { 2152 goto skip_offload; 2153 } 2154 2155 int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) & 2156 CP_TC_LGSEN_MSS_MASK; 2157 2158 DPRINTF("+++ C+ mode offloaded task TSO IP data %d " 2159 "frame data %d specified MSS=%d\n", 2160 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2161 2162 int tcp_send_offset = 0; 2163 2164 /* maximum IP header length is 60 bytes */ 2165 uint8_t saved_ip_header[60]; 2166 2167 /* save IP header template; data area is used in tcp checksum calculation */ 2168 memcpy(saved_ip_header, eth_payload_data, hlen); 2169 2170 /* a placeholder for checksum calculation routine in tcp case */ 2171 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2172 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2173 2174 /* pointer to TCP header */ 2175 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2176 2177 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2178 2179 /* Invalid TCP data offset? */ 2180 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) { 2181 goto skip_offload; 2182 } 2183 2184 int tcp_data_len = ip_data_len - tcp_hlen; 2185 2186 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2187 "data len %d\n", ip_data_len, tcp_hlen, tcp_data_len); 2188 2189 /* note the cycle below overwrites IP header data, 2190 but restores it from saved_ip_header before sending packet */ 2191 2192 int is_last_frame = 0; 2193 2194 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += large_send_mss) 2195 { 2196 uint16_t chunk_size = large_send_mss; 2197 2198 /* check if this is the last frame */ 2199 if (tcp_send_offset + large_send_mss >= tcp_data_len) 2200 { 2201 is_last_frame = 1; 2202 chunk_size = tcp_data_len - tcp_send_offset; 2203 } 2204 2205 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2206 ldl_be_p(&p_tcp_hdr->th_seq)); 2207 2208 /* add 4 TCP pseudoheader fields */ 2209 /* copy IP source and destination fields */ 2210 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2211 2212 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2213 "packet with %d bytes data\n", tcp_hlen + 2214 chunk_size); 2215 2216 if (tcp_send_offset) 2217 { 2218 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2219 } 2220 2221 /* keep PUSH and FIN flags only for the last frame */ 2222 if (!is_last_frame) 2223 { 2224 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN); 2225 } 2226 2227 /* recalculate TCP checksum */ 2228 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2229 p_tcpip_hdr->zeros = 0; 2230 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2231 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2232 2233 p_tcp_hdr->th_sum = 0; 2234 2235 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2236 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2237 tcp_checksum); 2238 2239 p_tcp_hdr->th_sum = tcp_checksum; 2240 2241 /* restore IP header */ 2242 memcpy(eth_payload_data, saved_ip_header, hlen); 2243 2244 /* set IP data length and recalculate IP checksum */ 2245 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2246 2247 /* increment IP id for subsequent frames */ 2248 ip->ip_id = cpu_to_be16(tcp_send_offset/large_send_mss + be16_to_cpu(ip->ip_id)); 2249 2250 ip->ip_sum = 0; 2251 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2252 DPRINTF("+++ C+ mode TSO IP header len=%d " 2253 "checksum=%04x\n", hlen, ip->ip_sum); 2254 2255 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2256 DPRINTF("+++ C+ mode TSO transferring packet size " 2257 "%d\n", tso_send_size); 2258 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2259 0, (uint8_t *) dot1q_buffer); 2260 2261 /* add transferred count to TCP sequence number */ 2262 stl_be_p(&p_tcp_hdr->th_seq, 2263 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); 2264 } 2265 2266 /* Stop sending this frame */ 2267 saved_size = 0; 2268 } 2269 else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))) 2270 { 2271 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2272 2273 /* maximum IP header length is 60 bytes */ 2274 uint8_t saved_ip_header[60]; 2275 memcpy(saved_ip_header, eth_payload_data, hlen); 2276 2277 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2278 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2279 2280 /* add 4 TCP pseudoheader fields */ 2281 /* copy IP source and destination fields */ 2282 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2283 2284 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2285 { 2286 DPRINTF("+++ C+ mode calculating TCP checksum for " 2287 "packet with %d bytes data\n", ip_data_len); 2288 2289 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2290 p_tcpip_hdr->zeros = 0; 2291 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2292 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2293 2294 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2295 2296 p_tcp_hdr->th_sum = 0; 2297 2298 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2299 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2300 tcp_checksum); 2301 2302 p_tcp_hdr->th_sum = tcp_checksum; 2303 } 2304 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2305 { 2306 DPRINTF("+++ C+ mode calculating UDP checksum for " 2307 "packet with %d bytes data\n", ip_data_len); 2308 2309 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2310 p_udpip_hdr->zeros = 0; 2311 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2312 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2313 2314 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2315 2316 p_udp_hdr->uh_sum = 0; 2317 2318 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2319 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2320 udp_checksum); 2321 2322 p_udp_hdr->uh_sum = udp_checksum; 2323 } 2324 2325 /* restore IP header */ 2326 memcpy(eth_payload_data, saved_ip_header, hlen); 2327 } 2328 } 2329 2330 skip_offload: 2331 /* update tally counter */ 2332 ++s->tally_counters.TxOk; 2333 2334 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2335 2336 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2337 (uint8_t *) dot1q_buffer); 2338 2339 /* restore card space if there was no recursion and reset offset */ 2340 if (!s->cplus_txbuffer) 2341 { 2342 s->cplus_txbuffer = saved_buffer; 2343 s->cplus_txbuffer_len = saved_buffer_len; 2344 s->cplus_txbuffer_offset = 0; 2345 } 2346 else 2347 { 2348 g_free(saved_buffer); 2349 } 2350 } 2351 else 2352 { 2353 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2354 } 2355 2356 return 1; 2357 } 2358 2359 static void rtl8139_cplus_transmit(RTL8139State *s) 2360 { 2361 int txcount = 0; 2362 2363 while (txcount < 64 && rtl8139_cplus_transmit_one(s)) 2364 { 2365 ++txcount; 2366 } 2367 2368 /* Mark transfer completed */ 2369 if (!txcount) 2370 { 2371 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2372 s->currCPlusTxDesc); 2373 } 2374 else 2375 { 2376 /* update interrupt status */ 2377 s->IntrStatus |= TxOK; 2378 rtl8139_update_irq(s); 2379 } 2380 } 2381 2382 static void rtl8139_transmit(RTL8139State *s) 2383 { 2384 int descriptor = s->currTxDesc, txcount = 0; 2385 2386 /*while*/ 2387 if (rtl8139_transmit_one(s, descriptor)) 2388 { 2389 ++s->currTxDesc; 2390 s->currTxDesc %= 4; 2391 ++txcount; 2392 } 2393 2394 /* Mark transfer completed */ 2395 if (!txcount) 2396 { 2397 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2398 s->currTxDesc); 2399 } 2400 } 2401 2402 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2403 { 2404 2405 int descriptor = txRegOffset/4; 2406 2407 /* handle C+ transmit mode register configuration */ 2408 2409 if (s->cplus_enabled) 2410 { 2411 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2412 "descriptor=%d\n", txRegOffset, val, descriptor); 2413 2414 /* handle Dump Tally Counters command */ 2415 s->TxStatus[descriptor] = val; 2416 2417 if (descriptor == 0 && (val & 0x8)) 2418 { 2419 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2420 2421 /* dump tally counters to specified memory location */ 2422 RTL8139TallyCounters_dma_write(s, tc_addr); 2423 2424 /* mark dump completed */ 2425 s->TxStatus[0] &= ~0x8; 2426 } 2427 2428 return; 2429 } 2430 2431 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2432 txRegOffset, val, descriptor); 2433 2434 /* mask only reserved bits */ 2435 val &= ~0xff00c000; /* these bits are reset on write */ 2436 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2437 2438 s->TxStatus[descriptor] = val; 2439 2440 /* attempt to start transmission */ 2441 rtl8139_transmit(s); 2442 } 2443 2444 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], 2445 uint32_t base, uint8_t addr, 2446 int size) 2447 { 2448 uint32_t reg = (addr - base) / 4; 2449 uint32_t offset = addr & 0x3; 2450 uint32_t ret = 0; 2451 2452 if (addr & (size - 1)) { 2453 DPRINTF("not implemented read for TxStatus/TxAddr " 2454 "addr=0x%x size=0x%x\n", addr, size); 2455 return ret; 2456 } 2457 2458 switch (size) { 2459 case 1: /* fall through */ 2460 case 2: /* fall through */ 2461 case 4: 2462 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); 2463 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", 2464 reg, addr, size, ret); 2465 break; 2466 default: 2467 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); 2468 break; 2469 } 2470 2471 return ret; 2472 } 2473 2474 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2475 { 2476 uint16_t ret = 0; 2477 2478 /* Simulate TSAD, it is read only anyway */ 2479 2480 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2481 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2482 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2483 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2484 2485 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2486 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2487 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2488 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2489 2490 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2491 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2492 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2493 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2494 2495 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2496 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2497 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2498 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2499 2500 2501 DPRINTF("TSAD read val=0x%04x\n", ret); 2502 2503 return ret; 2504 } 2505 2506 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2507 { 2508 uint16_t ret = s->CSCR; 2509 2510 DPRINTF("CSCR read val=0x%04x\n", ret); 2511 2512 return ret; 2513 } 2514 2515 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2516 { 2517 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2518 2519 s->TxAddr[txAddrOffset/4] = val; 2520 } 2521 2522 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2523 { 2524 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2525 2526 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2527 2528 return ret; 2529 } 2530 2531 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2532 { 2533 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2534 2535 /* this value is off by 16 */ 2536 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2537 2538 /* more buffer space may be available so try to receive */ 2539 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 2540 2541 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2542 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2543 } 2544 2545 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2546 { 2547 /* this value is off by 16 */ 2548 uint32_t ret = s->RxBufPtr - 0x10; 2549 2550 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2551 2552 return ret; 2553 } 2554 2555 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2556 { 2557 /* this value is NOT off by 16 */ 2558 uint32_t ret = s->RxBufAddr; 2559 2560 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2561 2562 return ret; 2563 } 2564 2565 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2566 { 2567 DPRINTF("RxBuf write val=0x%08x\n", val); 2568 2569 s->RxBuf = val; 2570 2571 /* may need to reset rxring here */ 2572 } 2573 2574 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2575 { 2576 uint32_t ret = s->RxBuf; 2577 2578 DPRINTF("RxBuf read val=0x%08x\n", ret); 2579 2580 return ret; 2581 } 2582 2583 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2584 { 2585 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2586 2587 /* mask unwritable bits */ 2588 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2589 2590 s->IntrMask = val; 2591 2592 rtl8139_update_irq(s); 2593 2594 } 2595 2596 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2597 { 2598 uint32_t ret = s->IntrMask; 2599 2600 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2601 2602 return ret; 2603 } 2604 2605 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2606 { 2607 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2608 2609 #if 0 2610 2611 /* writing to ISR has no effect */ 2612 2613 return; 2614 2615 #else 2616 uint16_t newStatus = s->IntrStatus & ~val; 2617 2618 /* mask unwritable bits */ 2619 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2620 2621 /* writing 1 to interrupt status register bit clears it */ 2622 s->IntrStatus = 0; 2623 rtl8139_update_irq(s); 2624 2625 s->IntrStatus = newStatus; 2626 rtl8139_set_next_tctr_time(s); 2627 rtl8139_update_irq(s); 2628 2629 #endif 2630 } 2631 2632 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2633 { 2634 uint32_t ret = s->IntrStatus; 2635 2636 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2637 2638 #if 0 2639 2640 /* reading ISR clears all interrupts */ 2641 s->IntrStatus = 0; 2642 2643 rtl8139_update_irq(s); 2644 2645 #endif 2646 2647 return ret; 2648 } 2649 2650 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2651 { 2652 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2653 2654 /* mask unwritable bits */ 2655 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2656 2657 s->MultiIntr = val; 2658 } 2659 2660 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2661 { 2662 uint32_t ret = s->MultiIntr; 2663 2664 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2665 2666 return ret; 2667 } 2668 2669 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2670 { 2671 RTL8139State *s = opaque; 2672 2673 switch (addr) 2674 { 2675 case MAC0 ... MAC0+4: 2676 s->phys[addr - MAC0] = val; 2677 break; 2678 case MAC0+5: 2679 s->phys[addr - MAC0] = val; 2680 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 2681 break; 2682 case MAC0+6 ... MAC0+7: 2683 /* reserved */ 2684 break; 2685 case MAR0 ... MAR0+7: 2686 s->mult[addr - MAR0] = val; 2687 break; 2688 case ChipCmd: 2689 rtl8139_ChipCmd_write(s, val); 2690 break; 2691 case Cfg9346: 2692 rtl8139_Cfg9346_write(s, val); 2693 break; 2694 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2695 rtl8139_TxConfig_writeb(s, val); 2696 break; 2697 case Config0: 2698 rtl8139_Config0_write(s, val); 2699 break; 2700 case Config1: 2701 rtl8139_Config1_write(s, val); 2702 break; 2703 case Config3: 2704 rtl8139_Config3_write(s, val); 2705 break; 2706 case Config4: 2707 rtl8139_Config4_write(s, val); 2708 break; 2709 case Config5: 2710 rtl8139_Config5_write(s, val); 2711 break; 2712 case MediaStatus: 2713 /* ignore */ 2714 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2715 val); 2716 break; 2717 2718 case HltClk: 2719 DPRINTF("HltClk write val=0x%08x\n", val); 2720 if (val == 'R') 2721 { 2722 s->clock_enabled = 1; 2723 } 2724 else if (val == 'H') 2725 { 2726 s->clock_enabled = 0; 2727 } 2728 break; 2729 2730 case TxThresh: 2731 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2732 s->TxThresh = val; 2733 break; 2734 2735 case TxPoll: 2736 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2737 if (val & (1 << 7)) 2738 { 2739 DPRINTF("C+ TxPoll high priority transmission (not " 2740 "implemented)\n"); 2741 //rtl8139_cplus_transmit(s); 2742 } 2743 if (val & (1 << 6)) 2744 { 2745 DPRINTF("C+ TxPoll normal priority transmission\n"); 2746 rtl8139_cplus_transmit(s); 2747 } 2748 2749 break; 2750 2751 default: 2752 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2753 val); 2754 break; 2755 } 2756 } 2757 2758 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2759 { 2760 RTL8139State *s = opaque; 2761 2762 switch (addr) 2763 { 2764 case IntrMask: 2765 rtl8139_IntrMask_write(s, val); 2766 break; 2767 2768 case IntrStatus: 2769 rtl8139_IntrStatus_write(s, val); 2770 break; 2771 2772 case MultiIntr: 2773 rtl8139_MultiIntr_write(s, val); 2774 break; 2775 2776 case RxBufPtr: 2777 rtl8139_RxBufPtr_write(s, val); 2778 break; 2779 2780 case BasicModeCtrl: 2781 rtl8139_BasicModeCtrl_write(s, val); 2782 break; 2783 case BasicModeStatus: 2784 rtl8139_BasicModeStatus_write(s, val); 2785 break; 2786 case NWayAdvert: 2787 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2788 s->NWayAdvert = val; 2789 break; 2790 case NWayLPAR: 2791 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2792 break; 2793 case NWayExpansion: 2794 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2795 s->NWayExpansion = val; 2796 break; 2797 2798 case CpCmd: 2799 rtl8139_CpCmd_write(s, val); 2800 break; 2801 2802 case IntrMitigate: 2803 rtl8139_IntrMitigate_write(s, val); 2804 break; 2805 2806 default: 2807 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2808 addr, val); 2809 2810 rtl8139_io_writeb(opaque, addr, val & 0xff); 2811 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2812 break; 2813 } 2814 } 2815 2816 static void rtl8139_set_next_tctr_time(RTL8139State *s) 2817 { 2818 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32; 2819 2820 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2821 2822 /* This function is called at least once per period, so it is a good 2823 * place to update the timer base. 2824 * 2825 * After one iteration of this loop the value in the Timer register does 2826 * not change, but the device model is counting up by 2^32 ticks (approx. 2827 * 130 seconds). 2828 */ 2829 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2830 s->TCTR_base += ns_per_period; 2831 } 2832 2833 if (!s->TimerInt) { 2834 timer_del(s->timer); 2835 } else { 2836 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; 2837 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2838 delta += ns_per_period; 2839 } 2840 timer_mod(s->timer, s->TCTR_base + delta); 2841 } 2842 } 2843 2844 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2845 { 2846 RTL8139State *s = opaque; 2847 2848 switch (addr) 2849 { 2850 case RxMissed: 2851 DPRINTF("RxMissed clearing on write\n"); 2852 s->RxMissed = 0; 2853 break; 2854 2855 case TxConfig: 2856 rtl8139_TxConfig_write(s, val); 2857 break; 2858 2859 case RxConfig: 2860 rtl8139_RxConfig_write(s, val); 2861 break; 2862 2863 case TxStatus0 ... TxStatus0+4*4-1: 2864 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2865 break; 2866 2867 case TxAddr0 ... TxAddr0+4*4-1: 2868 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2869 break; 2870 2871 case RxBuf: 2872 rtl8139_RxBuf_write(s, val); 2873 break; 2874 2875 case RxRingAddrLO: 2876 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2877 s->RxRingAddrLO = val; 2878 break; 2879 2880 case RxRingAddrHI: 2881 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2882 s->RxRingAddrHI = val; 2883 break; 2884 2885 case Timer: 2886 DPRINTF("TCTR Timer reset on write\n"); 2887 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2888 rtl8139_set_next_tctr_time(s); 2889 break; 2890 2891 case FlashReg: 2892 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2893 if (s->TimerInt != val) { 2894 s->TimerInt = val; 2895 rtl8139_set_next_tctr_time(s); 2896 } 2897 break; 2898 2899 default: 2900 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2901 addr, val); 2902 rtl8139_io_writeb(opaque, addr, val & 0xff); 2903 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2904 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2905 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2906 break; 2907 } 2908 } 2909 2910 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2911 { 2912 RTL8139State *s = opaque; 2913 int ret; 2914 2915 switch (addr) 2916 { 2917 case MAC0 ... MAC0+5: 2918 ret = s->phys[addr - MAC0]; 2919 break; 2920 case MAC0+6 ... MAC0+7: 2921 ret = 0; 2922 break; 2923 case MAR0 ... MAR0+7: 2924 ret = s->mult[addr - MAR0]; 2925 break; 2926 case TxStatus0 ... TxStatus0+4*4-1: 2927 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 2928 addr, 1); 2929 break; 2930 case ChipCmd: 2931 ret = rtl8139_ChipCmd_read(s); 2932 break; 2933 case Cfg9346: 2934 ret = rtl8139_Cfg9346_read(s); 2935 break; 2936 case Config0: 2937 ret = rtl8139_Config0_read(s); 2938 break; 2939 case Config1: 2940 ret = rtl8139_Config1_read(s); 2941 break; 2942 case Config3: 2943 ret = rtl8139_Config3_read(s); 2944 break; 2945 case Config4: 2946 ret = rtl8139_Config4_read(s); 2947 break; 2948 case Config5: 2949 ret = rtl8139_Config5_read(s); 2950 break; 2951 2952 case MediaStatus: 2953 /* The LinkDown bit of MediaStatus is inverse with link status */ 2954 ret = 0xd0 | (~s->BasicModeStatus & 0x04); 2955 DPRINTF("MediaStatus read 0x%x\n", ret); 2956 break; 2957 2958 case HltClk: 2959 ret = s->clock_enabled; 2960 DPRINTF("HltClk read 0x%x\n", ret); 2961 break; 2962 2963 case PCIRevisionID: 2964 ret = RTL8139_PCI_REVID; 2965 DPRINTF("PCI Revision ID read 0x%x\n", ret); 2966 break; 2967 2968 case TxThresh: 2969 ret = s->TxThresh; 2970 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 2971 break; 2972 2973 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 2974 ret = s->TxConfig >> 24; 2975 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 2976 break; 2977 2978 default: 2979 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 2980 ret = 0; 2981 break; 2982 } 2983 2984 return ret; 2985 } 2986 2987 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 2988 { 2989 RTL8139State *s = opaque; 2990 uint32_t ret; 2991 2992 switch (addr) 2993 { 2994 case TxAddr0 ... TxAddr0+4*4-1: 2995 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); 2996 break; 2997 case IntrMask: 2998 ret = rtl8139_IntrMask_read(s); 2999 break; 3000 3001 case IntrStatus: 3002 ret = rtl8139_IntrStatus_read(s); 3003 break; 3004 3005 case MultiIntr: 3006 ret = rtl8139_MultiIntr_read(s); 3007 break; 3008 3009 case RxBufPtr: 3010 ret = rtl8139_RxBufPtr_read(s); 3011 break; 3012 3013 case RxBufAddr: 3014 ret = rtl8139_RxBufAddr_read(s); 3015 break; 3016 3017 case BasicModeCtrl: 3018 ret = rtl8139_BasicModeCtrl_read(s); 3019 break; 3020 case BasicModeStatus: 3021 ret = rtl8139_BasicModeStatus_read(s); 3022 break; 3023 case NWayAdvert: 3024 ret = s->NWayAdvert; 3025 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3026 break; 3027 case NWayLPAR: 3028 ret = s->NWayLPAR; 3029 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3030 break; 3031 case NWayExpansion: 3032 ret = s->NWayExpansion; 3033 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3034 break; 3035 3036 case CpCmd: 3037 ret = rtl8139_CpCmd_read(s); 3038 break; 3039 3040 case IntrMitigate: 3041 ret = rtl8139_IntrMitigate_read(s); 3042 break; 3043 3044 case TxSummary: 3045 ret = rtl8139_TSAD_read(s); 3046 break; 3047 3048 case CSCR: 3049 ret = rtl8139_CSCR_read(s); 3050 break; 3051 3052 default: 3053 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3054 3055 ret = rtl8139_io_readb(opaque, addr); 3056 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3057 3058 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3059 break; 3060 } 3061 3062 return ret; 3063 } 3064 3065 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3066 { 3067 RTL8139State *s = opaque; 3068 uint32_t ret; 3069 3070 switch (addr) 3071 { 3072 case RxMissed: 3073 ret = s->RxMissed; 3074 3075 DPRINTF("RxMissed read val=0x%08x\n", ret); 3076 break; 3077 3078 case TxConfig: 3079 ret = rtl8139_TxConfig_read(s); 3080 break; 3081 3082 case RxConfig: 3083 ret = rtl8139_RxConfig_read(s); 3084 break; 3085 3086 case TxStatus0 ... TxStatus0+4*4-1: 3087 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 3088 addr, 4); 3089 break; 3090 3091 case TxAddr0 ... TxAddr0+4*4-1: 3092 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3093 break; 3094 3095 case RxBuf: 3096 ret = rtl8139_RxBuf_read(s); 3097 break; 3098 3099 case RxRingAddrLO: 3100 ret = s->RxRingAddrLO; 3101 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3102 break; 3103 3104 case RxRingAddrHI: 3105 ret = s->RxRingAddrHI; 3106 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3107 break; 3108 3109 case Timer: 3110 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / 3111 PCI_PERIOD; 3112 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3113 break; 3114 3115 case FlashReg: 3116 ret = s->TimerInt; 3117 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3118 break; 3119 3120 default: 3121 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3122 3123 ret = rtl8139_io_readb(opaque, addr); 3124 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3125 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3126 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3127 3128 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3129 break; 3130 } 3131 3132 return ret; 3133 } 3134 3135 /* */ 3136 3137 static int rtl8139_post_load(void *opaque, int version_id) 3138 { 3139 RTL8139State* s = opaque; 3140 rtl8139_set_next_tctr_time(s); 3141 if (version_id < 4) { 3142 s->cplus_enabled = s->CpCmd != 0; 3143 } 3144 3145 /* nc.link_down can't be migrated, so infer link_down according 3146 * to link status bit in BasicModeStatus */ 3147 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; 3148 3149 return 0; 3150 } 3151 3152 static bool rtl8139_hotplug_ready_needed(void *opaque) 3153 { 3154 return qdev_machine_modified(); 3155 } 3156 3157 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3158 .name = "rtl8139/hotplug_ready", 3159 .version_id = 1, 3160 .minimum_version_id = 1, 3161 .needed = rtl8139_hotplug_ready_needed, 3162 .fields = (VMStateField[]) { 3163 VMSTATE_END_OF_LIST() 3164 } 3165 }; 3166 3167 static int rtl8139_pre_save(void *opaque) 3168 { 3169 RTL8139State* s = opaque; 3170 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 3171 3172 /* for migration to older versions */ 3173 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; 3174 s->rtl8139_mmio_io_addr_dummy = 0; 3175 3176 return 0; 3177 } 3178 3179 static const VMStateDescription vmstate_rtl8139 = { 3180 .name = "rtl8139", 3181 .version_id = 5, 3182 .minimum_version_id = 3, 3183 .post_load = rtl8139_post_load, 3184 .pre_save = rtl8139_pre_save, 3185 .fields = (VMStateField[]) { 3186 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), 3187 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3188 VMSTATE_BUFFER(mult, RTL8139State), 3189 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3190 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3191 3192 VMSTATE_UINT32(RxBuf, RTL8139State), 3193 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3194 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3195 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3196 3197 VMSTATE_UINT16(IntrStatus, RTL8139State), 3198 VMSTATE_UINT16(IntrMask, RTL8139State), 3199 3200 VMSTATE_UINT32(TxConfig, RTL8139State), 3201 VMSTATE_UINT32(RxConfig, RTL8139State), 3202 VMSTATE_UINT32(RxMissed, RTL8139State), 3203 VMSTATE_UINT16(CSCR, RTL8139State), 3204 3205 VMSTATE_UINT8(Cfg9346, RTL8139State), 3206 VMSTATE_UINT8(Config0, RTL8139State), 3207 VMSTATE_UINT8(Config1, RTL8139State), 3208 VMSTATE_UINT8(Config3, RTL8139State), 3209 VMSTATE_UINT8(Config4, RTL8139State), 3210 VMSTATE_UINT8(Config5, RTL8139State), 3211 3212 VMSTATE_UINT8(clock_enabled, RTL8139State), 3213 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3214 3215 VMSTATE_UINT16(MultiIntr, RTL8139State), 3216 3217 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3218 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3219 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3220 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3221 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3222 3223 VMSTATE_UINT16(CpCmd, RTL8139State), 3224 VMSTATE_UINT8(TxThresh, RTL8139State), 3225 3226 VMSTATE_UNUSED(4), 3227 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3228 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3229 3230 VMSTATE_UINT32(currTxDesc, RTL8139State), 3231 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3232 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3233 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3234 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3235 3236 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3237 VMSTATE_INT32(eeprom.mode, RTL8139State), 3238 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3239 VMSTATE_UINT8(eeprom.address, RTL8139State), 3240 VMSTATE_UINT16(eeprom.input, RTL8139State), 3241 VMSTATE_UINT16(eeprom.output, RTL8139State), 3242 3243 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3244 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3245 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3246 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3247 3248 VMSTATE_UINT32(TCTR, RTL8139State), 3249 VMSTATE_UINT32(TimerInt, RTL8139State), 3250 VMSTATE_INT64(TCTR_base, RTL8139State), 3251 3252 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State), 3253 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State), 3254 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State), 3255 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State), 3256 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State), 3257 VMSTATE_UINT16(tally_counters.FAE, RTL8139State), 3258 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State), 3259 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State), 3260 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State), 3261 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State), 3262 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5), 3263 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State), 3264 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State), 3265 3266 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3267 VMSTATE_END_OF_LIST() 3268 }, 3269 .subsections = (const VMStateDescription*[]) { 3270 &vmstate_rtl8139_hotplug_ready, 3271 NULL 3272 } 3273 }; 3274 3275 /***********************************************************/ 3276 /* PCI RTL8139 definitions */ 3277 3278 static void rtl8139_ioport_write(void *opaque, hwaddr addr, 3279 uint64_t val, unsigned size) 3280 { 3281 switch (size) { 3282 case 1: 3283 rtl8139_io_writeb(opaque, addr, val); 3284 break; 3285 case 2: 3286 rtl8139_io_writew(opaque, addr, val); 3287 break; 3288 case 4: 3289 rtl8139_io_writel(opaque, addr, val); 3290 break; 3291 } 3292 } 3293 3294 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, 3295 unsigned size) 3296 { 3297 switch (size) { 3298 case 1: 3299 return rtl8139_io_readb(opaque, addr); 3300 case 2: 3301 return rtl8139_io_readw(opaque, addr); 3302 case 4: 3303 return rtl8139_io_readl(opaque, addr); 3304 } 3305 3306 return -1; 3307 } 3308 3309 static const MemoryRegionOps rtl8139_io_ops = { 3310 .read = rtl8139_ioport_read, 3311 .write = rtl8139_ioport_write, 3312 .impl = { 3313 .min_access_size = 1, 3314 .max_access_size = 4, 3315 }, 3316 .endianness = DEVICE_LITTLE_ENDIAN, 3317 }; 3318 3319 static void rtl8139_timer(void *opaque) 3320 { 3321 RTL8139State *s = opaque; 3322 3323 if (!s->clock_enabled) 3324 { 3325 DPRINTF(">>> timer: clock is not running\n"); 3326 return; 3327 } 3328 3329 s->IntrStatus |= PCSTimeout; 3330 rtl8139_update_irq(s); 3331 rtl8139_set_next_tctr_time(s); 3332 } 3333 3334 static void pci_rtl8139_uninit(PCIDevice *dev) 3335 { 3336 RTL8139State *s = RTL8139(dev); 3337 3338 g_free(s->cplus_txbuffer); 3339 s->cplus_txbuffer = NULL; 3340 timer_free(s->timer); 3341 qemu_del_nic(s->nic); 3342 } 3343 3344 static void rtl8139_set_link_status(NetClientState *nc) 3345 { 3346 RTL8139State *s = qemu_get_nic_opaque(nc); 3347 3348 if (nc->link_down) { 3349 s->BasicModeStatus &= ~0x04; 3350 } else { 3351 s->BasicModeStatus |= 0x04; 3352 } 3353 3354 s->IntrStatus |= RxUnderrun; 3355 rtl8139_update_irq(s); 3356 } 3357 3358 static NetClientInfo net_rtl8139_info = { 3359 .type = NET_CLIENT_DRIVER_NIC, 3360 .size = sizeof(NICState), 3361 .can_receive = rtl8139_can_receive, 3362 .receive = rtl8139_receive, 3363 .link_status_changed = rtl8139_set_link_status, 3364 }; 3365 3366 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) 3367 { 3368 RTL8139State *s = RTL8139(dev); 3369 DeviceState *d = DEVICE(dev); 3370 uint8_t *pci_conf; 3371 3372 pci_conf = dev->config; 3373 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3374 /* TODO: start of capability list, but no capability 3375 * list bit in status register, and offset 0xdc seems unused. */ 3376 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3377 3378 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, 3379 "rtl8139", 0x100); 3380 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io, 3381 0, 0x100); 3382 3383 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3384 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3385 3386 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3387 3388 /* prepare eeprom */ 3389 s->eeprom.contents[0] = 0x8129; 3390 #if 1 3391 /* PCI vendor and device ID should be mirrored here */ 3392 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3393 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3394 #endif 3395 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3396 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3397 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3398 3399 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3400 object_get_typename(OBJECT(dev)), d->id, s); 3401 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 3402 3403 s->cplus_txbuffer = NULL; 3404 s->cplus_txbuffer_len = 0; 3405 s->cplus_txbuffer_offset = 0; 3406 3407 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); 3408 } 3409 3410 static void rtl8139_instance_init(Object *obj) 3411 { 3412 RTL8139State *s = RTL8139(obj); 3413 3414 device_add_bootindex_property(obj, &s->conf.bootindex, 3415 "bootindex", "/ethernet-phy@0", 3416 DEVICE(obj)); 3417 } 3418 3419 static Property rtl8139_properties[] = { 3420 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3421 DEFINE_PROP_END_OF_LIST(), 3422 }; 3423 3424 static void rtl8139_class_init(ObjectClass *klass, void *data) 3425 { 3426 DeviceClass *dc = DEVICE_CLASS(klass); 3427 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3428 3429 k->realize = pci_rtl8139_realize; 3430 k->exit = pci_rtl8139_uninit; 3431 k->romfile = "efi-rtl8139.rom"; 3432 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3433 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3434 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3435 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3436 dc->reset = rtl8139_reset; 3437 dc->vmsd = &vmstate_rtl8139; 3438 device_class_set_props(dc, rtl8139_properties); 3439 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3440 } 3441 3442 static const TypeInfo rtl8139_info = { 3443 .name = TYPE_RTL8139, 3444 .parent = TYPE_PCI_DEVICE, 3445 .instance_size = sizeof(RTL8139State), 3446 .class_init = rtl8139_class_init, 3447 .instance_init = rtl8139_instance_init, 3448 .interfaces = (InterfaceInfo[]) { 3449 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 3450 { }, 3451 }, 3452 }; 3453 3454 static void rtl8139_register_types(void) 3455 { 3456 type_register_static(&rtl8139_info); 3457 } 3458 3459 type_init(rtl8139_register_types)