malta.c (48768B)
1 /* 2 * QEMU Malta board support 3 * 4 * Copyright (c) 2006 Aurelien Jarno 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/bitops.h" 28 #include "qemu/datadir.h" 29 #include "qemu/guest-random.h" 30 #include "hw/clock.h" 31 #include "hw/southbridge/piix.h" 32 #include "hw/isa/superio.h" 33 #include "hw/char/serial.h" 34 #include "net/net.h" 35 #include "hw/boards.h" 36 #include "hw/i2c/smbus_eeprom.h" 37 #include "hw/block/flash.h" 38 #include "hw/mips/mips.h" 39 #include "hw/mips/bootloader.h" 40 #include "hw/mips/cpudevs.h" 41 #include "hw/pci/pci.h" 42 #include "qemu/log.h" 43 #include "hw/mips/bios.h" 44 #include "hw/ide/pci.h" 45 #include "hw/irq.h" 46 #include "hw/loader.h" 47 #include "elf.h" 48 #include "qom/object.h" 49 #include "hw/sysbus.h" /* SysBusDevice */ 50 #include "qemu/host-utils.h" 51 #include "sysemu/qtest.h" 52 #include "sysemu/reset.h" 53 #include "sysemu/runstate.h" 54 #include "qapi/error.h" 55 #include "qemu/error-report.h" 56 #include "hw/misc/empty_slot.h" 57 #include "sysemu/kvm.h" 58 #include "semihosting/semihost.h" 59 #include "hw/mips/cps.h" 60 #include "hw/qdev-clock.h" 61 62 #define ENVP_PADDR 0x2000 63 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) 64 #define ENVP_NB_ENTRIES 16 65 #define ENVP_ENTRY_SIZE 256 66 67 /* Hardware addresses */ 68 #define FLASH_ADDRESS 0x1e000000ULL 69 #define FPGA_ADDRESS 0x1f000000ULL 70 #define RESET_ADDRESS 0x1fc00000ULL 71 72 #define FLASH_SIZE 0x400000 73 74 typedef struct { 75 MemoryRegion iomem; 76 MemoryRegion iomem_lo; /* 0 - 0x900 */ 77 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ 78 uint32_t leds; 79 uint32_t brk; 80 uint32_t gpout; 81 uint32_t i2cin; 82 uint32_t i2coe; 83 uint32_t i2cout; 84 uint32_t i2csel; 85 CharBackend display; 86 char display_text[9]; 87 SerialMM *uart; 88 bool display_inited; 89 } MaltaFPGAState; 90 91 #define TYPE_MIPS_MALTA "mips-malta" 92 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) 93 94 struct MaltaState { 95 SysBusDevice parent_obj; 96 97 Clock *cpuclk; 98 MIPSCPSState cps; 99 }; 100 101 static struct _loaderparams { 102 int ram_size, ram_low_size; 103 const char *kernel_filename; 104 const char *kernel_cmdline; 105 const char *initrd_filename; 106 } loaderparams; 107 108 /* Malta FPGA */ 109 static void malta_fpga_update_display(void *opaque) 110 { 111 char leds_text[9]; 112 int i; 113 MaltaFPGAState *s = opaque; 114 115 for (i = 7 ; i >= 0 ; i--) { 116 if (s->leds & (1 << i)) { 117 leds_text[i] = '#'; 118 } else { 119 leds_text[i] = ' '; 120 } 121 } 122 leds_text[8] = '\0'; 123 124 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", 125 leds_text); 126 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", 127 s->display_text); 128 } 129 130 /* 131 * EEPROM 24C01 / 24C02 emulation. 132 * 133 * Emulation for serial EEPROMs: 134 * 24C01 - 1024 bit (128 x 8) 135 * 24C02 - 2048 bit (256 x 8) 136 * 137 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. 138 */ 139 140 #if defined(DEBUG) 141 # define logout(fmt, ...) \ 142 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) 143 #else 144 # define logout(fmt, ...) ((void)0) 145 #endif 146 147 struct _eeprom24c0x_t { 148 uint8_t tick; 149 uint8_t address; 150 uint8_t command; 151 uint8_t ack; 152 uint8_t scl; 153 uint8_t sda; 154 uint8_t data; 155 /* uint16_t size; */ 156 uint8_t contents[256]; 157 }; 158 159 typedef struct _eeprom24c0x_t eeprom24c0x_t; 160 161 static eeprom24c0x_t spd_eeprom = { 162 .contents = { 163 /* 00000000: */ 164 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, 165 /* 00000008: */ 166 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, 167 /* 00000010: */ 168 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 169 /* 00000018: */ 170 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, 171 /* 00000020: */ 172 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 173 /* 00000028: */ 174 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 175 /* 00000030: */ 176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 177 /* 00000038: */ 178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, 179 /* 00000040: */ 180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 181 /* 00000048: */ 182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 183 /* 00000050: */ 184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 185 /* 00000058: */ 186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 187 /* 00000060: */ 188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 189 /* 00000068: */ 190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 191 /* 00000070: */ 192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 193 /* 00000078: */ 194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, 195 }, 196 }; 197 198 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) 199 { 200 enum { SDR = 0x4, DDR2 = 0x8 } type; 201 uint8_t *spd = spd_eeprom.contents; 202 uint8_t nbanks = 0; 203 uint16_t density = 0; 204 int i; 205 206 /* work in terms of MB */ 207 ram_size /= MiB; 208 209 while ((ram_size >= 4) && (nbanks <= 2)) { 210 int sz_log2 = MIN(31 - clz32(ram_size), 14); 211 nbanks++; 212 density |= 1 << (sz_log2 - 2); 213 ram_size -= 1 << sz_log2; 214 } 215 216 /* split to 2 banks if possible */ 217 if ((nbanks == 1) && (density > 1)) { 218 nbanks++; 219 density >>= 1; 220 } 221 222 if (density & 0xff00) { 223 density = (density & 0xe0) | ((density >> 8) & 0x1f); 224 type = DDR2; 225 } else if (!(density & 0x1f)) { 226 type = DDR2; 227 } else { 228 type = SDR; 229 } 230 231 if (ram_size) { 232 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" 233 " of SDRAM", ram_size); 234 } 235 236 /* fill in SPD memory information */ 237 spd[2] = type; 238 spd[5] = nbanks; 239 spd[31] = density; 240 241 /* checksum */ 242 spd[63] = 0; 243 for (i = 0; i < 63; i++) { 244 spd[63] += spd[i]; 245 } 246 247 /* copy for SMBUS */ 248 memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); 249 } 250 251 static void generate_eeprom_serial(uint8_t *eeprom) 252 { 253 int i, pos = 0; 254 uint8_t mac[6] = { 0x00 }; 255 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; 256 257 /* version */ 258 eeprom[pos++] = 0x01; 259 260 /* count */ 261 eeprom[pos++] = 0x02; 262 263 /* MAC address */ 264 eeprom[pos++] = 0x01; /* MAC */ 265 eeprom[pos++] = 0x06; /* length */ 266 memcpy(&eeprom[pos], mac, sizeof(mac)); 267 pos += sizeof(mac); 268 269 /* serial number */ 270 eeprom[pos++] = 0x02; /* serial */ 271 eeprom[pos++] = 0x05; /* length */ 272 memcpy(&eeprom[pos], sn, sizeof(sn)); 273 pos += sizeof(sn); 274 275 /* checksum */ 276 eeprom[pos] = 0; 277 for (i = 0; i < pos; i++) { 278 eeprom[pos] += eeprom[i]; 279 } 280 } 281 282 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) 283 { 284 logout("%u: scl = %u, sda = %u, data = 0x%02x\n", 285 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); 286 return eeprom->sda; 287 } 288 289 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) 290 { 291 if (eeprom->scl && scl && (eeprom->sda != sda)) { 292 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", 293 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, 294 sda ? "stop" : "start"); 295 if (!sda) { 296 eeprom->tick = 1; 297 eeprom->command = 0; 298 } 299 } else if (eeprom->tick == 0 && !eeprom->ack) { 300 /* Waiting for start. */ 301 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", 302 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 303 } else if (!eeprom->scl && scl) { 304 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", 305 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); 306 if (eeprom->ack) { 307 logout("\ti2c ack bit = 0\n"); 308 sda = 0; 309 eeprom->ack = 0; 310 } else if (eeprom->sda == sda) { 311 uint8_t bit = (sda != 0); 312 logout("\ti2c bit = %d\n", bit); 313 if (eeprom->tick < 9) { 314 eeprom->command <<= 1; 315 eeprom->command += bit; 316 eeprom->tick++; 317 if (eeprom->tick == 9) { 318 logout("\tcommand 0x%04x, %s\n", eeprom->command, 319 bit ? "read" : "write"); 320 eeprom->ack = 1; 321 } 322 } else if (eeprom->tick < 17) { 323 if (eeprom->command & 1) { 324 sda = ((eeprom->data & 0x80) != 0); 325 } 326 eeprom->address <<= 1; 327 eeprom->address += bit; 328 eeprom->tick++; 329 eeprom->data <<= 1; 330 if (eeprom->tick == 17) { 331 eeprom->data = eeprom->contents[eeprom->address]; 332 logout("\taddress 0x%04x, data 0x%02x\n", 333 eeprom->address, eeprom->data); 334 eeprom->ack = 1; 335 eeprom->tick = 0; 336 } 337 } else if (eeprom->tick >= 17) { 338 sda = 0; 339 } 340 } else { 341 logout("\tsda changed with raising scl\n"); 342 } 343 } else { 344 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, 345 scl, eeprom->sda, sda); 346 } 347 eeprom->scl = scl; 348 eeprom->sda = sda; 349 } 350 351 static uint64_t malta_fpga_read(void *opaque, hwaddr addr, 352 unsigned size) 353 { 354 MaltaFPGAState *s = opaque; 355 uint32_t val = 0; 356 uint32_t saddr; 357 358 saddr = (addr & 0xfffff); 359 360 switch (saddr) { 361 362 /* SWITCH Register */ 363 case 0x00200: 364 val = 0x00000000; 365 break; 366 367 /* STATUS Register */ 368 case 0x00208: 369 #if TARGET_BIG_ENDIAN 370 val = 0x00000012; 371 #else 372 val = 0x00000010; 373 #endif 374 break; 375 376 /* JMPRS Register */ 377 case 0x00210: 378 val = 0x00; 379 break; 380 381 /* LEDBAR Register */ 382 case 0x00408: 383 val = s->leds; 384 break; 385 386 /* BRKRES Register */ 387 case 0x00508: 388 val = s->brk; 389 break; 390 391 /* UART Registers are handled directly by the serial device */ 392 393 /* GPOUT Register */ 394 case 0x00a00: 395 val = s->gpout; 396 break; 397 398 /* XXX: implement a real I2C controller */ 399 400 /* GPINP Register */ 401 case 0x00a08: 402 /* IN = OUT until a real I2C control is implemented */ 403 if (s->i2csel) { 404 val = s->i2cout; 405 } else { 406 val = 0x00; 407 } 408 break; 409 410 /* I2CINP Register */ 411 case 0x00b00: 412 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); 413 break; 414 415 /* I2COE Register */ 416 case 0x00b08: 417 val = s->i2coe; 418 break; 419 420 /* I2COUT Register */ 421 case 0x00b10: 422 val = s->i2cout; 423 break; 424 425 /* I2CSEL Register */ 426 case 0x00b18: 427 val = s->i2csel; 428 break; 429 430 default: 431 qemu_log_mask(LOG_GUEST_ERROR, 432 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", 433 addr); 434 break; 435 } 436 return val; 437 } 438 439 static void malta_fpga_write(void *opaque, hwaddr addr, 440 uint64_t val, unsigned size) 441 { 442 MaltaFPGAState *s = opaque; 443 uint32_t saddr; 444 445 saddr = (addr & 0xfffff); 446 447 switch (saddr) { 448 449 /* SWITCH Register */ 450 case 0x00200: 451 break; 452 453 /* JMPRS Register */ 454 case 0x00210: 455 break; 456 457 /* LEDBAR Register */ 458 case 0x00408: 459 s->leds = val & 0xff; 460 malta_fpga_update_display(s); 461 break; 462 463 /* ASCIIWORD Register */ 464 case 0x00410: 465 snprintf(s->display_text, 9, "%08X", (uint32_t)val); 466 malta_fpga_update_display(s); 467 break; 468 469 /* ASCIIPOS0 to ASCIIPOS7 Registers */ 470 case 0x00418: 471 case 0x00420: 472 case 0x00428: 473 case 0x00430: 474 case 0x00438: 475 case 0x00440: 476 case 0x00448: 477 case 0x00450: 478 s->display_text[(saddr - 0x00418) >> 3] = (char) val; 479 malta_fpga_update_display(s); 480 break; 481 482 /* SOFTRES Register */ 483 case 0x00500: 484 if (val == 0x42) { 485 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 486 } 487 break; 488 489 /* BRKRES Register */ 490 case 0x00508: 491 s->brk = val & 0xff; 492 break; 493 494 /* UART Registers are handled directly by the serial device */ 495 496 /* GPOUT Register */ 497 case 0x00a00: 498 s->gpout = val & 0xff; 499 break; 500 501 /* I2COE Register */ 502 case 0x00b08: 503 s->i2coe = val & 0x03; 504 break; 505 506 /* I2COUT Register */ 507 case 0x00b10: 508 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); 509 s->i2cout = val; 510 break; 511 512 /* I2CSEL Register */ 513 case 0x00b18: 514 s->i2csel = val & 0x01; 515 break; 516 517 default: 518 qemu_log_mask(LOG_GUEST_ERROR, 519 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", 520 addr); 521 break; 522 } 523 } 524 525 static const MemoryRegionOps malta_fpga_ops = { 526 .read = malta_fpga_read, 527 .write = malta_fpga_write, 528 .endianness = DEVICE_NATIVE_ENDIAN, 529 }; 530 531 static void malta_fpga_reset(void *opaque) 532 { 533 MaltaFPGAState *s = opaque; 534 535 s->leds = 0x00; 536 s->brk = 0x0a; 537 s->gpout = 0x00; 538 s->i2cin = 0x3; 539 s->i2coe = 0x0; 540 s->i2cout = 0x3; 541 s->i2csel = 0x1; 542 543 s->display_text[8] = '\0'; 544 snprintf(s->display_text, 9, " "); 545 } 546 547 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) 548 { 549 MaltaFPGAState *s = opaque; 550 551 if (event == CHR_EVENT_OPENED && !s->display_inited) { 552 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); 553 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 554 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 555 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 556 qemu_chr_fe_printf(&s->display, "\n"); 557 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); 558 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 559 qemu_chr_fe_printf(&s->display, "+ +\r\n"); 560 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); 561 s->display_inited = true; 562 } 563 } 564 565 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, 566 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) 567 { 568 MaltaFPGAState *s; 569 Chardev *chr; 570 571 s = g_new0(MaltaFPGAState, 1); 572 573 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, 574 "malta-fpga", 0x100000); 575 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", 576 &s->iomem, 0, 0x900); 577 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", 578 &s->iomem, 0xa00, 0x100000 - 0xa00); 579 580 memory_region_add_subregion(address_space, base, &s->iomem_lo); 581 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); 582 583 chr = qemu_chr_new("fpga", "vc:320x200", NULL); 584 qemu_chr_fe_init(&s->display, chr, NULL); 585 qemu_chr_fe_set_handlers(&s->display, NULL, NULL, 586 malta_fgpa_display_event, NULL, s, NULL, true); 587 588 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, 589 230400, uart_chr, DEVICE_NATIVE_ENDIAN); 590 591 malta_fpga_reset(s); 592 qemu_register_reset(malta_fpga_reset, s); 593 594 return s; 595 } 596 597 /* Network support */ 598 static void network_init(PCIBus *pci_bus) 599 { 600 int i; 601 602 for (i = 0; i < nb_nics; i++) { 603 NICInfo *nd = &nd_table[i]; 604 const char *default_devaddr = NULL; 605 606 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0)) 607 /* The malta board has a PCNet card using PCI SLOT 11 */ 608 default_devaddr = "0b"; 609 610 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr); 611 } 612 } 613 614 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, 615 uint64_t kernel_entry) 616 { 617 uint16_t *p; 618 619 /* Small bootloader */ 620 p = (uint16_t *)base; 621 622 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) 623 #define NM_HI2(VAL) \ 624 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1)) 625 #define NM_LO(VAL) ((VAL) & 0xfff) 626 627 stw_p(p++, 0x2800); stw_p(p++, 0x001c); 628 /* bc to_here */ 629 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 630 /* nop */ 631 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 632 /* nop */ 633 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 634 /* nop */ 635 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 636 /* nop */ 637 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 638 /* nop */ 639 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 640 /* nop */ 641 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 642 /* nop */ 643 644 /* to_here: */ 645 if (semihosting_get_argc()) { 646 /* Preserve a0 content as arguments have been passed */ 647 stw_p(p++, 0x8000); stw_p(p++, 0xc000); 648 /* nop */ 649 } else { 650 stw_p(p++, 0x0080); stw_p(p++, 0x0002); 651 /* li a0,2 */ 652 } 653 654 stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64)); 655 656 stw_p(p++, NM_HI2(ENVP_VADDR - 64)); 657 /* lui sp,%hi(ENVP_VADDR - 64) */ 658 659 stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64)); 660 /* ori sp,sp,%lo(ENVP_VADDR - 64) */ 661 662 stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR)); 663 664 stw_p(p++, NM_HI2(ENVP_VADDR)); 665 /* lui a1,%hi(ENVP_VADDR) */ 666 667 stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR)); 668 /* ori a1,a1,%lo(ENVP_VADDR) */ 669 670 stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8)); 671 672 stw_p(p++, NM_HI2(ENVP_VADDR + 8)); 673 /* lui a2,%hi(ENVP_VADDR + 8) */ 674 675 stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8)); 676 /* ori a2,a2,%lo(ENVP_VADDR + 8) */ 677 678 stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); 679 680 stw_p(p++, NM_HI2(loaderparams.ram_low_size)); 681 /* lui a3,%hi(loaderparams.ram_low_size) */ 682 683 stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); 684 /* ori a3,a3,%lo(loaderparams.ram_low_size) */ 685 686 /* 687 * Load BAR registers as done by YAMON: 688 * 689 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff 690 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000 691 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000 692 * 693 */ 694 stw_p(p++, 0xe040); stw_p(p++, 0x0681); 695 /* lui t1, %hi(0xb4000000) */ 696 697 #if TARGET_BIG_ENDIAN 698 699 stw_p(p++, 0xe020); stw_p(p++, 0x0be1); 700 /* lui t0, %hi(0xdf000000) */ 701 702 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */ 703 stw_p(p++, 0x8422); stw_p(p++, 0x9068); 704 /* sw t0, 0x68(t1) */ 705 706 stw_p(p++, 0xe040); stw_p(p++, 0x077d); 707 /* lui t1, %hi(0xbbe00000) */ 708 709 stw_p(p++, 0xe020); stw_p(p++, 0x0801); 710 /* lui t0, %hi(0xc0000000) */ 711 712 /* 0x48 corresponds to GT_PCI0IOLD */ 713 stw_p(p++, 0x8422); stw_p(p++, 0x9048); 714 /* sw t0, 0x48(t1) */ 715 716 stw_p(p++, 0xe020); stw_p(p++, 0x0800); 717 /* lui t0, %hi(0x40000000) */ 718 719 /* 0x50 corresponds to GT_PCI0IOHD */ 720 stw_p(p++, 0x8422); stw_p(p++, 0x9050); 721 /* sw t0, 0x50(t1) */ 722 723 stw_p(p++, 0xe020); stw_p(p++, 0x0001); 724 /* lui t0, %hi(0x80000000) */ 725 726 /* 0x58 corresponds to GT_PCI0M0LD */ 727 stw_p(p++, 0x8422); stw_p(p++, 0x9058); 728 /* sw t0, 0x58(t1) */ 729 730 stw_p(p++, 0xe020); stw_p(p++, 0x07e0); 731 /* lui t0, %hi(0x3f000000) */ 732 733 /* 0x60 corresponds to GT_PCI0M0HD */ 734 stw_p(p++, 0x8422); stw_p(p++, 0x9060); 735 /* sw t0, 0x60(t1) */ 736 737 stw_p(p++, 0xe020); stw_p(p++, 0x0821); 738 /* lui t0, %hi(0xc1000000) */ 739 740 /* 0x80 corresponds to GT_PCI0M1LD */ 741 stw_p(p++, 0x8422); stw_p(p++, 0x9080); 742 /* sw t0, 0x80(t1) */ 743 744 stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); 745 /* lui t0, %hi(0x5e000000) */ 746 747 #else 748 749 stw_p(p++, 0x0020); stw_p(p++, 0x00df); 750 /* addiu[32] t0, $0, 0xdf */ 751 752 /* 0x68 corresponds to GT_ISD */ 753 stw_p(p++, 0x8422); stw_p(p++, 0x9068); 754 /* sw t0, 0x68(t1) */ 755 756 /* Use kseg2 remapped address 0x1be00000 */ 757 stw_p(p++, 0xe040); stw_p(p++, 0x077d); 758 /* lui t1, %hi(0xbbe00000) */ 759 760 stw_p(p++, 0x0020); stw_p(p++, 0x00c0); 761 /* addiu[32] t0, $0, 0xc0 */ 762 763 /* 0x48 corresponds to GT_PCI0IOLD */ 764 stw_p(p++, 0x8422); stw_p(p++, 0x9048); 765 /* sw t0, 0x48(t1) */ 766 767 stw_p(p++, 0x0020); stw_p(p++, 0x0040); 768 /* addiu[32] t0, $0, 0x40 */ 769 770 /* 0x50 corresponds to GT_PCI0IOHD */ 771 stw_p(p++, 0x8422); stw_p(p++, 0x9050); 772 /* sw t0, 0x50(t1) */ 773 774 stw_p(p++, 0x0020); stw_p(p++, 0x0080); 775 /* addiu[32] t0, $0, 0x80 */ 776 777 /* 0x58 corresponds to GT_PCI0M0LD */ 778 stw_p(p++, 0x8422); stw_p(p++, 0x9058); 779 /* sw t0, 0x58(t1) */ 780 781 stw_p(p++, 0x0020); stw_p(p++, 0x003f); 782 /* addiu[32] t0, $0, 0x3f */ 783 784 /* 0x60 corresponds to GT_PCI0M0HD */ 785 stw_p(p++, 0x8422); stw_p(p++, 0x9060); 786 /* sw t0, 0x60(t1) */ 787 788 stw_p(p++, 0x0020); stw_p(p++, 0x00c1); 789 /* addiu[32] t0, $0, 0xc1 */ 790 791 /* 0x80 corresponds to GT_PCI0M1LD */ 792 stw_p(p++, 0x8422); stw_p(p++, 0x9080); 793 /* sw t0, 0x80(t1) */ 794 795 stw_p(p++, 0x0020); stw_p(p++, 0x005e); 796 /* addiu[32] t0, $0, 0x5e */ 797 798 #endif 799 800 /* 0x88 corresponds to GT_PCI0M1HD */ 801 stw_p(p++, 0x8422); stw_p(p++, 0x9088); 802 /* sw t0, 0x88(t1) */ 803 804 stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); 805 806 stw_p(p++, NM_HI2(kernel_entry)); 807 /* lui t9,%hi(kernel_entry) */ 808 809 stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); 810 /* ori t9,t9,%lo(kernel_entry) */ 811 812 stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); 813 /* jalrc t8 */ 814 } 815 816 /* 817 * ROM and pseudo bootloader 818 * 819 * The following code implements a very very simple bootloader. It first 820 * loads the registers a0 to a3 to the values expected by the OS, and 821 * then jump at the kernel address. 822 * 823 * The bootloader should pass the locations of the kernel arguments and 824 * environment variables tables. Those tables contain the 32-bit address 825 * of NULL terminated strings. The environment variables table should be 826 * terminated by a NULL address. 827 * 828 * For a simpler implementation, the number of kernel arguments is fixed 829 * to two (the name of the kernel and the command line), and the two 830 * tables are actually the same one. 831 * 832 * The registers a0 to a3 should contain the following values: 833 * a0 - number of kernel arguments 834 * a1 - 32-bit address of the kernel arguments table 835 * a2 - 32-bit address of the environment variables table 836 * a3 - RAM size in bytes 837 */ 838 static void write_bootloader(uint8_t *base, uint64_t run_addr, 839 uint64_t kernel_entry) 840 { 841 uint32_t *p; 842 843 /* Small bootloader */ 844 p = (uint32_t *)base; 845 846 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ 847 ((run_addr + 0x580) & 0x0fffffff) >> 2); 848 stl_p(p++, 0x00000000); /* nop */ 849 850 /* YAMON service vector */ 851 stl_p(base + 0x500, run_addr + 0x0580); /* start: */ 852 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ 853 stl_p(base + 0x520, run_addr + 0x0580); /* start: */ 854 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ 855 stl_p(base + 0x534, run_addr + 0x0808); /* print: */ 856 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ 857 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ 858 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ 859 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ 860 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ 861 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ 862 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ 863 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ 864 865 866 /* Second part of the bootloader */ 867 p = (uint32_t *) (base + 0x580); 868 869 /* 870 * Load BAR registers as done by YAMON: 871 * 872 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff 873 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000 874 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000 875 * 876 */ 877 878 /* Bus endianess is always reversed */ 879 #if TARGET_BIG_ENDIAN 880 #define cpu_to_gt32 cpu_to_le32 881 #else 882 #define cpu_to_gt32 cpu_to_be32 883 #endif 884 885 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 886 bl_gen_write_u32(&p, /* GT_ISD */ 887 cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), 888 cpu_to_gt32(0x1be00000 << 3)); 889 890 /* setup MEM-to-PCI0 mapping */ 891 /* setup PCI0 io window to 0x18000000-0x181fffff */ 892 bl_gen_write_u32(&p, /* GT_PCI0IOLD */ 893 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), 894 cpu_to_gt32(0x18000000 << 3)); 895 bl_gen_write_u32(&p, /* GT_PCI0IOHD */ 896 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), 897 cpu_to_gt32(0x08000000 << 3)); 898 /* setup PCI0 mem windows */ 899 bl_gen_write_u32(&p, /* GT_PCI0M0LD */ 900 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), 901 cpu_to_gt32(0x10000000 << 3)); 902 bl_gen_write_u32(&p, /* GT_PCI0M0HD */ 903 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), 904 cpu_to_gt32(0x07e00000 << 3)); 905 906 bl_gen_write_u32(&p, /* GT_PCI0M1LD */ 907 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), 908 cpu_to_gt32(0x18200000 << 3)); 909 bl_gen_write_u32(&p, /* GT_PCI0M1HD */ 910 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), 911 cpu_to_gt32(0x0bc00000 << 3)); 912 913 #undef cpu_to_gt32 914 915 bl_gen_jump_kernel(&p, 916 true, ENVP_VADDR - 64, 917 /* 918 * If semihosting is used, arguments have already been 919 * passed, so we preserve $a0. 920 */ 921 !semihosting_get_argc(), 2, 922 true, ENVP_VADDR, 923 true, ENVP_VADDR + 8, 924 true, loaderparams.ram_low_size, 925 kernel_entry); 926 927 /* YAMON subroutines */ 928 p = (uint32_t *) (base + 0x800); 929 stl_p(p++, 0x03e00009); /* jalr ra */ 930 stl_p(p++, 0x24020000); /* li v0,0 */ 931 /* 808 YAMON print */ 932 stl_p(p++, 0x03e06821); /* move t5,ra */ 933 stl_p(p++, 0x00805821); /* move t3,a0 */ 934 stl_p(p++, 0x00a05021); /* move t2,a1 */ 935 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 936 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 937 stl_p(p++, 0x10800005); /* beqz a0,834 */ 938 stl_p(p++, 0x00000000); /* nop */ 939 stl_p(p++, 0x0ff0021c); /* jal 870 */ 940 stl_p(p++, 0x00000000); /* nop */ 941 stl_p(p++, 0x1000fff9); /* b 814 */ 942 stl_p(p++, 0x00000000); /* nop */ 943 stl_p(p++, 0x01a00009); /* jalr t5 */ 944 stl_p(p++, 0x01602021); /* move a0,t3 */ 945 /* 0x83c YAMON print_count */ 946 stl_p(p++, 0x03e06821); /* move t5,ra */ 947 stl_p(p++, 0x00805821); /* move t3,a0 */ 948 stl_p(p++, 0x00a05021); /* move t2,a1 */ 949 stl_p(p++, 0x00c06021); /* move t4,a2 */ 950 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ 951 stl_p(p++, 0x0ff0021c); /* jal 870 */ 952 stl_p(p++, 0x00000000); /* nop */ 953 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ 954 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ 955 stl_p(p++, 0x1580fffa); /* bnez t4,84c */ 956 stl_p(p++, 0x00000000); /* nop */ 957 stl_p(p++, 0x01a00009); /* jalr t5 */ 958 stl_p(p++, 0x01602021); /* move a0,t3 */ 959 /* 0x870 */ 960 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ 961 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ 962 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ 963 stl_p(p++, 0x00000000); /* nop */ 964 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ 965 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ 966 stl_p(p++, 0x00000000); /* nop */ 967 stl_p(p++, 0x03e00009); /* jalr ra */ 968 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ 969 970 } 971 972 static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index, 973 const char *string, ...) 974 { 975 va_list ap; 976 uint32_t table_addr; 977 978 if (index >= ENVP_NB_ENTRIES) { 979 return; 980 } 981 982 if (string == NULL) { 983 prom_buf[index] = 0; 984 return; 985 } 986 987 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; 988 prom_buf[index] = tswap32(ENVP_VADDR + table_addr); 989 990 va_start(ap, string); 991 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); 992 va_end(ap); 993 } 994 995 static void reinitialize_rng_seed(void *opaque) 996 { 997 char *rng_seed_hex = opaque; 998 uint8_t rng_seed[32]; 999 1000 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1001 for (size_t i = 0; i < sizeof(rng_seed); ++i) { 1002 sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]); 1003 } 1004 } 1005 1006 /* Kernel */ 1007 static uint64_t load_kernel(void) 1008 { 1009 uint64_t kernel_entry, kernel_high, initrd_size; 1010 long kernel_size; 1011 ram_addr_t initrd_offset; 1012 int big_endian; 1013 uint32_t *prom_buf; 1014 long prom_size; 1015 int prom_index = 0; 1016 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); 1017 uint8_t rng_seed[32]; 1018 char rng_seed_hex[sizeof(rng_seed) * 2 + 1]; 1019 size_t rng_seed_prom_offset; 1020 1021 #if TARGET_BIG_ENDIAN 1022 big_endian = 1; 1023 #else 1024 big_endian = 0; 1025 #endif 1026 1027 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 1028 cpu_mips_kseg0_to_phys, NULL, 1029 &kernel_entry, NULL, 1030 &kernel_high, NULL, big_endian, EM_MIPS, 1031 1, 0); 1032 if (kernel_size < 0) { 1033 error_report("could not load kernel '%s': %s", 1034 loaderparams.kernel_filename, 1035 load_elf_strerror(kernel_size)); 1036 exit(1); 1037 } 1038 1039 /* Check where the kernel has been linked */ 1040 if (kernel_entry & 0x80000000ll) { 1041 if (kvm_enabled()) { 1042 error_report("KVM guest kernels must be linked in useg. " 1043 "Did you forget to enable CONFIG_KVM_GUEST?"); 1044 exit(1); 1045 } 1046 1047 xlate_to_kseg0 = cpu_mips_phys_to_kseg0; 1048 } else { 1049 /* if kernel entry is in useg it is probably a KVM T&E kernel */ 1050 mips_um_ksegs_enable(); 1051 1052 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0; 1053 } 1054 1055 /* load initrd */ 1056 initrd_size = 0; 1057 initrd_offset = 0; 1058 if (loaderparams.initrd_filename) { 1059 initrd_size = get_image_size(loaderparams.initrd_filename); 1060 if (initrd_size > 0) { 1061 /* 1062 * The kernel allocates the bootmap memory in the low memory after 1063 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB 1064 * pages. 1065 */ 1066 initrd_offset = ROUND_UP(loaderparams.ram_low_size 1067 - (initrd_size + 128 * KiB), 1068 INITRD_PAGE_SIZE); 1069 if (kernel_high >= initrd_offset) { 1070 error_report("memory too small for initial ram disk '%s'", 1071 loaderparams.initrd_filename); 1072 exit(1); 1073 } 1074 initrd_size = load_image_targphys(loaderparams.initrd_filename, 1075 initrd_offset, 1076 loaderparams.ram_size - initrd_offset); 1077 } 1078 if (initrd_size == (target_ulong) -1) { 1079 error_report("could not load initial ram disk '%s'", 1080 loaderparams.initrd_filename); 1081 exit(1); 1082 } 1083 } 1084 1085 /* Setup prom parameters. */ 1086 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); 1087 prom_buf = g_malloc(prom_size); 1088 1089 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); 1090 if (initrd_size > 0) { 1091 prom_set(prom_buf, prom_index++, 1092 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", 1093 xlate_to_kseg0(NULL, initrd_offset), 1094 initrd_size, loaderparams.kernel_cmdline); 1095 } else { 1096 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); 1097 } 1098 1099 prom_set(prom_buf, prom_index++, "memsize"); 1100 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); 1101 1102 prom_set(prom_buf, prom_index++, "ememsize"); 1103 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); 1104 1105 prom_set(prom_buf, prom_index++, "modetty0"); 1106 prom_set(prom_buf, prom_index++, "38400n8r"); 1107 1108 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1109 for (size_t i = 0; i < sizeof(rng_seed); ++i) { 1110 sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]); 1111 } 1112 prom_set(prom_buf, prom_index++, "rngseed"); 1113 rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE + 1114 sizeof(uint32_t) * ENVP_NB_ENTRIES; 1115 prom_set(prom_buf, prom_index++, "%s", rng_seed_hex); 1116 1117 prom_set(prom_buf, prom_index++, NULL); 1118 1119 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); 1120 qemu_register_reset_nosnapshotload(reinitialize_rng_seed, 1121 rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset); 1122 1123 g_free(prom_buf); 1124 return kernel_entry; 1125 } 1126 1127 static void malta_mips_config(MIPSCPU *cpu) 1128 { 1129 MachineState *ms = MACHINE(qdev_get_machine()); 1130 unsigned int smp_cpus = ms->smp.cpus; 1131 CPUMIPSState *env = &cpu->env; 1132 CPUState *cs = CPU(cpu); 1133 1134 if (ase_mt_available(env)) { 1135 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 1136 CP0MVPC0_PTC, 8, 1137 smp_cpus * cs->nr_threads - 1); 1138 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, 1139 CP0MVPC0_PVPE, 4, smp_cpus - 1); 1140 } 1141 } 1142 1143 static void main_cpu_reset(void *opaque) 1144 { 1145 MIPSCPU *cpu = opaque; 1146 CPUMIPSState *env = &cpu->env; 1147 1148 cpu_reset(CPU(cpu)); 1149 1150 /* 1151 * The bootloader does not need to be rewritten as it is located in a 1152 * read only location. The kernel location and the arguments table 1153 * location does not change. 1154 */ 1155 if (loaderparams.kernel_filename) { 1156 env->CP0_Status &= ~(1 << CP0St_ERL); 1157 } 1158 1159 malta_mips_config(cpu); 1160 1161 if (kvm_enabled()) { 1162 /* Start running from the bootloader we wrote to end of RAM */ 1163 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size; 1164 } 1165 } 1166 1167 static void create_cpu_without_cps(MachineState *ms, MaltaState *s, 1168 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1169 { 1170 CPUMIPSState *env; 1171 MIPSCPU *cpu; 1172 int i; 1173 1174 for (i = 0; i < ms->smp.cpus; i++) { 1175 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); 1176 1177 /* Init internal devices */ 1178 cpu_mips_irq_init_cpu(cpu); 1179 cpu_mips_clock_init(cpu); 1180 qemu_register_reset(main_cpu_reset, cpu); 1181 } 1182 1183 cpu = MIPS_CPU(first_cpu); 1184 env = &cpu->env; 1185 *i8259_irq = env->irq[2]; 1186 *cbus_irq = env->irq[4]; 1187 } 1188 1189 static void create_cps(MachineState *ms, MaltaState *s, 1190 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1191 { 1192 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1193 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, 1194 &error_fatal); 1195 object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, 1196 &error_fatal); 1197 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); 1198 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1199 1200 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 1201 1202 *i8259_irq = get_cps_irq(&s->cps, 3); 1203 *cbus_irq = NULL; 1204 } 1205 1206 static void mips_create_cpu(MachineState *ms, MaltaState *s, 1207 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1208 { 1209 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { 1210 create_cps(ms, s, cbus_irq, i8259_irq); 1211 } else { 1212 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); 1213 } 1214 } 1215 1216 static 1217 void mips_malta_init(MachineState *machine) 1218 { 1219 ram_addr_t ram_size = machine->ram_size; 1220 ram_addr_t ram_low_size; 1221 const char *kernel_filename = machine->kernel_filename; 1222 const char *kernel_cmdline = machine->kernel_cmdline; 1223 const char *initrd_filename = machine->initrd_filename; 1224 char *filename; 1225 PFlashCFI01 *fl; 1226 MemoryRegion *system_memory = get_system_memory(); 1227 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); 1228 MemoryRegion *ram_low_postio; 1229 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); 1230 const size_t smbus_eeprom_size = 8 * 256; 1231 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); 1232 uint64_t kernel_entry, bootloader_run_addr; 1233 PCIBus *pci_bus; 1234 ISABus *isa_bus; 1235 qemu_irq cbus_irq, i8259_irq; 1236 I2CBus *smbus; 1237 DriveInfo *dinfo; 1238 int fl_idx = 0; 1239 int be; 1240 MaltaState *s; 1241 PCIDevice *piix4; 1242 DeviceState *dev; 1243 1244 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); 1245 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); 1246 1247 /* create CPU */ 1248 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); 1249 1250 /* allocate RAM */ 1251 if (ram_size > 2 * GiB) { 1252 error_report("Too much memory for this machine: %" PRId64 "MB," 1253 " maximum 2048MB", ram_size / MiB); 1254 exit(1); 1255 } 1256 1257 /* register RAM at high address where it is undisturbed by IO */ 1258 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 1259 1260 /* alias for pre IO hole access */ 1261 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", 1262 machine->ram, 0, MIN(ram_size, 256 * MiB)); 1263 memory_region_add_subregion(system_memory, 0, ram_low_preio); 1264 1265 /* alias for post IO hole access, if there is enough RAM */ 1266 if (ram_size > 512 * MiB) { 1267 ram_low_postio = g_new(MemoryRegion, 1); 1268 memory_region_init_alias(ram_low_postio, NULL, 1269 "mips_malta_low_postio.ram", 1270 machine->ram, 512 * MiB, 1271 ram_size - 512 * MiB); 1272 memory_region_add_subregion(system_memory, 512 * MiB, 1273 ram_low_postio); 1274 } 1275 1276 #if TARGET_BIG_ENDIAN 1277 be = 1; 1278 #else 1279 be = 0; 1280 #endif 1281 1282 /* FPGA */ 1283 1284 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ 1285 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); 1286 1287 /* Load firmware in flash / BIOS. */ 1288 dinfo = drive_get(IF_PFLASH, 0, fl_idx); 1289 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", 1290 FLASH_SIZE, 1291 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 1292 65536, 1293 4, 0x0000, 0x0000, 0x0000, 0x0000, be); 1294 bios = pflash_cfi01_get_memory(fl); 1295 fl_idx++; 1296 if (kernel_filename) { 1297 ram_low_size = MIN(ram_size, 256 * MiB); 1298 /* For KVM we reserve 1MB of RAM for running bootloader */ 1299 if (kvm_enabled()) { 1300 ram_low_size -= 0x100000; 1301 bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size); 1302 } else { 1303 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS); 1304 } 1305 1306 /* Write a small bootloader to the flash location. */ 1307 loaderparams.ram_size = ram_size; 1308 loaderparams.ram_low_size = ram_low_size; 1309 loaderparams.kernel_filename = kernel_filename; 1310 loaderparams.kernel_cmdline = kernel_cmdline; 1311 loaderparams.initrd_filename = initrd_filename; 1312 kernel_entry = load_kernel(); 1313 1314 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { 1315 write_bootloader(memory_region_get_ram_ptr(bios), 1316 bootloader_run_addr, kernel_entry); 1317 } else { 1318 write_bootloader_nanomips(memory_region_get_ram_ptr(bios), 1319 bootloader_run_addr, kernel_entry); 1320 } 1321 if (kvm_enabled()) { 1322 /* Write the bootloader code @ the end of RAM, 1MB reserved */ 1323 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + 1324 ram_low_size, 1325 bootloader_run_addr, kernel_entry); 1326 } 1327 } else { 1328 target_long bios_size = FLASH_SIZE; 1329 /* The flash region isn't executable from a KVM guest */ 1330 if (kvm_enabled()) { 1331 error_report("KVM enabled but no -kernel argument was specified. " 1332 "Booting from flash is not supported with KVM."); 1333 exit(1); 1334 } 1335 /* Load firmware from flash. */ 1336 if (!dinfo) { 1337 /* Load a BIOS image. */ 1338 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 1339 machine->firmware ?: BIOS_FILENAME); 1340 if (filename) { 1341 bios_size = load_image_targphys(filename, FLASH_ADDRESS, 1342 BIOS_SIZE); 1343 g_free(filename); 1344 } else { 1345 bios_size = -1; 1346 } 1347 if ((bios_size < 0 || bios_size > BIOS_SIZE) && 1348 machine->firmware && !qtest_enabled()) { 1349 error_report("Could not load MIPS bios '%s'", machine->firmware); 1350 exit(1); 1351 } 1352 } 1353 /* 1354 * In little endian mode the 32bit words in the bios are swapped, 1355 * a neat trick which allows bi-endian firmware. 1356 */ 1357 #if !TARGET_BIG_ENDIAN 1358 { 1359 uint32_t *end, *addr; 1360 const size_t swapsize = MIN(bios_size, 0x3e0000); 1361 addr = rom_ptr(FLASH_ADDRESS, swapsize); 1362 if (!addr) { 1363 addr = memory_region_get_ram_ptr(bios); 1364 } 1365 end = (void *)addr + swapsize; 1366 while (addr < end) { 1367 bswap32s(addr); 1368 addr++; 1369 } 1370 } 1371 #endif 1372 } 1373 1374 /* 1375 * Map the BIOS at a 2nd physical location, as on the real board. 1376 * Copy it so that we can patch in the MIPS revision, which cannot be 1377 * handled by an overlapping region as the resulting ROM code subpage 1378 * regions are not executable. 1379 */ 1380 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, 1381 &error_fatal); 1382 if (!rom_copy(memory_region_get_ram_ptr(bios_copy), 1383 FLASH_ADDRESS, BIOS_SIZE)) { 1384 memcpy(memory_region_get_ram_ptr(bios_copy), 1385 memory_region_get_ram_ptr(bios), BIOS_SIZE); 1386 } 1387 memory_region_set_readonly(bios_copy, true); 1388 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); 1389 1390 /* Board ID = 0x420 (Malta Board with CoreLV) */ 1391 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); 1392 1393 /* Northbridge */ 1394 dev = sysbus_create_simple("gt64120", -1, NULL); 1395 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 1396 /* 1397 * The whole address space decoded by the GT-64120A doesn't generate 1398 * exception when accessing invalid memory. Create an empty slot to 1399 * emulate this feature. 1400 */ 1401 empty_slot_init("GT64120", 0, 0x20000000); 1402 1403 /* Southbridge */ 1404 piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, 1405 TYPE_PIIX4_PCI_DEVICE); 1406 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); 1407 1408 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); 1409 pci_ide_create_devs(PCI_DEVICE(dev)); 1410 1411 /* Interrupt controller */ 1412 qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); 1413 1414 /* generate SPD EEPROM data */ 1415 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); 1416 smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); 1417 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); 1418 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); 1419 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); 1420 g_free(smbus_eeprom_buf); 1421 1422 /* Super I/O: SMS FDC37M817 */ 1423 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); 1424 1425 /* Network card */ 1426 network_init(pci_bus); 1427 1428 /* Optional PCI video card */ 1429 pci_vga_init(pci_bus); 1430 } 1431 1432 static void mips_malta_instance_init(Object *obj) 1433 { 1434 MaltaState *s = MIPS_MALTA(obj); 1435 1436 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); 1437 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ 1438 } 1439 1440 static const TypeInfo mips_malta_device = { 1441 .name = TYPE_MIPS_MALTA, 1442 .parent = TYPE_SYS_BUS_DEVICE, 1443 .instance_size = sizeof(MaltaState), 1444 .instance_init = mips_malta_instance_init, 1445 }; 1446 1447 GlobalProperty malta_compat[] = { 1448 { "PIIX4_PM", "memory-hotplug-support", "off" }, 1449 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 1450 { "PIIX4_PM", "acpi-root-pci-hotplug", "off" }, 1451 { "PIIX4_PM", "x-not-migrate-acpi-index", "true" }, 1452 }; 1453 const size_t malta_compat_len = G_N_ELEMENTS(malta_compat); 1454 1455 static void mips_malta_machine_init(MachineClass *mc) 1456 { 1457 mc->desc = "MIPS Malta Core LV"; 1458 mc->init = mips_malta_init; 1459 mc->block_default_type = IF_IDE; 1460 mc->max_cpus = 16; 1461 mc->is_default = true; 1462 #ifdef TARGET_MIPS64 1463 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); 1464 #else 1465 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 1466 #endif 1467 mc->default_ram_id = "mips_malta.ram"; 1468 compat_props_add(mc->compat_props, malta_compat, malta_compat_len); 1469 } 1470 1471 DEFINE_MACHINE("malta", mips_malta_machine_init) 1472 1473 static void mips_malta_register_types(void) 1474 { 1475 type_register_static(&mips_malta_device); 1476 } 1477 1478 type_init(mips_malta_register_types)