lpc_ich9.c (27715B)
1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "cpu.h" 34 #include "qapi/error.h" 35 #include "qapi/visitor.h" 36 #include "qemu/range.h" 37 #include "hw/dma/i8257.h" 38 #include "hw/isa/isa.h" 39 #include "migration/vmstate.h" 40 #include "hw/irq.h" 41 #include "hw/isa/apm.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci/pci_bridge.h" 44 #include "hw/i386/ich9.h" 45 #include "hw/acpi/acpi.h" 46 #include "hw/acpi/ich9.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/qdev-properties.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "hw/core/cpu.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "qemu/cutils.h" 54 #include "hw/acpi/acpi_aml_interface.h" 55 56 /*****************************************************************************/ 57 /* ICH9 LPC PCI to ISA bridge */ 58 59 static void ich9_lpc_reset(DeviceState *qdev); 60 61 /* chipset configuration register 62 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 63 * are used. 64 * Although it's not pci configuration space, it's little endian as Intel. 65 */ 66 67 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 68 { 69 int intx; 70 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 71 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 72 } 73 } 74 75 static void ich9_cc_update(ICH9LPCState *lpc) 76 { 77 int slot; 78 int pci_intx; 79 80 const int reg_offsets[] = { 81 ICH9_CC_D25IR, 82 ICH9_CC_D26IR, 83 ICH9_CC_D27IR, 84 ICH9_CC_D28IR, 85 ICH9_CC_D29IR, 86 ICH9_CC_D30IR, 87 ICH9_CC_D31IR, 88 }; 89 const int *offset; 90 91 /* D{25 - 31}IR, but D30IR is read only to 0. */ 92 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 93 if (slot == 30) { 94 continue; 95 } 96 ich9_cc_update_ir(lpc->irr[slot], 97 pci_get_word(lpc->chip_config + *offset)); 98 } 99 100 /* 101 * D30: DMI2PCI bridge 102 * It is arbitrarily decided how INTx lines of PCI devices behind 103 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 104 * INT[A-D] are connected to PIRQ[E-H] 105 */ 106 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 107 lpc->irr[30][pci_intx] = pci_intx + 4; 108 } 109 } 110 111 static void ich9_cc_init(ICH9LPCState *lpc) 112 { 113 int slot; 114 int intx; 115 116 /* the default irq routing is arbitrary as long as it matches with 117 * acpi irq routing table. 118 * The one that is incompatible with piix_pci(= bochs) one is 119 * intentionally chosen to let the users know that the different 120 * board is used. 121 * 122 * int[A-D] -> pirq[E-F] 123 * avoid pirq A-D because they are used for pci express port 124 */ 125 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 126 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 127 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 128 } 129 } 130 ich9_cc_update(lpc); 131 } 132 133 static void ich9_cc_reset(ICH9LPCState *lpc) 134 { 135 uint8_t *c = lpc->chip_config; 136 137 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 138 139 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 145 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 146 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 147 148 ich9_cc_update(lpc); 149 } 150 151 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 152 { 153 *addr &= ICH9_CC_ADDR_MASK; 154 if (*addr + *len >= ICH9_CC_SIZE) { 155 *len = ICH9_CC_SIZE - *addr; 156 } 157 } 158 159 /* val: little endian */ 160 static void ich9_cc_write(void *opaque, hwaddr addr, 161 uint64_t val, unsigned len) 162 { 163 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 164 165 ich9_cc_addr_len(&addr, &len); 166 memcpy(lpc->chip_config + addr, &val, len); 167 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 168 ich9_cc_update(lpc); 169 } 170 171 /* return value: little endian */ 172 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 173 unsigned len) 174 { 175 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 176 177 uint32_t val = 0; 178 ich9_cc_addr_len(&addr, &len); 179 memcpy(&val, lpc->chip_config + addr, len); 180 return val; 181 } 182 183 /* IRQ routing */ 184 /* */ 185 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 186 { 187 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 188 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 189 } 190 191 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 192 int *pic_irq, int *pic_dis) 193 { 194 switch (pirq_num) { 195 case 0 ... 3: /* A-D */ 196 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 197 pic_irq, pic_dis); 198 return; 199 case 4 ... 7: /* E-H */ 200 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 201 pic_irq, pic_dis); 202 return; 203 default: 204 break; 205 } 206 abort(); 207 } 208 209 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 210 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 211 { 212 int i, pic_level; 213 214 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 215 216 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 217 pic_level = 0; 218 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 219 int tmp_irq; 220 int tmp_dis; 221 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 222 if (!tmp_dis && tmp_irq == gsi) { 223 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 224 } 225 } 226 if (gsi == lpc->sci_gsi) { 227 pic_level |= lpc->sci_level; 228 } 229 230 qemu_set_irq(lpc->gsi[gsi], pic_level); 231 } 232 233 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 234 static int ich9_pirq_to_gsi(int pirq) 235 { 236 return pirq + ICH9_LPC_PIC_NUM_PINS; 237 } 238 239 static int ich9_gsi_to_pirq(int gsi) 240 { 241 return gsi - ICH9_LPC_PIC_NUM_PINS; 242 } 243 244 /* gsi: ioapic irq 16-23, otherwise assert */ 245 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 246 { 247 int level = 0; 248 249 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 250 251 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 252 if (gsi == lpc->sci_gsi) { 253 level |= lpc->sci_level; 254 } 255 256 qemu_set_irq(lpc->gsi[gsi], level); 257 } 258 259 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 260 { 261 ICH9LPCState *lpc = opaque; 262 int pic_irq, pic_dis; 263 264 assert(0 <= pirq); 265 assert(pirq < ICH9_LPC_NB_PIRQS); 266 267 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 268 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 269 ich9_lpc_update_pic(lpc, pic_irq); 270 } 271 272 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 273 * a given device irq pin. 274 */ 275 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 276 { 277 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 278 PCIBus *pci_bus = PCI_BUS(bus); 279 PCIDevice *lpc_pdev = 280 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 281 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 282 283 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 284 } 285 286 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 287 { 288 ICH9LPCState *lpc = opaque; 289 PCIINTxRoute route; 290 int pic_irq; 291 int pic_dis; 292 293 assert(0 <= pirq_pin); 294 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 295 296 route.mode = PCI_INTX_ENABLED; 297 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 298 if (!pic_dis) { 299 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 300 route.irq = pic_irq; 301 } else { 302 route.mode = PCI_INTX_DISABLED; 303 route.irq = -1; 304 } 305 } else { 306 route.irq = ich9_pirq_to_gsi(pirq_pin); 307 } 308 309 return route; 310 } 311 312 void ich9_generate_smi(void) 313 { 314 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 315 } 316 317 /* Returns -1 on error, IRQ number on success */ 318 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 319 { 320 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & 321 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK; 322 switch (sel) { 323 case ICH9_LPC_ACPI_CTRL_9: 324 return 9; 325 case ICH9_LPC_ACPI_CTRL_10: 326 return 10; 327 case ICH9_LPC_ACPI_CTRL_11: 328 return 11; 329 case ICH9_LPC_ACPI_CTRL_20: 330 return 20; 331 case ICH9_LPC_ACPI_CTRL_21: 332 return 21; 333 default: 334 /* reserved */ 335 qemu_log_mask(LOG_GUEST_ERROR, 336 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel); 337 break; 338 } 339 return -1; 340 } 341 342 static void ich9_set_sci(void *opaque, int irq_num, int level) 343 { 344 ICH9LPCState *lpc = opaque; 345 int irq; 346 347 assert(irq_num == 0); 348 level = !!level; 349 if (level == lpc->sci_level) { 350 return; 351 } 352 lpc->sci_level = level; 353 354 irq = lpc->sci_gsi; 355 if (irq < 0) { 356 return; 357 } 358 359 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 360 ich9_lpc_update_apic(lpc, irq); 361 } else { 362 ich9_lpc_update_pic(lpc, irq); 363 } 364 } 365 366 static void smi_features_ok_callback(void *opaque) 367 { 368 ICH9LPCState *lpc = opaque; 369 uint64_t guest_features; 370 uint64_t guest_cpu_hotplug_features; 371 372 if (lpc->smi_features_ok) { 373 /* negotiation already complete, features locked */ 374 return; 375 } 376 377 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 378 le64_to_cpus(&guest_features); 379 if (guest_features & ~lpc->smi_host_features) { 380 /* guest requests invalid features, leave @features_ok at zero */ 381 return; 382 } 383 384 guest_cpu_hotplug_features = guest_features & 385 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | 386 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 387 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && 388 guest_cpu_hotplug_features) { 389 /* 390 * cpu hot-[un]plug with SMI requires SMI broadcast, 391 * leave @features_ok at zero 392 */ 393 return; 394 } 395 396 if (guest_cpu_hotplug_features == 397 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) { 398 /* cpu hot-unplug is unsupported without cpu-hotplug */ 399 return; 400 } 401 402 /* valid feature subset requested, lock it down, report success */ 403 lpc->smi_negotiated_features = guest_features; 404 lpc->smi_features_ok = 1; 405 } 406 407 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 408 { 409 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 410 qemu_irq sci_irq; 411 FWCfgState *fw_cfg = fw_cfg_find(); 412 413 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 414 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 415 416 if (lpc->smi_host_features && fw_cfg) { 417 uint64_t host_features_le; 418 419 host_features_le = cpu_to_le64(lpc->smi_host_features); 420 memcpy(lpc->smi_host_features_le, &host_features_le, 421 sizeof host_features_le); 422 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 423 lpc->smi_host_features_le, 424 sizeof lpc->smi_host_features_le); 425 426 /* The other two guest-visible fields are cleared on device reset, we 427 * just link them into fw_cfg here. 428 */ 429 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 430 NULL, NULL, NULL, 431 lpc->smi_guest_features_le, 432 sizeof lpc->smi_guest_features_le, 433 false); 434 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 435 smi_features_ok_callback, NULL, lpc, 436 &lpc->smi_features_ok, 437 sizeof lpc->smi_features_ok, 438 true); 439 } 440 441 ich9_lpc_reset(DEVICE(lpc)); 442 } 443 444 /* APM */ 445 446 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 447 { 448 ICH9LPCState *lpc = arg; 449 450 /* ACPI specs 3.0, 4.7.2.5 */ 451 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 452 val == ICH9_APM_ACPI_ENABLE, 453 val == ICH9_APM_ACPI_DISABLE); 454 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 455 return; 456 } 457 458 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 459 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 460 if (lpc->smi_negotiated_features & 461 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 462 CPUState *cs; 463 CPU_FOREACH(cs) { 464 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 465 } 466 } else { 467 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 468 } 469 } 470 } 471 472 /* config:PMBASE */ 473 static void 474 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 475 { 476 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 477 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 478 int new_gsi; 479 480 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 481 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 482 } else { 483 pm_io_base = 0; 484 } 485 486 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 487 488 new_gsi = ich9_lpc_sci_irq(lpc); 489 if (new_gsi == -1) { 490 return; 491 } 492 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 493 qemu_set_irq(lpc->pm.irq, 0); 494 lpc->sci_gsi = new_gsi; 495 qemu_set_irq(lpc->pm.irq, 1); 496 } 497 lpc->sci_gsi = new_gsi; 498 } 499 500 /* config:RCBA */ 501 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 502 { 503 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 504 505 if (rcba_old & ICH9_LPC_RCBA_EN) { 506 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 507 } 508 if (rcba & ICH9_LPC_RCBA_EN) { 509 memory_region_add_subregion_overlap(get_system_memory(), 510 rcba & ICH9_LPC_RCBA_BA_MASK, 511 &lpc->rcrb_mem, 1); 512 } 513 } 514 515 /* config:GEN_PMCON* */ 516 static void 517 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 518 { 519 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 520 uint16_t wmask; 521 522 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 523 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 524 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 525 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 526 lpc->pm.smi_en_wmask &= ~1; 527 } 528 } 529 530 static int ich9_lpc_post_load(void *opaque, int version_id) 531 { 532 ICH9LPCState *lpc = opaque; 533 534 ich9_lpc_pmbase_sci_update(lpc); 535 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 536 ich9_lpc_pmcon_update(lpc); 537 return 0; 538 } 539 540 static void ich9_lpc_config_write(PCIDevice *d, 541 uint32_t addr, uint32_t val, int len) 542 { 543 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 544 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 545 546 pci_default_write_config(d, addr, val, len); 547 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 548 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 549 ich9_lpc_pmbase_sci_update(lpc); 550 } 551 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 552 ich9_lpc_rcba_update(lpc, rcba_old); 553 } 554 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 555 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 556 } 557 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 558 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 559 } 560 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 561 ich9_lpc_pmcon_update(lpc); 562 } 563 } 564 565 static void ich9_lpc_reset(DeviceState *qdev) 566 { 567 PCIDevice *d = PCI_DEVICE(qdev); 568 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 569 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 570 int i; 571 572 for (i = 0; i < 4; i++) { 573 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 574 ICH9_LPC_PIRQ_ROUT_DEFAULT); 575 } 576 for (i = 0; i < 4; i++) { 577 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 578 ICH9_LPC_PIRQ_ROUT_DEFAULT); 579 } 580 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 581 582 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 583 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 584 585 ich9_cc_reset(lpc); 586 587 ich9_lpc_pmbase_sci_update(lpc); 588 ich9_lpc_rcba_update(lpc, rcba_old); 589 590 lpc->sci_level = 0; 591 lpc->rst_cnt = 0; 592 593 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 594 lpc->smi_features_ok = 0; 595 lpc->smi_negotiated_features = 0; 596 } 597 598 /* root complex register block is mapped into memory space */ 599 static const MemoryRegionOps rcrb_mmio_ops = { 600 .read = ich9_cc_read, 601 .write = ich9_cc_write, 602 .endianness = DEVICE_LITTLE_ENDIAN, 603 }; 604 605 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 606 { 607 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 608 MemoryRegion *io_as = pci_address_space_io(&s->d); 609 uint8_t *pci_conf; 610 611 pci_conf = s->d.config; 612 if (memory_region_present(io_as, 0x3f8)) { 613 /* com1 */ 614 pci_conf[0x82] |= 0x01; 615 } 616 if (memory_region_present(io_as, 0x2f8)) { 617 /* com2 */ 618 pci_conf[0x82] |= 0x02; 619 } 620 if (memory_region_present(io_as, 0x378)) { 621 /* lpt */ 622 pci_conf[0x82] |= 0x04; 623 } 624 if (memory_region_present(io_as, 0x3f2)) { 625 /* floppy */ 626 pci_conf[0x82] |= 0x08; 627 } 628 } 629 630 /* reset control */ 631 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 632 unsigned len) 633 { 634 ICH9LPCState *lpc = opaque; 635 636 if (val & 4) { 637 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 638 return; 639 } 640 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 641 } 642 643 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 644 { 645 ICH9LPCState *lpc = opaque; 646 647 return lpc->rst_cnt; 648 } 649 650 static const MemoryRegionOps ich9_rst_cnt_ops = { 651 .read = ich9_rst_cnt_read, 652 .write = ich9_rst_cnt_write, 653 .endianness = DEVICE_LITTLE_ENDIAN 654 }; 655 656 static void ich9_lpc_initfn(Object *obj) 657 { 658 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 659 660 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 661 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 662 663 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, 664 &lpc->sci_gsi, OBJ_PROP_FLAG_READ); 665 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 666 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 667 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 668 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 669 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, 670 &lpc->smi_negotiated_features, 671 OBJ_PROP_FLAG_READ); 672 673 ich9_pm_add_properties(obj, &lpc->pm); 674 } 675 676 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 677 { 678 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 679 DeviceState *dev = DEVICE(d); 680 ISABus *isa_bus; 681 682 if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) && 683 !(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) { 684 /* 685 * smi_features_ok_callback() throws an error on this. 686 * 687 * So bail out here instead of advertizing the invalid 688 * configuration and get obscure firmware failures from that. 689 */ 690 error_setg(errp, "cpu hot-unplug requires cpu hot-plug"); 691 return; 692 } 693 694 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 695 errp); 696 if (!isa_bus) { 697 return; 698 } 699 700 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 701 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 702 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 703 ICH9_LPC_ACPI_CTRL_ACPI_EN | 704 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 705 706 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 707 "lpc-rcrb-mmio", ICH9_CC_SIZE); 708 709 lpc->isa_bus = isa_bus; 710 711 ich9_cc_init(lpc); 712 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 713 714 lpc->machine_ready.notify = ich9_lpc_machine_ready; 715 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 716 717 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 718 "lpc-reset-control", 1); 719 memory_region_add_subregion_overlap(pci_address_space_io(d), 720 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 721 1); 722 723 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 724 725 isa_bus_irqs(isa_bus, lpc->gsi); 726 727 i8257_dma_init(isa_bus, 0); 728 } 729 730 static bool ich9_rst_cnt_needed(void *opaque) 731 { 732 ICH9LPCState *lpc = opaque; 733 734 return (lpc->rst_cnt != 0); 735 } 736 737 static const VMStateDescription vmstate_ich9_rst_cnt = { 738 .name = "ICH9LPC/rst_cnt", 739 .version_id = 1, 740 .minimum_version_id = 1, 741 .needed = ich9_rst_cnt_needed, 742 .fields = (VMStateField[]) { 743 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 744 VMSTATE_END_OF_LIST() 745 } 746 }; 747 748 static bool ich9_smi_feat_needed(void *opaque) 749 { 750 ICH9LPCState *lpc = opaque; 751 752 return !buffer_is_zero(lpc->smi_guest_features_le, 753 sizeof lpc->smi_guest_features_le) || 754 lpc->smi_features_ok; 755 } 756 757 static const VMStateDescription vmstate_ich9_smi_feat = { 758 .name = "ICH9LPC/smi_feat", 759 .version_id = 1, 760 .minimum_version_id = 1, 761 .needed = ich9_smi_feat_needed, 762 .fields = (VMStateField[]) { 763 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 764 sizeof(uint64_t)), 765 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 766 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 767 VMSTATE_END_OF_LIST() 768 } 769 }; 770 771 static const VMStateDescription vmstate_ich9_lpc = { 772 .name = "ICH9LPC", 773 .version_id = 1, 774 .minimum_version_id = 1, 775 .post_load = ich9_lpc_post_load, 776 .fields = (VMStateField[]) { 777 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 778 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 779 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 780 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 781 VMSTATE_UINT32(sci_level, ICH9LPCState), 782 VMSTATE_END_OF_LIST() 783 }, 784 .subsections = (const VMStateDescription*[]) { 785 &vmstate_ich9_rst_cnt, 786 &vmstate_ich9_smi_feat, 787 NULL 788 } 789 }; 790 791 static Property ich9_lpc_properties[] = { 792 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 793 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), 794 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 795 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 796 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, 797 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), 798 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, 799 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true), 800 DEFINE_PROP_END_OF_LIST(), 801 }; 802 803 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 804 { 805 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 806 807 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 808 } 809 810 static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) 811 { 812 Aml *field; 813 BusChild *kid; 814 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 815 BusState *bus = BUS(s->isa_bus); 816 Aml *sb_scope = aml_scope("\\_SB"); 817 818 /* ICH9 PCI to ISA irq remapping */ 819 aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, 820 aml_int(0x60), 0x0C)); 821 /* Fields declarion has to happen *after* operation region */ 822 field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 823 aml_append(field, aml_named_field("PRQA", 8)); 824 aml_append(field, aml_named_field("PRQB", 8)); 825 aml_append(field, aml_named_field("PRQC", 8)); 826 aml_append(field, aml_named_field("PRQD", 8)); 827 aml_append(field, aml_reserved_field(0x20)); 828 aml_append(field, aml_named_field("PRQE", 8)); 829 aml_append(field, aml_named_field("PRQF", 8)); 830 aml_append(field, aml_named_field("PRQG", 8)); 831 aml_append(field, aml_named_field("PRQH", 8)); 832 aml_append(sb_scope, field); 833 aml_append(scope, sb_scope); 834 835 QTAILQ_FOREACH(kid, &bus->children, sibling) { 836 call_dev_aml_func(DEVICE(kid->child), scope); 837 } 838 } 839 840 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 841 { 842 DeviceClass *dc = DEVICE_CLASS(klass); 843 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 844 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 845 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 846 AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass); 847 848 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 849 dc->reset = ich9_lpc_reset; 850 k->realize = ich9_lpc_realize; 851 dc->vmsd = &vmstate_ich9_lpc; 852 device_class_set_props(dc, ich9_lpc_properties); 853 k->config_write = ich9_lpc_config_write; 854 dc->desc = "ICH9 LPC bridge"; 855 k->vendor_id = PCI_VENDOR_ID_INTEL; 856 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 857 k->revision = ICH9_A2_LPC_REVISION; 858 k->class_id = PCI_CLASS_BRIDGE_ISA; 859 /* 860 * Reason: part of ICH9 southbridge, needs to be wired up by 861 * pc_q35_init() 862 */ 863 dc->user_creatable = false; 864 hc->pre_plug = ich9_pm_device_pre_plug_cb; 865 hc->plug = ich9_pm_device_plug_cb; 866 hc->unplug_request = ich9_pm_device_unplug_request_cb; 867 hc->unplug = ich9_pm_device_unplug_cb; 868 adevc->ospm_status = ich9_pm_ospm_status; 869 adevc->send_event = ich9_send_gpe; 870 adevc->madt_cpu = pc_madt_cpu_entry; 871 amldevc->build_dev_aml = build_ich9_isa_aml; 872 } 873 874 static const TypeInfo ich9_lpc_info = { 875 .name = TYPE_ICH9_LPC_DEVICE, 876 .parent = TYPE_PCI_DEVICE, 877 .instance_size = sizeof(ICH9LPCState), 878 .instance_init = ich9_lpc_initfn, 879 .class_init = ich9_lpc_class_init, 880 .interfaces = (InterfaceInfo[]) { 881 { TYPE_HOTPLUG_HANDLER }, 882 { TYPE_ACPI_DEVICE_IF }, 883 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 884 { TYPE_ACPI_DEV_AML_IF }, 885 { } 886 } 887 }; 888 889 static void ich9_lpc_register(void) 890 { 891 type_register_static(&ich9_lpc_info); 892 } 893 894 type_init(ich9_lpc_register);