arm_gicv3_dist.c (30888B)
1 /* 2 * ARM GICv3 emulation: Distributor 3 * 4 * Copyright (c) 2015 Huawei. 5 * Copyright (c) 2016 Linaro Limited. 6 * Written by Shlomo Pongratz, Peter Maydell 7 * 8 * This code is licensed under the GPL, version 2 or (at your option) 9 * any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "trace.h" 15 #include "gicv3_internal.h" 16 17 /* The GICD_NSACR registers contain a two bit field for each interrupt which 18 * allows the guest to give NonSecure code access to registers controlling 19 * Secure interrupts: 20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI) 21 * 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR 22 * 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER, 23 * and w/o to CLRSPI_NSR 24 * 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR 25 * 26 * Given a (multiple-of-32) interrupt number, these mask functions return 27 * a mask word where each bit is 1 if the NSACR settings permit access 28 * to the interrupt. The mask returned can then be ORed with the GICD_GROUP 29 * word for this set of interrupts to give an overall mask. 30 */ 31 32 typedef uint32_t maskfn(GICv3State *s, int irq); 33 34 static uint32_t mask_nsacr_ge1(GICv3State *s, int irq) 35 { 36 /* Return a mask where each bit is set if the NSACR field is >= 1 */ 37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 38 39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr; 41 return half_unshuffle64(raw_nsacr); 42 } 43 44 static uint32_t mask_nsacr_ge2(GICv3State *s, int irq) 45 { 46 /* Return a mask where each bit is set if the NSACR field is >= 2 */ 47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; 48 49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; 50 raw_nsacr = raw_nsacr >> 1; 51 return half_unshuffle64(raw_nsacr); 52 } 53 54 /* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register, 55 * but it would be implemented using: 56 * raw_nsacr = (raw_nsacr >> 1) & raw_nsacr; 57 */ 58 59 static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs, 60 maskfn *maskfn, int irq) 61 { 62 /* Return a 32-bit mask which should be applied for this set of 32 63 * interrupts; each bit is 1 if access is permitted by the 64 * combination of attrs.secure, GICD_GROUPR and GICD_NSACR. 65 */ 66 uint32_t mask; 67 68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI 70 * unless the NSACR bits permit access. 71 */ 72 mask = *gic_bmp_ptr32(s->group, irq); 73 if (maskfn) { 74 mask |= maskfn(s, irq); 75 } 76 return mask; 77 } 78 return 0xFFFFFFFFU; 79 } 80 81 static int gicd_ns_access(GICv3State *s, int irq) 82 { 83 /* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the 84 * specified interrupt. 85 */ 86 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 87 return 0; 88 } 89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); 90 } 91 92 static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 93 uint32_t *bmp, 94 maskfn *maskfn, 95 int offset, uint32_t val) 96 { 97 /* Helper routine to implement writing to a "set-bitmap" register 98 * (GICD_ISENABLER, GICD_ISPENDR, etc). 99 * Semantics implemented here: 100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 102 * Writing 1 means "set bit in bitmap"; writing 0 is ignored. 103 * offset should be the offset in bytes of the register from the start 104 * of its group. 105 */ 106 int irq = offset * 8; 107 108 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 109 return; 110 } 111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 112 *gic_bmp_ptr32(bmp, irq) |= val; 113 gicv3_update(s, irq, 32); 114 } 115 116 static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 117 uint32_t *bmp, 118 maskfn *maskfn, 119 int offset, uint32_t val) 120 { 121 /* Helper routine to implement writing to a "clear-bitmap" register 122 * (GICD_ICENABLER, GICD_ICPENDR, etc). 123 * Semantics implemented here: 124 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 125 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 126 * Writing 1 means "clear bit in bitmap"; writing 0 is ignored. 127 * offset should be the offset in bytes of the register from the start 128 * of its group. 129 */ 130 int irq = offset * 8; 131 132 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 133 return; 134 } 135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 136 *gic_bmp_ptr32(bmp, irq) &= ~val; 137 gicv3_update(s, irq, 32); 138 } 139 140 static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs, 141 uint32_t *bmp, 142 maskfn *maskfn, 143 int offset) 144 { 145 /* Helper routine to implement reading a "set/clear-bitmap" register 146 * (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc). 147 * Semantics implemented here: 148 * RAZ/WI for SGIs, PPIs, unimplemented IRQs 149 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. 150 * offset should be the offset in bytes of the register from the start 151 * of its group. 152 */ 153 int irq = offset * 8; 154 uint32_t val; 155 156 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 157 return 0; 158 } 159 val = *gic_bmp_ptr32(bmp, irq); 160 if (bmp == s->pending) { 161 /* The PENDING register is a special case -- for level triggered 162 * interrupts, the PENDING state is the logical OR of the state of 163 * the PENDING latch with the input line level. 164 */ 165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq); 166 uint32_t level = *gic_bmp_ptr32(s->level, irq); 167 val |= (~edge & level); 168 } 169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq); 170 return val; 171 } 172 173 static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq) 174 { 175 /* Read the value of GICD_IPRIORITYR<n> for the specified interrupt, 176 * honouring security state (these are RAZ/WI for Group 0 or Secure 177 * Group 1 interrupts). 178 */ 179 uint32_t prio; 180 181 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 182 return 0; 183 } 184 185 prio = s->gicd_ipriority[irq]; 186 187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 188 if (!gicv3_gicd_group_test(s, irq)) { 189 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 190 return 0; 191 } 192 /* NS view of the interrupt priority */ 193 prio = (prio << 1) & 0xff; 194 } 195 return prio; 196 } 197 198 static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq, 199 uint8_t value) 200 { 201 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt, 202 * honouring security state (these are RAZ/WI for Group 0 or Secure 203 * Group 1 interrupts). 204 */ 205 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 206 return; 207 } 208 209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 210 if (!gicv3_gicd_group_test(s, irq)) { 211 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ 212 return; 213 } 214 /* NS view of the interrupt priority */ 215 value = 0x80 | (value >> 1); 216 } 217 s->gicd_ipriority[irq] = value; 218 } 219 220 static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq) 221 { 222 /* Read the value of GICD_IROUTER<n> for the specified interrupt, 223 * honouring security state. 224 */ 225 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 226 return 0; 227 } 228 229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 230 /* RAZ/WI for NS accesses to secure interrupts */ 231 if (!gicv3_gicd_group_test(s, irq)) { 232 if (gicd_ns_access(s, irq) != 3) { 233 return 0; 234 } 235 } 236 } 237 238 return s->gicd_irouter[irq]; 239 } 240 241 static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq, 242 uint64_t val) 243 { 244 /* Write the value of GICD_IROUTER<n> for the specified interrupt, 245 * honouring security state. 246 */ 247 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 248 return; 249 } 250 251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 252 /* RAZ/WI for NS accesses to secure interrupts */ 253 if (!gicv3_gicd_group_test(s, irq)) { 254 if (gicd_ns_access(s, irq) != 3) { 255 return; 256 } 257 } 258 } 259 260 s->gicd_irouter[irq] = val; 261 gicv3_cache_target_cpustate(s, irq); 262 gicv3_update(s, irq, 1); 263 } 264 265 /** 266 * gicd_readb 267 * gicd_readw 268 * gicd_readl 269 * gicd_readq 270 * gicd_writeb 271 * gicd_writew 272 * gicd_writel 273 * gicd_writeq 274 * 275 * Return %true if the operation succeeded, %false otherwise. 276 */ 277 278 static bool gicd_readb(GICv3State *s, hwaddr offset, 279 uint64_t *data, MemTxAttrs attrs) 280 { 281 /* Most GICv3 distributor registers do not support byte accesses. */ 282 switch (offset) { 283 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 284 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 285 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 286 /* This GIC implementation always has affinity routing enabled, 287 * so these registers are all RAZ/WI. 288 */ 289 return true; 290 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 291 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); 292 return true; 293 default: 294 return false; 295 } 296 } 297 298 static bool gicd_writeb(GICv3State *s, hwaddr offset, 299 uint64_t value, MemTxAttrs attrs) 300 { 301 /* Most GICv3 distributor registers do not support byte accesses. */ 302 switch (offset) { 303 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 304 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 305 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 306 /* This GIC implementation always has affinity routing enabled, 307 * so these registers are all RAZ/WI. 308 */ 309 return true; 310 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 311 { 312 int irq = offset - GICD_IPRIORITYR; 313 314 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 315 return true; 316 } 317 gicd_write_ipriorityr(s, attrs, irq, value); 318 gicv3_update(s, irq, 1); 319 return true; 320 } 321 default: 322 return false; 323 } 324 } 325 326 static bool gicd_readw(GICv3State *s, hwaddr offset, 327 uint64_t *data, MemTxAttrs attrs) 328 { 329 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 330 * support 16 bit accesses, and those registers are all part of the 331 * optional message-based SPI feature which this GIC does not currently 332 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 333 * reserved. 334 */ 335 return false; 336 } 337 338 static bool gicd_writew(GICv3State *s, hwaddr offset, 339 uint64_t value, MemTxAttrs attrs) 340 { 341 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR 342 * support 16 bit accesses, and those registers are all part of the 343 * optional message-based SPI feature which this GIC does not currently 344 * implement (ie for us GICD_TYPER.MBIS == 0), so for us they are 345 * reserved. 346 */ 347 return false; 348 } 349 350 static bool gicd_readl(GICv3State *s, hwaddr offset, 351 uint64_t *data, MemTxAttrs attrs) 352 { 353 /* Almost all GICv3 distributor registers are 32-bit. 354 * Note that WO registers must return an UNKNOWN value on reads, 355 * not an abort. 356 */ 357 358 switch (offset) { 359 case GICD_CTLR: 360 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 361 /* The NS view of the GICD_CTLR sees only certain bits: 362 * + bit [31] (RWP) is an alias of the Secure bit [31] 363 * + bit [4] (ARE_NS) is an alias of Secure bit [5] 364 * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if 365 * NS affinity routing is enabled, otherwise RES0 366 * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if 367 * NS affinity routing is not enabled, otherwise RES0 368 * Since for QEMU affinity routing is always enabled 369 * for both S and NS this means that bits [4] and [5] are 370 * both always 1, and we can simply make the NS view 371 * be bits 31, 4 and 1 of the S view. 372 */ 373 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S | 374 GICD_CTLR_EN_GRP1NS | 375 GICD_CTLR_RWP); 376 } else { 377 *data = s->gicd_ctlr; 378 } 379 return true; 380 case GICD_TYPER: 381 { 382 /* For this implementation: 383 * No1N == 1 (1-of-N SPI interrupts not supported) 384 * A3V == 1 (non-zero values of Affinity level 3 supported) 385 * IDbits == 0xf (we support 16-bit interrupt identifiers) 386 * DVIS == 1 (Direct virtual LPI injection supported) if GICv4 387 * LPIS == 1 (LPIs are supported if affinity routing is enabled) 388 * num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated 389 * by GICD_TYPER.IDbits) 390 * MBIS == 0 (message-based SPIs not supported) 391 * SecurityExtn == 1 if security extns supported 392 * CPUNumber == 0 since for us ARE is always 1 393 * ITLinesNumber == (num external irqs / 32) - 1 394 */ 395 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; 396 /* 397 * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and 398 * "security extensions not supported" always implies DS == 1, 399 * so we only need to check the DS bit. 400 */ 401 bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); 402 bool dvis = s->revision >= 4; 403 404 *data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) | 405 (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | 406 (0xf << 19) | itlinesnumber; 407 return true; 408 } 409 case GICD_IIDR: 410 /* We claim to be an ARM r0p0 with a zero ProductID. 411 * This is the same as an r0p0 GIC-500. 412 */ 413 *data = gicv3_iidr(); 414 return true; 415 case GICD_STATUSR: 416 /* RAZ/WI for us (this is an optional register and our implementation 417 * does not track RO/WO/reserved violations to report them to the guest) 418 */ 419 *data = 0; 420 return true; 421 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 422 { 423 int irq; 424 425 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 426 *data = 0; 427 return true; 428 } 429 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 430 irq = (offset - GICD_IGROUPR) * 8; 431 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 432 *data = 0; 433 return true; 434 } 435 *data = *gic_bmp_ptr32(s->group, irq); 436 return true; 437 } 438 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 439 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 440 offset - GICD_ISENABLER); 441 return true; 442 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 443 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, 444 offset - GICD_ICENABLER); 445 return true; 446 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 447 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 448 offset - GICD_ISPENDR); 449 return true; 450 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 451 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 452 offset - GICD_ICPENDR); 453 return true; 454 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 455 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 456 offset - GICD_ISACTIVER); 457 return true; 458 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 459 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, 460 offset - GICD_ICACTIVER); 461 return true; 462 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 463 { 464 int i, irq = offset - GICD_IPRIORITYR; 465 uint32_t value = 0; 466 467 for (i = irq + 3; i >= irq; i--) { 468 value <<= 8; 469 value |= gicd_read_ipriorityr(s, attrs, i); 470 } 471 *data = value; 472 return true; 473 } 474 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 475 /* RAZ/WI since affinity routing is always enabled */ 476 *data = 0; 477 return true; 478 case GICD_ICFGR ... GICD_ICFGR + 0xff: 479 { 480 /* Here only the even bits are used; odd bits are RES0 */ 481 int irq = (offset - GICD_ICFGR) * 4; 482 uint32_t value = 0; 483 484 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 485 *data = 0; 486 return true; 487 } 488 489 /* Since our edge_trigger bitmap is one bit per irq, we only need 490 * half of the 32-bit word, which we can then spread out 491 * into the odd bits. 492 */ 493 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f); 494 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 495 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16); 496 value = half_shuffle32(value) << 1; 497 *data = value; 498 return true; 499 } 500 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 501 { 502 int irq; 503 504 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 505 /* RAZ/WI if security disabled, or if 506 * security enabled and this is an NS access 507 */ 508 *data = 0; 509 return true; 510 } 511 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 512 irq = (offset - GICD_IGRPMODR) * 8; 513 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 514 *data = 0; 515 return true; 516 } 517 *data = *gic_bmp_ptr32(s->grpmod, irq); 518 return true; 519 } 520 case GICD_NSACR ... GICD_NSACR + 0xff: 521 { 522 /* Two bits per interrupt */ 523 int irq = (offset - GICD_NSACR) * 4; 524 525 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 526 *data = 0; 527 return true; 528 } 529 530 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 531 /* RAZ/WI if security disabled, or if 532 * security enabled and this is an NS access 533 */ 534 *data = 0; 535 return true; 536 } 537 538 *data = s->gicd_nsacr[irq / 16]; 539 return true; 540 } 541 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 542 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 543 /* RAZ/WI since affinity routing is always enabled */ 544 *data = 0; 545 return true; 546 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 547 { 548 uint64_t r; 549 int irq = (offset - GICD_IROUTER) / 8; 550 551 r = gicd_read_irouter(s, attrs, irq); 552 if (offset & 7) { 553 *data = r >> 32; 554 } else { 555 *data = (uint32_t)r; 556 } 557 return true; 558 } 559 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 560 /* ID registers */ 561 *data = gicv3_idreg(s, offset - GICD_IDREGS, GICV3_PIDR0_DIST); 562 return true; 563 case GICD_SGIR: 564 /* WO registers, return unknown value */ 565 qemu_log_mask(LOG_GUEST_ERROR, 566 "%s: invalid guest read from WO register at offset " 567 TARGET_FMT_plx "\n", __func__, offset); 568 *data = 0; 569 return true; 570 default: 571 return false; 572 } 573 } 574 575 static bool gicd_writel(GICv3State *s, hwaddr offset, 576 uint64_t value, MemTxAttrs attrs) 577 { 578 /* Almost all GICv3 distributor registers are 32-bit. Note that 579 * RO registers must ignore writes, not abort. 580 */ 581 582 switch (offset) { 583 case GICD_CTLR: 584 { 585 uint32_t mask; 586 /* GICv3 5.3.20 */ 587 if (s->gicd_ctlr & GICD_CTLR_DS) { 588 /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI, 589 * ARE is RAO/WI (affinity routing always on), and only 590 * bits 0 and 1 (group enables) are writable. 591 */ 592 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS; 593 } else { 594 if (attrs.secure) { 595 /* for secure access: 596 * ARE_NS and ARE_S are RAO/WI (affinity routing always on) 597 * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup) 598 * 599 * We can only modify bits[2:0] (the group enables). 600 */ 601 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL; 602 } else { 603 /* For non secure access ARE_NS is RAO/WI and EnableGrp1 604 * is RES0. The only writable bit is [1] (EnableGrp1A), which 605 * is an alias of the Secure bit [1]. 606 */ 607 mask = GICD_CTLR_EN_GRP1NS; 608 } 609 } 610 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask); 611 if (value & mask & GICD_CTLR_DS) { 612 /* We just set DS, so the ARE_NS and EnG1S bits are now RES0. 613 * Note that this is a one-way transition because if DS is set 614 * then it's not writable, so it can only go back to 0 with a 615 * hardware reset. 616 */ 617 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); 618 } 619 gicv3_full_update(s); 620 return true; 621 } 622 case GICD_STATUSR: 623 /* RAZ/WI for our implementation */ 624 return true; 625 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f: 626 { 627 int irq; 628 629 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { 630 return true; 631 } 632 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 633 irq = (offset - GICD_IGROUPR) * 8; 634 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 635 return true; 636 } 637 *gic_bmp_ptr32(s->group, irq) = value; 638 gicv3_update(s, irq, 32); 639 return true; 640 } 641 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f: 642 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, 643 offset - GICD_ISENABLER, value); 644 return true; 645 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f: 646 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, 647 offset - GICD_ICENABLER, value); 648 return true; 649 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f: 650 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, 651 offset - GICD_ISPENDR, value); 652 return true; 653 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f: 654 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, 655 offset - GICD_ICPENDR, value); 656 return true; 657 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f: 658 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, 659 offset - GICD_ISACTIVER, value); 660 return true; 661 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f: 662 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, 663 offset - GICD_ICACTIVER, value); 664 return true; 665 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff: 666 { 667 int i, irq = offset - GICD_IPRIORITYR; 668 669 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) { 670 return true; 671 } 672 673 for (i = irq; i < irq + 4; i++, value >>= 8) { 674 gicd_write_ipriorityr(s, attrs, i, value); 675 } 676 gicv3_update(s, irq, 4); 677 return true; 678 } 679 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff: 680 /* RAZ/WI since affinity routing is always enabled */ 681 return true; 682 case GICD_ICFGR ... GICD_ICFGR + 0xff: 683 { 684 /* Here only the odd bits are used; even bits are RES0 */ 685 int irq = (offset - GICD_ICFGR) * 4; 686 uint32_t mask, oldval; 687 688 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 689 return true; 690 } 691 692 /* Since our edge_trigger bitmap is one bit per irq, our input 693 * 32-bits will compress down into 16 bits which we need 694 * to write into the bitmap. 695 */ 696 value = half_unshuffle32(value >> 1); 697 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f); 698 if (irq & 0x1f) { 699 value <<= 16; 700 mask &= 0xffff0000U; 701 } else { 702 mask &= 0xffff; 703 } 704 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); 705 value = (oldval & ~mask) | (value & mask); 706 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value; 707 return true; 708 } 709 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff: 710 { 711 int irq; 712 713 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 714 /* RAZ/WI if security disabled, or if 715 * security enabled and this is an NS access 716 */ 717 return true; 718 } 719 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ 720 irq = (offset - GICD_IGRPMODR) * 8; 721 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 722 return true; 723 } 724 *gic_bmp_ptr32(s->grpmod, irq) = value; 725 gicv3_update(s, irq, 32); 726 return true; 727 } 728 case GICD_NSACR ... GICD_NSACR + 0xff: 729 { 730 /* Two bits per interrupt */ 731 int irq = (offset - GICD_NSACR) * 4; 732 733 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 734 return true; 735 } 736 737 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { 738 /* RAZ/WI if security disabled, or if 739 * security enabled and this is an NS access 740 */ 741 return true; 742 } 743 744 s->gicd_nsacr[irq / 16] = value; 745 /* No update required as this only affects access permission checks */ 746 return true; 747 } 748 case GICD_SGIR: 749 /* RES0 if affinity routing is enabled */ 750 return true; 751 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf: 752 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: 753 /* RAZ/WI since affinity routing is always enabled */ 754 return true; 755 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 756 { 757 uint64_t r; 758 int irq = (offset - GICD_IROUTER) / 8; 759 760 if (irq < GIC_INTERNAL || irq >= s->num_irq) { 761 return true; 762 } 763 764 /* Write half of the 64-bit register */ 765 r = gicd_read_irouter(s, attrs, irq); 766 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value); 767 gicd_write_irouter(s, attrs, irq, r); 768 return true; 769 } 770 case GICD_IDREGS ... GICD_IDREGS + 0x2f: 771 case GICD_TYPER: 772 case GICD_IIDR: 773 /* RO registers, ignore the write */ 774 qemu_log_mask(LOG_GUEST_ERROR, 775 "%s: invalid guest write to RO register at offset " 776 TARGET_FMT_plx "\n", __func__, offset); 777 return true; 778 default: 779 return false; 780 } 781 } 782 783 static bool gicd_writeq(GICv3State *s, hwaddr offset, 784 uint64_t value, MemTxAttrs attrs) 785 { 786 /* Our only 64-bit registers are GICD_IROUTER<n> */ 787 int irq; 788 789 switch (offset) { 790 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 791 irq = (offset - GICD_IROUTER) / 8; 792 gicd_write_irouter(s, attrs, irq, value); 793 return true; 794 default: 795 return false; 796 } 797 } 798 799 static bool gicd_readq(GICv3State *s, hwaddr offset, 800 uint64_t *data, MemTxAttrs attrs) 801 { 802 /* Our only 64-bit registers are GICD_IROUTER<n> */ 803 int irq; 804 805 switch (offset) { 806 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: 807 irq = (offset - GICD_IROUTER) / 8; 808 *data = gicd_read_irouter(s, attrs, irq); 809 return true; 810 default: 811 return false; 812 } 813 } 814 815 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 816 unsigned size, MemTxAttrs attrs) 817 { 818 GICv3State *s = (GICv3State *)opaque; 819 bool r; 820 821 switch (size) { 822 case 1: 823 r = gicd_readb(s, offset, data, attrs); 824 break; 825 case 2: 826 r = gicd_readw(s, offset, data, attrs); 827 break; 828 case 4: 829 r = gicd_readl(s, offset, data, attrs); 830 break; 831 case 8: 832 r = gicd_readq(s, offset, data, attrs); 833 break; 834 default: 835 r = false; 836 break; 837 } 838 839 if (!r) { 840 qemu_log_mask(LOG_GUEST_ERROR, 841 "%s: invalid guest read at offset " TARGET_FMT_plx 842 " size %u\n", __func__, offset, size); 843 trace_gicv3_dist_badread(offset, size, attrs.secure); 844 /* The spec requires that reserved registers are RAZ/WI; 845 * so use MEMTX_ERROR returns from leaf functions as a way to 846 * trigger the guest-error logging but don't return it to 847 * the caller, or we'll cause a spurious guest data abort. 848 */ 849 *data = 0; 850 } else { 851 trace_gicv3_dist_read(offset, *data, size, attrs.secure); 852 } 853 return MEMTX_OK; 854 } 855 856 MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, 857 unsigned size, MemTxAttrs attrs) 858 { 859 GICv3State *s = (GICv3State *)opaque; 860 bool r; 861 862 switch (size) { 863 case 1: 864 r = gicd_writeb(s, offset, data, attrs); 865 break; 866 case 2: 867 r = gicd_writew(s, offset, data, attrs); 868 break; 869 case 4: 870 r = gicd_writel(s, offset, data, attrs); 871 break; 872 case 8: 873 r = gicd_writeq(s, offset, data, attrs); 874 break; 875 default: 876 r = false; 877 break; 878 } 879 880 if (!r) { 881 qemu_log_mask(LOG_GUEST_ERROR, 882 "%s: invalid guest write at offset " TARGET_FMT_plx 883 " size %u\n", __func__, offset, size); 884 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); 885 /* The spec requires that reserved registers are RAZ/WI; 886 * so use MEMTX_ERROR returns from leaf functions as a way to 887 * trigger the guest-error logging but don't return it to 888 * the caller, or we'll cause a spurious guest data abort. 889 */ 890 } else { 891 trace_gicv3_dist_write(offset, data, size, attrs.secure); 892 } 893 return MEMTX_OK; 894 } 895 896 void gicv3_dist_set_irq(GICv3State *s, int irq, int level) 897 { 898 /* Update distributor state for a change in an external SPI input line */ 899 if (level == gicv3_gicd_level_test(s, irq)) { 900 return; 901 } 902 903 trace_gicv3_dist_set_irq(irq, level); 904 905 gicv3_gicd_level_replace(s, irq, level); 906 907 if (level) { 908 /* 0->1 edges latch the pending bit for edge-triggered interrupts */ 909 if (gicv3_gicd_edge_trigger_test(s, irq)) { 910 gicv3_gicd_pending_set(s, irq); 911 } 912 } 913 914 gicv3_update(s, irq, 1); 915 }