pc.c (68205B)
1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/cxl/cxl.h" 79 #include "hw/cxl/cxl_host.h" 80 #include "qapi/error.h" 81 #include "qapi/qapi-visit-common.h" 82 #include "qapi/qapi-visit-machine.h" 83 #include "qapi/visitor.h" 84 #include "hw/core/cpu.h" 85 #include "hw/usb.h" 86 #include "hw/i386/intel_iommu.h" 87 #include "hw/net/ne2000-isa.h" 88 #include "standard-headers/asm-x86/bootparam.h" 89 #include "hw/virtio/virtio-iommu.h" 90 #include "hw/virtio/virtio-pmem-pci.h" 91 #include "hw/virtio/virtio-mem-pci.h" 92 #include "hw/mem/memory-device.h" 93 #include "sysemu/replay.h" 94 #include "target/i386/cpu.h" 95 #include "qapi/qmp/qerror.h" 96 #include "e820_memory_layout.h" 97 #include "fw_cfg.h" 98 #include "trace.h" 99 #include CONFIG_DEVICES 100 101 /* 102 * Helper for setting model-id for CPU models that changed model-id 103 * depending on QEMU versions up to QEMU 2.4. 104 */ 105 #define PC_CPU_MODEL_IDS(v) \ 106 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 107 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 108 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 109 110 GlobalProperty pc_compat_7_1[] = {}; 111 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 112 113 GlobalProperty pc_compat_7_0[] = {}; 114 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 115 116 GlobalProperty pc_compat_6_2[] = { 117 { "virtio-mem", "unplugged-inaccessible", "off" }, 118 }; 119 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 120 121 GlobalProperty pc_compat_6_1[] = { 122 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 123 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 124 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 125 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 126 }; 127 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 128 129 GlobalProperty pc_compat_6_0[] = { 130 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 131 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 132 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 133 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 134 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 135 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 136 }; 137 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 138 139 GlobalProperty pc_compat_5_2[] = { 140 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 141 }; 142 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 143 144 GlobalProperty pc_compat_5_1[] = { 145 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 146 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 147 }; 148 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 149 150 GlobalProperty pc_compat_5_0[] = { 151 }; 152 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 153 154 GlobalProperty pc_compat_4_2[] = { 155 { "mch", "smbase-smram", "off" }, 156 }; 157 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 158 159 GlobalProperty pc_compat_4_1[] = {}; 160 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 161 162 GlobalProperty pc_compat_4_0[] = {}; 163 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 164 165 GlobalProperty pc_compat_3_1[] = { 166 { "intel-iommu", "dma-drain", "off" }, 167 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 168 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 169 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 170 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 171 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 172 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 173 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 174 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 175 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 176 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 177 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 178 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 179 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 180 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 181 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 182 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 183 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 184 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 185 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 186 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 187 }; 188 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 189 190 GlobalProperty pc_compat_3_0[] = { 191 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 192 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 193 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 194 }; 195 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 196 197 GlobalProperty pc_compat_2_12[] = { 198 { TYPE_X86_CPU, "legacy-cache", "on" }, 199 { TYPE_X86_CPU, "topoext", "off" }, 200 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 201 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 202 }; 203 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 204 205 GlobalProperty pc_compat_2_11[] = { 206 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 207 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 208 }; 209 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 210 211 GlobalProperty pc_compat_2_10[] = { 212 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 213 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 214 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 215 }; 216 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 217 218 GlobalProperty pc_compat_2_9[] = { 219 { "mch", "extended-tseg-mbytes", "0" }, 220 }; 221 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 222 223 GlobalProperty pc_compat_2_8[] = { 224 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 225 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 226 { "ICH9-LPC", "x-smi-broadcast", "off" }, 227 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 228 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 229 }; 230 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 231 232 GlobalProperty pc_compat_2_7[] = { 233 { TYPE_X86_CPU, "l3-cache", "off" }, 234 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 235 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 236 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 237 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 238 { "isa-pcspk", "migrate", "off" }, 239 }; 240 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 241 242 GlobalProperty pc_compat_2_6[] = { 243 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 244 { "vmxnet3", "romfile", "" }, 245 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 246 { "apic-common", "legacy-instance-id", "on", } 247 }; 248 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 249 250 GlobalProperty pc_compat_2_5[] = {}; 251 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 252 253 GlobalProperty pc_compat_2_4[] = { 254 PC_CPU_MODEL_IDS("2.4.0") 255 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 256 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 257 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 258 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 259 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 260 { TYPE_X86_CPU, "check", "off" }, 261 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 262 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 263 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 264 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 265 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 266 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 267 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 268 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 269 }; 270 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 271 272 GlobalProperty pc_compat_2_3[] = { 273 PC_CPU_MODEL_IDS("2.3.0") 274 { TYPE_X86_CPU, "arat", "off" }, 275 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 276 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 277 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 278 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 279 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 280 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 281 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 282 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 283 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 284 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 285 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 286 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 287 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 288 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 289 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 290 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 291 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 292 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 293 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 294 }; 295 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 296 297 GlobalProperty pc_compat_2_2[] = { 298 PC_CPU_MODEL_IDS("2.2.0") 299 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 301 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 302 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 303 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 307 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 308 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 309 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 310 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 311 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 312 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 313 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 314 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 315 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 316 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 317 }; 318 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 319 320 GlobalProperty pc_compat_2_1[] = { 321 PC_CPU_MODEL_IDS("2.1.0") 322 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 323 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 324 }; 325 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 326 327 GlobalProperty pc_compat_2_0[] = { 328 PC_CPU_MODEL_IDS("2.0.0") 329 { "virtio-scsi-pci", "any_layout", "off" }, 330 { "PIIX4_PM", "memory-hotplug-support", "off" }, 331 { "apic", "version", "0x11" }, 332 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 333 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 334 { "pci-serial", "prog_if", "0" }, 335 { "pci-serial-2x", "prog_if", "0" }, 336 { "pci-serial-4x", "prog_if", "0" }, 337 { "virtio-net-pci", "guest_announce", "off" }, 338 { "ICH9-LPC", "memory-hotplug-support", "off" }, 339 }; 340 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 341 342 GlobalProperty pc_compat_1_7[] = { 343 PC_CPU_MODEL_IDS("1.7.0") 344 { TYPE_USB_DEVICE, "msos-desc", "no" }, 345 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 346 { "hpet", HPET_INTCAP, "4" }, 347 }; 348 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 349 350 GlobalProperty pc_compat_1_6[] = { 351 PC_CPU_MODEL_IDS("1.6.0") 352 { "e1000", "mitigation", "off" }, 353 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 354 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 355 { "i440FX-pcihost", "short_root_bus", "1" }, 356 { "q35-pcihost", "short_root_bus", "1" }, 357 }; 358 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 359 360 GlobalProperty pc_compat_1_5[] = { 361 PC_CPU_MODEL_IDS("1.5.0") 362 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 363 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 364 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 365 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 366 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 367 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 368 { "virtio-net-pci", "any_layout", "off" }, 369 { TYPE_X86_CPU, "pmu", "on" }, 370 { "i440FX-pcihost", "short_root_bus", "0" }, 371 { "q35-pcihost", "short_root_bus", "0" }, 372 }; 373 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 374 375 GlobalProperty pc_compat_1_4[] = { 376 PC_CPU_MODEL_IDS("1.4.0") 377 { "scsi-hd", "discard_granularity", "0" }, 378 { "scsi-cd", "discard_granularity", "0" }, 379 { "ide-hd", "discard_granularity", "0" }, 380 { "ide-cd", "discard_granularity", "0" }, 381 { "virtio-blk-pci", "discard_granularity", "0" }, 382 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 383 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 384 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 385 { "e1000", "romfile", "pxe-e1000.rom" }, 386 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 387 { "pcnet", "romfile", "pxe-pcnet.rom" }, 388 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 389 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 390 { "486-" TYPE_X86_CPU, "model", "0" }, 391 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 392 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 393 }; 394 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 395 396 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 397 { 398 GSIState *s; 399 400 s = g_new0(GSIState, 1); 401 if (kvm_ioapic_in_kernel()) { 402 kvm_pc_setup_irq_routing(pci_enabled); 403 } 404 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 405 406 return s; 407 } 408 409 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 410 unsigned size) 411 { 412 } 413 414 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 415 { 416 return 0xffffffffffffffffULL; 417 } 418 419 /* MSDOS compatibility mode FPU exception support */ 420 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 421 unsigned size) 422 { 423 if (tcg_enabled()) { 424 cpu_set_ignne(); 425 } 426 } 427 428 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 429 { 430 return 0xffffffffffffffffULL; 431 } 432 433 /* PC cmos mappings */ 434 435 #define REG_EQUIPMENT_BYTE 0x14 436 437 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 438 int16_t cylinders, int8_t heads, int8_t sectors) 439 { 440 rtc_set_memory(s, type_ofs, 47); 441 rtc_set_memory(s, info_ofs, cylinders); 442 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 443 rtc_set_memory(s, info_ofs + 2, heads); 444 rtc_set_memory(s, info_ofs + 3, 0xff); 445 rtc_set_memory(s, info_ofs + 4, 0xff); 446 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 447 rtc_set_memory(s, info_ofs + 6, cylinders); 448 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 449 rtc_set_memory(s, info_ofs + 8, sectors); 450 } 451 452 /* convert boot_device letter to something recognizable by the bios */ 453 static int boot_device2nibble(char boot_device) 454 { 455 switch(boot_device) { 456 case 'a': 457 case 'b': 458 return 0x01; /* floppy boot */ 459 case 'c': 460 return 0x02; /* hard drive boot */ 461 case 'd': 462 return 0x03; /* CD-ROM boot */ 463 case 'n': 464 return 0x04; /* Network boot */ 465 } 466 return 0; 467 } 468 469 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 470 { 471 #define PC_MAX_BOOT_DEVICES 3 472 int nbds, bds[3] = { 0, }; 473 int i; 474 475 nbds = strlen(boot_device); 476 if (nbds > PC_MAX_BOOT_DEVICES) { 477 error_setg(errp, "Too many boot devices for PC"); 478 return; 479 } 480 for (i = 0; i < nbds; i++) { 481 bds[i] = boot_device2nibble(boot_device[i]); 482 if (bds[i] == 0) { 483 error_setg(errp, "Invalid boot device for PC: '%c'", 484 boot_device[i]); 485 return; 486 } 487 } 488 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 489 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 490 } 491 492 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 493 { 494 set_boot_dev(opaque, boot_device, errp); 495 } 496 497 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 498 { 499 int val, nb, i; 500 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 501 FLOPPY_DRIVE_TYPE_NONE }; 502 503 /* floppy type */ 504 if (floppy) { 505 for (i = 0; i < 2; i++) { 506 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 507 } 508 } 509 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 510 cmos_get_fd_drive_type(fd_type[1]); 511 rtc_set_memory(rtc_state, 0x10, val); 512 513 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 514 nb = 0; 515 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 516 nb++; 517 } 518 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 519 nb++; 520 } 521 switch (nb) { 522 case 0: 523 break; 524 case 1: 525 val |= 0x01; /* 1 drive, ready for boot */ 526 break; 527 case 2: 528 val |= 0x41; /* 2 drives, ready for boot */ 529 break; 530 } 531 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 532 } 533 534 typedef struct pc_cmos_init_late_arg { 535 ISADevice *rtc_state; 536 BusState *idebus[2]; 537 } pc_cmos_init_late_arg; 538 539 typedef struct check_fdc_state { 540 ISADevice *floppy; 541 bool multiple; 542 } CheckFdcState; 543 544 static int check_fdc(Object *obj, void *opaque) 545 { 546 CheckFdcState *state = opaque; 547 Object *fdc; 548 uint32_t iobase; 549 Error *local_err = NULL; 550 551 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 552 if (!fdc) { 553 return 0; 554 } 555 556 iobase = object_property_get_uint(obj, "iobase", &local_err); 557 if (local_err || iobase != 0x3f0) { 558 error_free(local_err); 559 return 0; 560 } 561 562 if (state->floppy) { 563 state->multiple = true; 564 } else { 565 state->floppy = ISA_DEVICE(obj); 566 } 567 return 0; 568 } 569 570 static const char * const fdc_container_path[] = { 571 "/unattached", "/peripheral", "/peripheral-anon" 572 }; 573 574 /* 575 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 576 * and ACPI objects. 577 */ 578 static ISADevice *pc_find_fdc0(void) 579 { 580 int i; 581 Object *container; 582 CheckFdcState state = { 0 }; 583 584 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 585 container = container_get(qdev_get_machine(), fdc_container_path[i]); 586 object_child_foreach(container, check_fdc, &state); 587 } 588 589 if (state.multiple) { 590 warn_report("multiple floppy disk controllers with " 591 "iobase=0x3f0 have been found"); 592 error_printf("the one being picked for CMOS setup might not reflect " 593 "your intent"); 594 } 595 596 return state.floppy; 597 } 598 599 static void pc_cmos_init_late(void *opaque) 600 { 601 pc_cmos_init_late_arg *arg = opaque; 602 ISADevice *s = arg->rtc_state; 603 int16_t cylinders; 604 int8_t heads, sectors; 605 int val; 606 int i, trans; 607 608 val = 0; 609 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 610 &cylinders, &heads, §ors) >= 0) { 611 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 612 val |= 0xf0; 613 } 614 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 615 &cylinders, &heads, §ors) >= 0) { 616 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 617 val |= 0x0f; 618 } 619 rtc_set_memory(s, 0x12, val); 620 621 val = 0; 622 for (i = 0; i < 4; i++) { 623 /* NOTE: ide_get_geometry() returns the physical 624 geometry. It is always such that: 1 <= sects <= 63, 1 625 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 626 geometry can be different if a translation is done. */ 627 if (arg->idebus[i / 2] && 628 ide_get_geometry(arg->idebus[i / 2], i % 2, 629 &cylinders, &heads, §ors) >= 0) { 630 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 631 assert((trans & ~3) == 0); 632 val |= trans << (i * 2); 633 } 634 } 635 rtc_set_memory(s, 0x39, val); 636 637 pc_cmos_init_floppy(s, pc_find_fdc0()); 638 639 qemu_unregister_reset(pc_cmos_init_late, opaque); 640 } 641 642 void pc_cmos_init(PCMachineState *pcms, 643 BusState *idebus0, BusState *idebus1, 644 ISADevice *s) 645 { 646 int val; 647 static pc_cmos_init_late_arg arg; 648 X86MachineState *x86ms = X86_MACHINE(pcms); 649 650 /* various important CMOS locations needed by PC/Bochs bios */ 651 652 /* memory size */ 653 /* base memory (first MiB) */ 654 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 655 rtc_set_memory(s, 0x15, val); 656 rtc_set_memory(s, 0x16, val >> 8); 657 /* extended memory (next 64MiB) */ 658 if (x86ms->below_4g_mem_size > 1 * MiB) { 659 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 660 } else { 661 val = 0; 662 } 663 if (val > 65535) 664 val = 65535; 665 rtc_set_memory(s, 0x17, val); 666 rtc_set_memory(s, 0x18, val >> 8); 667 rtc_set_memory(s, 0x30, val); 668 rtc_set_memory(s, 0x31, val >> 8); 669 /* memory between 16MiB and 4GiB */ 670 if (x86ms->below_4g_mem_size > 16 * MiB) { 671 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 672 } else { 673 val = 0; 674 } 675 if (val > 65535) 676 val = 65535; 677 rtc_set_memory(s, 0x34, val); 678 rtc_set_memory(s, 0x35, val >> 8); 679 /* memory above 4GiB */ 680 val = x86ms->above_4g_mem_size / 65536; 681 rtc_set_memory(s, 0x5b, val); 682 rtc_set_memory(s, 0x5c, val >> 8); 683 rtc_set_memory(s, 0x5d, val >> 16); 684 685 object_property_add_link(OBJECT(pcms), "rtc_state", 686 TYPE_ISA_DEVICE, 687 (Object **)&x86ms->rtc, 688 object_property_allow_set_link, 689 OBJ_PROP_LINK_STRONG); 690 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 691 &error_abort); 692 693 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 694 695 val = 0; 696 val |= 0x02; /* FPU is there */ 697 val |= 0x04; /* PS/2 mouse installed */ 698 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 699 700 /* hard drives and FDC */ 701 arg.rtc_state = s; 702 arg.idebus[0] = idebus0; 703 arg.idebus[1] = idebus1; 704 qemu_register_reset(pc_cmos_init_late, &arg); 705 } 706 707 static void handle_a20_line_change(void *opaque, int irq, int level) 708 { 709 X86CPU *cpu = opaque; 710 711 /* XXX: send to all CPUs ? */ 712 /* XXX: add logic to handle multiple A20 line sources */ 713 x86_cpu_set_a20(cpu, level); 714 } 715 716 #define NE2000_NB_MAX 6 717 718 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 719 0x280, 0x380 }; 720 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 721 722 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 723 { 724 static int nb_ne2k = 0; 725 726 if (nb_ne2k == NE2000_NB_MAX) 727 return; 728 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 729 ne2000_irq[nb_ne2k], nd); 730 nb_ne2k++; 731 } 732 733 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 734 { 735 X86CPU *cpu = opaque; 736 737 if (level) { 738 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 739 } 740 } 741 742 static 743 void pc_machine_done(Notifier *notifier, void *data) 744 { 745 PCMachineState *pcms = container_of(notifier, 746 PCMachineState, machine_done); 747 X86MachineState *x86ms = X86_MACHINE(pcms); 748 749 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 750 &error_fatal); 751 752 if (pcms->cxl_devices_state.is_enabled) { 753 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 754 } 755 756 /* set the number of CPUs */ 757 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 758 759 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 760 761 acpi_setup(); 762 if (x86ms->fw_cfg) { 763 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 764 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 765 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 766 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 767 } 768 } 769 770 void pc_guest_info_init(PCMachineState *pcms) 771 { 772 X86MachineState *x86ms = X86_MACHINE(pcms); 773 774 x86ms->apic_xrupt_override = true; 775 pcms->machine_done.notify = pc_machine_done; 776 qemu_add_machine_init_done_notifier(&pcms->machine_done); 777 } 778 779 /* setup pci memory address space mapping into system address space */ 780 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 781 MemoryRegion *pci_address_space) 782 { 783 /* Set to lower priority than RAM */ 784 memory_region_add_subregion_overlap(system_memory, 0x0, 785 pci_address_space, -1); 786 } 787 788 void xen_load_linux(PCMachineState *pcms) 789 { 790 int i; 791 FWCfgState *fw_cfg; 792 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 793 X86MachineState *x86ms = X86_MACHINE(pcms); 794 795 assert(MACHINE(pcms)->kernel_filename != NULL); 796 797 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 798 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 799 rom_set_fw(fw_cfg); 800 801 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 802 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 803 for (i = 0; i < nb_option_roms; i++) { 804 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 805 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 806 !strcmp(option_rom[i].name, "pvh.bin") || 807 !strcmp(option_rom[i].name, "multiboot.bin") || 808 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 809 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 810 } 811 x86ms->fw_cfg = fw_cfg; 812 } 813 814 #define PC_ROM_MIN_VGA 0xc0000 815 #define PC_ROM_MIN_OPTION 0xc8000 816 #define PC_ROM_MAX 0xe0000 817 #define PC_ROM_ALIGN 0x800 818 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 819 820 static hwaddr pc_above_4g_end(PCMachineState *pcms) 821 { 822 X86MachineState *x86ms = X86_MACHINE(pcms); 823 824 if (pcms->sgx_epc.size != 0) { 825 return sgx_epc_above_4g_end(&pcms->sgx_epc); 826 } 827 828 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 829 } 830 831 static void pc_get_device_memory_range(PCMachineState *pcms, 832 hwaddr *base, 833 ram_addr_t *device_mem_size) 834 { 835 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 836 MachineState *machine = MACHINE(pcms); 837 ram_addr_t size; 838 hwaddr addr; 839 840 size = machine->maxram_size - machine->ram_size; 841 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 842 843 if (pcmc->enforce_aligned_dimm) { 844 /* size device region assuming 1G page max alignment per slot */ 845 size += (1 * GiB) * machine->ram_slots; 846 } 847 848 *base = addr; 849 *device_mem_size = size; 850 } 851 852 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 853 { 854 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 855 hwaddr cxl_base; 856 ram_addr_t size; 857 858 if (pcmc->has_reserved_memory) { 859 pc_get_device_memory_range(pcms, &cxl_base, &size); 860 cxl_base += size; 861 } else { 862 cxl_base = pc_above_4g_end(pcms); 863 } 864 865 return cxl_base; 866 } 867 868 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 869 { 870 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 871 872 if (pcms->cxl_devices_state.fixed_windows) { 873 GList *it; 874 875 start = ROUND_UP(start, 256 * MiB); 876 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 877 CXLFixedWindow *fw = it->data; 878 start += fw->size; 879 } 880 } 881 882 return start; 883 } 884 885 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 886 { 887 X86CPU *cpu = X86_CPU(first_cpu); 888 889 /* 32-bit systems don't have hole64 thus return max CPU address */ 890 if (cpu->phys_bits <= 32) { 891 return ((hwaddr)1 << cpu->phys_bits) - 1; 892 } 893 894 return pc_pci_hole64_start() + pci_hole64_size - 1; 895 } 896 897 /* 898 * AMD systems with an IOMMU have an additional hole close to the 899 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 900 * on kernel version, VFIO may or may not let you DMA map those ranges. 901 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 902 * with certain memory sizes. It's also wrong to use those IOVA ranges 903 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 904 * The ranges reserved for Hyper-Transport are: 905 * 906 * FD_0000_0000h - FF_FFFF_FFFFh 907 * 908 * The ranges represent the following: 909 * 910 * Base Address Top Address Use 911 * 912 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 913 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 914 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 915 * FD_F910_0000h FD_F91F_FFFFh System Management 916 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 917 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 918 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 919 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 920 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 921 * FE_2000_0000h FF_FFFF_FFFFh Reserved 922 * 923 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 924 * Table 3: Special Address Controls (GPA) for more information. 925 */ 926 #define AMD_HT_START 0xfd00000000UL 927 #define AMD_HT_END 0xffffffffffUL 928 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 929 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 930 931 void pc_memory_init(PCMachineState *pcms, 932 MemoryRegion *system_memory, 933 MemoryRegion *rom_memory, 934 MemoryRegion **ram_memory, 935 uint64_t pci_hole64_size) 936 { 937 int linux_boot, i; 938 MemoryRegion *option_rom_mr; 939 MemoryRegion *ram_below_4g, *ram_above_4g; 940 FWCfgState *fw_cfg; 941 MachineState *machine = MACHINE(pcms); 942 MachineClass *mc = MACHINE_GET_CLASS(machine); 943 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 944 X86MachineState *x86ms = X86_MACHINE(pcms); 945 hwaddr maxphysaddr, maxusedaddr; 946 hwaddr cxl_base, cxl_resv_end = 0; 947 X86CPU *cpu = X86_CPU(first_cpu); 948 949 assert(machine->ram_size == x86ms->below_4g_mem_size + 950 x86ms->above_4g_mem_size); 951 952 linux_boot = (machine->kernel_filename != NULL); 953 954 /* 955 * The HyperTransport range close to the 1T boundary is unique to AMD 956 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 957 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 958 * older machine types (<= 7.0) for compatibility purposes. 959 */ 960 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 961 /* Bail out if max possible address does not cross HT range */ 962 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 963 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 964 } 965 966 /* 967 * Advertise the HT region if address space covers the reserved 968 * region or if we relocate. 969 */ 970 if (cpu->phys_bits >= 40) { 971 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 972 } 973 } 974 975 /* 976 * phys-bits is required to be appropriately configured 977 * to make sure max used GPA is reachable. 978 */ 979 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 980 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 981 if (maxphysaddr < maxusedaddr) { 982 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 983 " phys-bits too low (%u)", 984 maxphysaddr, maxusedaddr, cpu->phys_bits); 985 exit(EXIT_FAILURE); 986 } 987 988 /* 989 * Split single memory region and use aliases to address portions of it, 990 * done for backwards compatibility with older qemus. 991 */ 992 *ram_memory = machine->ram; 993 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 994 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 995 0, x86ms->below_4g_mem_size); 996 memory_region_add_subregion(system_memory, 0, ram_below_4g); 997 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 998 if (x86ms->above_4g_mem_size > 0) { 999 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1000 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1001 machine->ram, 1002 x86ms->below_4g_mem_size, 1003 x86ms->above_4g_mem_size); 1004 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1005 ram_above_4g); 1006 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1007 E820_RAM); 1008 } 1009 1010 if (pcms->sgx_epc.size != 0) { 1011 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1012 } 1013 1014 if (!pcmc->has_reserved_memory && 1015 (machine->ram_slots || 1016 (machine->maxram_size > machine->ram_size))) { 1017 1018 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1019 mc->name); 1020 exit(EXIT_FAILURE); 1021 } 1022 1023 /* always allocate the device memory information */ 1024 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1025 1026 /* initialize device memory address space */ 1027 if (pcmc->has_reserved_memory && 1028 (machine->ram_size < machine->maxram_size)) { 1029 ram_addr_t device_mem_size; 1030 1031 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1032 error_report("unsupported amount of memory slots: %"PRIu64, 1033 machine->ram_slots); 1034 exit(EXIT_FAILURE); 1035 } 1036 1037 if (QEMU_ALIGN_UP(machine->maxram_size, 1038 TARGET_PAGE_SIZE) != machine->maxram_size) { 1039 error_report("maximum memory size must by aligned to multiple of " 1040 "%d bytes", TARGET_PAGE_SIZE); 1041 exit(EXIT_FAILURE); 1042 } 1043 1044 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1045 1046 if ((machine->device_memory->base + device_mem_size) < 1047 device_mem_size) { 1048 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1049 machine->maxram_size); 1050 exit(EXIT_FAILURE); 1051 } 1052 1053 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1054 "device-memory", device_mem_size); 1055 memory_region_add_subregion(system_memory, machine->device_memory->base, 1056 &machine->device_memory->mr); 1057 } 1058 1059 if (pcms->cxl_devices_state.is_enabled) { 1060 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1061 hwaddr cxl_size = MiB; 1062 1063 cxl_base = pc_get_cxl_range_start(pcms); 1064 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1065 memory_region_add_subregion(system_memory, cxl_base, mr); 1066 cxl_resv_end = cxl_base + cxl_size; 1067 if (pcms->cxl_devices_state.fixed_windows) { 1068 hwaddr cxl_fmw_base; 1069 GList *it; 1070 1071 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1072 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1073 CXLFixedWindow *fw = it->data; 1074 1075 fw->base = cxl_fmw_base; 1076 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1077 "cxl-fixed-memory-region", fw->size); 1078 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1079 cxl_fmw_base += fw->size; 1080 cxl_resv_end = cxl_fmw_base; 1081 } 1082 } 1083 } 1084 1085 /* Initialize PC system firmware */ 1086 pc_system_firmware_init(pcms, rom_memory); 1087 1088 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1089 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1090 &error_fatal); 1091 if (pcmc->pci_enabled) { 1092 memory_region_set_readonly(option_rom_mr, true); 1093 } 1094 memory_region_add_subregion_overlap(rom_memory, 1095 PC_ROM_MIN_VGA, 1096 option_rom_mr, 1097 1); 1098 1099 fw_cfg = fw_cfg_arch_create(machine, 1100 x86ms->boot_cpus, x86ms->apic_id_limit); 1101 1102 rom_set_fw(fw_cfg); 1103 1104 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1105 uint64_t *val = g_malloc(sizeof(*val)); 1106 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1107 uint64_t res_mem_end = machine->device_memory->base; 1108 1109 if (!pcmc->broken_reserved_end) { 1110 res_mem_end += memory_region_size(&machine->device_memory->mr); 1111 } 1112 1113 if (pcms->cxl_devices_state.is_enabled) { 1114 res_mem_end = cxl_resv_end; 1115 } 1116 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1117 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1118 } 1119 1120 if (linux_boot) { 1121 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1122 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 1123 } 1124 1125 for (i = 0; i < nb_option_roms; i++) { 1126 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1127 } 1128 x86ms->fw_cfg = fw_cfg; 1129 1130 /* Init default IOAPIC address space */ 1131 x86ms->ioapic_as = &address_space_memory; 1132 1133 /* Init ACPI memory hotplug IO base address */ 1134 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1135 } 1136 1137 /* 1138 * The 64bit pci hole starts after "above 4G RAM" and 1139 * potentially the space reserved for memory hotplug. 1140 */ 1141 uint64_t pc_pci_hole64_start(void) 1142 { 1143 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1144 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1145 MachineState *ms = MACHINE(pcms); 1146 uint64_t hole64_start = 0; 1147 ram_addr_t size = 0; 1148 1149 if (pcms->cxl_devices_state.is_enabled) { 1150 hole64_start = pc_get_cxl_range_end(pcms); 1151 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1152 pc_get_device_memory_range(pcms, &hole64_start, &size); 1153 if (!pcmc->broken_reserved_end) { 1154 hole64_start += size; 1155 } 1156 } else { 1157 hole64_start = pc_above_4g_end(pcms); 1158 } 1159 1160 return ROUND_UP(hole64_start, 1 * GiB); 1161 } 1162 1163 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1164 { 1165 DeviceState *dev = NULL; 1166 1167 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1168 if (pci_bus) { 1169 PCIDevice *pcidev = pci_vga_init(pci_bus); 1170 dev = pcidev ? &pcidev->qdev : NULL; 1171 } else if (isa_bus) { 1172 ISADevice *isadev = isa_vga_init(isa_bus); 1173 dev = isadev ? DEVICE(isadev) : NULL; 1174 } 1175 rom_reset_order_override(); 1176 return dev; 1177 } 1178 1179 static const MemoryRegionOps ioport80_io_ops = { 1180 .write = ioport80_write, 1181 .read = ioport80_read, 1182 .endianness = DEVICE_NATIVE_ENDIAN, 1183 .impl = { 1184 .min_access_size = 1, 1185 .max_access_size = 1, 1186 }, 1187 }; 1188 1189 static const MemoryRegionOps ioportF0_io_ops = { 1190 .write = ioportF0_write, 1191 .read = ioportF0_read, 1192 .endianness = DEVICE_NATIVE_ENDIAN, 1193 .impl = { 1194 .min_access_size = 1, 1195 .max_access_size = 1, 1196 }, 1197 }; 1198 1199 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1200 bool create_i8042, bool no_vmport) 1201 { 1202 int i; 1203 DriveInfo *fd[MAX_FD]; 1204 qemu_irq *a20_line; 1205 ISADevice *fdc, *i8042, *port92, *vmmouse; 1206 1207 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1208 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1209 1210 for (i = 0; i < MAX_FD; i++) { 1211 fd[i] = drive_get(IF_FLOPPY, 0, i); 1212 create_fdctrl |= !!fd[i]; 1213 } 1214 if (create_fdctrl) { 1215 fdc = isa_new(TYPE_ISA_FDC); 1216 if (fdc) { 1217 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1218 isa_fdc_init_drives(fdc, fd); 1219 } 1220 } 1221 1222 if (!create_i8042) { 1223 return; 1224 } 1225 1226 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1227 if (!no_vmport) { 1228 isa_create_simple(isa_bus, TYPE_VMPORT); 1229 vmmouse = isa_try_new("vmmouse"); 1230 } else { 1231 vmmouse = NULL; 1232 } 1233 if (vmmouse) { 1234 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1235 &error_abort); 1236 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1237 } 1238 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1239 1240 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1241 i8042_setup_a20_line(i8042, a20_line[0]); 1242 qdev_connect_gpio_out_named(DEVICE(port92), 1243 PORT92_A20_LINE, 0, a20_line[1]); 1244 g_free(a20_line); 1245 } 1246 1247 void pc_basic_device_init(struct PCMachineState *pcms, 1248 ISABus *isa_bus, qemu_irq *gsi, 1249 ISADevice **rtc_state, 1250 bool create_fdctrl, 1251 uint32_t hpet_irqs) 1252 { 1253 int i; 1254 DeviceState *hpet = NULL; 1255 int pit_isa_irq = 0; 1256 qemu_irq pit_alt_irq = NULL; 1257 qemu_irq rtc_irq = NULL; 1258 ISADevice *pit = NULL; 1259 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1260 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1261 X86MachineState *x86ms = X86_MACHINE(pcms); 1262 1263 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1264 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1265 1266 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1267 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1268 1269 /* 1270 * Check if an HPET shall be created. 1271 * 1272 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1273 * when the HPET wants to take over. Thus we have to disable the latter. 1274 */ 1275 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1276 kvm_has_pit_state2())) { 1277 hpet = qdev_try_new(TYPE_HPET); 1278 if (!hpet) { 1279 error_report("couldn't create HPET device"); 1280 exit(1); 1281 } 1282 /* 1283 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1284 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1285 * IRQ2. 1286 */ 1287 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1288 HPET_INTCAP, NULL); 1289 if (!compat) { 1290 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1291 } 1292 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1293 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1294 1295 for (i = 0; i < GSI_NUM_PINS; i++) { 1296 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1297 } 1298 pit_isa_irq = -1; 1299 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1300 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1301 } 1302 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1303 1304 qemu_register_boot_set(pc_boot_set, *rtc_state); 1305 1306 if (!xen_enabled() && 1307 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1308 if (kvm_pit_in_kernel()) { 1309 pit = kvm_pit_init(isa_bus, 0x40); 1310 } else { 1311 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1312 } 1313 if (hpet) { 1314 /* connect PIT to output control line of the HPET */ 1315 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1316 } 1317 pcspk_init(pcms->pcspk, isa_bus, pit); 1318 } 1319 1320 /* Super I/O */ 1321 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1322 pcms->vmport != ON_OFF_AUTO_ON); 1323 } 1324 1325 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1326 { 1327 int i; 1328 1329 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1330 for (i = 0; i < nb_nics; i++) { 1331 NICInfo *nd = &nd_table[i]; 1332 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1333 1334 if (g_str_equal(model, "ne2k_isa")) { 1335 pc_init_ne2k_isa(isa_bus, nd); 1336 } else { 1337 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1338 } 1339 } 1340 rom_reset_order_override(); 1341 } 1342 1343 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1344 { 1345 qemu_irq *i8259; 1346 1347 if (kvm_pic_in_kernel()) { 1348 i8259 = kvm_i8259_init(isa_bus); 1349 } else if (xen_enabled()) { 1350 i8259 = xen_interrupt_controller_init(); 1351 } else { 1352 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1353 } 1354 1355 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1356 i8259_irqs[i] = i8259[i]; 1357 } 1358 1359 g_free(i8259); 1360 } 1361 1362 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1363 Error **errp) 1364 { 1365 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1366 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1367 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1368 const MachineState *ms = MACHINE(hotplug_dev); 1369 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1370 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1371 Error *local_err = NULL; 1372 1373 /* 1374 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1375 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1376 * addition to cover this case. 1377 */ 1378 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1379 error_setg(errp, 1380 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1381 return; 1382 } 1383 1384 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1385 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1386 return; 1387 } 1388 1389 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1390 if (local_err) { 1391 error_propagate(errp, local_err); 1392 return; 1393 } 1394 1395 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1396 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1397 } 1398 1399 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1400 DeviceState *dev, Error **errp) 1401 { 1402 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1403 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1404 MachineState *ms = MACHINE(hotplug_dev); 1405 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1406 1407 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1408 1409 if (is_nvdimm) { 1410 nvdimm_plug(ms->nvdimms_state); 1411 } 1412 1413 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1414 } 1415 1416 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1417 DeviceState *dev, Error **errp) 1418 { 1419 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1420 1421 /* 1422 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1423 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1424 * addition to cover this case. 1425 */ 1426 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1427 error_setg(errp, 1428 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1429 return; 1430 } 1431 1432 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1433 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1434 return; 1435 } 1436 1437 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1438 errp); 1439 } 1440 1441 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1442 DeviceState *dev, Error **errp) 1443 { 1444 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1445 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1446 Error *local_err = NULL; 1447 1448 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1449 if (local_err) { 1450 goto out; 1451 } 1452 1453 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1454 qdev_unrealize(dev); 1455 out: 1456 error_propagate(errp, local_err); 1457 } 1458 1459 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1460 DeviceState *dev, Error **errp) 1461 { 1462 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1463 Error *local_err = NULL; 1464 1465 if (!hotplug_dev2 && dev->hotplugged) { 1466 /* 1467 * Without a bus hotplug handler, we cannot control the plug/unplug 1468 * order. We should never reach this point when hotplugging on x86, 1469 * however, better add a safety net. 1470 */ 1471 error_setg(errp, "hotplug of virtio based memory devices not supported" 1472 " on this bus."); 1473 return; 1474 } 1475 /* 1476 * First, see if we can plug this memory device at all. If that 1477 * succeeds, branch of to the actual hotplug handler. 1478 */ 1479 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1480 &local_err); 1481 if (!local_err && hotplug_dev2) { 1482 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1483 } 1484 error_propagate(errp, local_err); 1485 } 1486 1487 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1488 DeviceState *dev, Error **errp) 1489 { 1490 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1491 Error *local_err = NULL; 1492 1493 /* 1494 * Plug the memory device first and then branch off to the actual 1495 * hotplug handler. If that one fails, we can easily undo the memory 1496 * device bits. 1497 */ 1498 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1499 if (hotplug_dev2) { 1500 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1501 if (local_err) { 1502 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1503 } 1504 } 1505 error_propagate(errp, local_err); 1506 } 1507 1508 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1509 DeviceState *dev, Error **errp) 1510 { 1511 /* We don't support hot unplug of virtio based memory devices */ 1512 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1513 } 1514 1515 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1516 DeviceState *dev, Error **errp) 1517 { 1518 /* We don't support hot unplug of virtio based memory devices */ 1519 } 1520 1521 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1522 DeviceState *dev, Error **errp) 1523 { 1524 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1525 pc_memory_pre_plug(hotplug_dev, dev, errp); 1526 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1527 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1528 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1529 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1530 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1531 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1532 /* Declare the APIC range as the reserved MSI region */ 1533 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1534 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1535 1536 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1537 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1538 resv_prop_str, errp); 1539 g_free(resv_prop_str); 1540 } 1541 1542 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1543 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1544 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1545 1546 if (pcms->iommu) { 1547 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1548 "for x86 yet."); 1549 return; 1550 } 1551 pcms->iommu = dev; 1552 } 1553 } 1554 1555 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1556 DeviceState *dev, Error **errp) 1557 { 1558 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1559 pc_memory_plug(hotplug_dev, dev, errp); 1560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1561 x86_cpu_plug(hotplug_dev, dev, errp); 1562 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1563 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1564 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1565 } 1566 } 1567 1568 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1569 DeviceState *dev, Error **errp) 1570 { 1571 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1572 pc_memory_unplug_request(hotplug_dev, dev, errp); 1573 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1574 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1575 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1576 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1577 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1578 } else { 1579 error_setg(errp, "acpi: device unplug request for not supported device" 1580 " type: %s", object_get_typename(OBJECT(dev))); 1581 } 1582 } 1583 1584 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1585 DeviceState *dev, Error **errp) 1586 { 1587 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1588 pc_memory_unplug(hotplug_dev, dev, errp); 1589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1590 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1591 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1592 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1593 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1594 } else { 1595 error_setg(errp, "acpi: device unplug for not supported device" 1596 " type: %s", object_get_typename(OBJECT(dev))); 1597 } 1598 } 1599 1600 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1601 DeviceState *dev) 1602 { 1603 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1604 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1605 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1606 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1607 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1608 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1609 return HOTPLUG_HANDLER(machine); 1610 } 1611 1612 return NULL; 1613 } 1614 1615 static void 1616 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1617 const char *name, void *opaque, 1618 Error **errp) 1619 { 1620 MachineState *ms = MACHINE(obj); 1621 int64_t value = 0; 1622 1623 if (ms->device_memory) { 1624 value = memory_region_size(&ms->device_memory->mr); 1625 } 1626 1627 visit_type_int(v, name, &value, errp); 1628 } 1629 1630 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1631 void *opaque, Error **errp) 1632 { 1633 PCMachineState *pcms = PC_MACHINE(obj); 1634 OnOffAuto vmport = pcms->vmport; 1635 1636 visit_type_OnOffAuto(v, name, &vmport, errp); 1637 } 1638 1639 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1640 void *opaque, Error **errp) 1641 { 1642 PCMachineState *pcms = PC_MACHINE(obj); 1643 1644 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1645 } 1646 1647 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1648 { 1649 PCMachineState *pcms = PC_MACHINE(obj); 1650 1651 return pcms->smbus_enabled; 1652 } 1653 1654 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1655 { 1656 PCMachineState *pcms = PC_MACHINE(obj); 1657 1658 pcms->smbus_enabled = value; 1659 } 1660 1661 static bool pc_machine_get_sata(Object *obj, Error **errp) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(obj); 1664 1665 return pcms->sata_enabled; 1666 } 1667 1668 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1669 { 1670 PCMachineState *pcms = PC_MACHINE(obj); 1671 1672 pcms->sata_enabled = value; 1673 } 1674 1675 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1676 { 1677 PCMachineState *pcms = PC_MACHINE(obj); 1678 1679 return pcms->hpet_enabled; 1680 } 1681 1682 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1683 { 1684 PCMachineState *pcms = PC_MACHINE(obj); 1685 1686 pcms->hpet_enabled = value; 1687 } 1688 1689 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1690 { 1691 PCMachineState *pcms = PC_MACHINE(obj); 1692 1693 return pcms->i8042_enabled; 1694 } 1695 1696 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1697 { 1698 PCMachineState *pcms = PC_MACHINE(obj); 1699 1700 pcms->i8042_enabled = value; 1701 } 1702 1703 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1704 { 1705 PCMachineState *pcms = PC_MACHINE(obj); 1706 1707 return pcms->default_bus_bypass_iommu; 1708 } 1709 1710 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1711 Error **errp) 1712 { 1713 PCMachineState *pcms = PC_MACHINE(obj); 1714 1715 pcms->default_bus_bypass_iommu = value; 1716 } 1717 1718 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1719 void *opaque, Error **errp) 1720 { 1721 PCMachineState *pcms = PC_MACHINE(obj); 1722 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1723 1724 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1725 } 1726 1727 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1728 void *opaque, Error **errp) 1729 { 1730 PCMachineState *pcms = PC_MACHINE(obj); 1731 1732 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1733 } 1734 1735 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1736 const char *name, void *opaque, 1737 Error **errp) 1738 { 1739 PCMachineState *pcms = PC_MACHINE(obj); 1740 uint64_t value = pcms->max_ram_below_4g; 1741 1742 visit_type_size(v, name, &value, errp); 1743 } 1744 1745 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1746 const char *name, void *opaque, 1747 Error **errp) 1748 { 1749 PCMachineState *pcms = PC_MACHINE(obj); 1750 uint64_t value; 1751 1752 if (!visit_type_size(v, name, &value, errp)) { 1753 return; 1754 } 1755 if (value > 4 * GiB) { 1756 error_setg(errp, 1757 "Machine option 'max-ram-below-4g=%"PRIu64 1758 "' expects size less than or equal to 4G", value); 1759 return; 1760 } 1761 1762 if (value < 1 * MiB) { 1763 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1764 "BIOS may not work with less than 1MiB", value); 1765 } 1766 1767 pcms->max_ram_below_4g = value; 1768 } 1769 1770 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1771 const char *name, void *opaque, 1772 Error **errp) 1773 { 1774 PCMachineState *pcms = PC_MACHINE(obj); 1775 uint64_t value = pcms->max_fw_size; 1776 1777 visit_type_size(v, name, &value, errp); 1778 } 1779 1780 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1781 const char *name, void *opaque, 1782 Error **errp) 1783 { 1784 PCMachineState *pcms = PC_MACHINE(obj); 1785 Error *error = NULL; 1786 uint64_t value; 1787 1788 visit_type_size(v, name, &value, &error); 1789 if (error) { 1790 error_propagate(errp, error); 1791 return; 1792 } 1793 1794 /* 1795 * We don't have a theoretically justifiable exact lower bound on the base 1796 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1797 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1798 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1799 * size. 1800 */ 1801 if (value > 16 * MiB) { 1802 error_setg(errp, 1803 "User specified max allowed firmware size %" PRIu64 " is " 1804 "greater than 16MiB. If combined firwmare size exceeds " 1805 "16MiB the system may not boot, or experience intermittent" 1806 "stability issues.", 1807 value); 1808 return; 1809 } 1810 1811 pcms->max_fw_size = value; 1812 } 1813 1814 1815 static void pc_machine_initfn(Object *obj) 1816 { 1817 PCMachineState *pcms = PC_MACHINE(obj); 1818 1819 #ifdef CONFIG_VMPORT 1820 pcms->vmport = ON_OFF_AUTO_AUTO; 1821 #else 1822 pcms->vmport = ON_OFF_AUTO_OFF; 1823 #endif /* CONFIG_VMPORT */ 1824 pcms->max_ram_below_4g = 0; /* use default */ 1825 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1826 1827 /* acpi build is enabled by default if machine supports it */ 1828 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1829 pcms->smbus_enabled = true; 1830 pcms->sata_enabled = true; 1831 pcms->i8042_enabled = true; 1832 pcms->max_fw_size = 8 * MiB; 1833 #ifdef CONFIG_HPET 1834 pcms->hpet_enabled = true; 1835 #endif 1836 pcms->default_bus_bypass_iommu = false; 1837 1838 pc_system_flash_create(pcms); 1839 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1840 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1841 OBJECT(pcms->pcspk), "audiodev"); 1842 cxl_machine_init(obj, &pcms->cxl_devices_state); 1843 } 1844 1845 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1846 { 1847 CPUState *cs; 1848 X86CPU *cpu; 1849 1850 qemu_devices_reset(reason); 1851 1852 /* Reset APIC after devices have been reset to cancel 1853 * any changes that qemu_devices_reset() might have done. 1854 */ 1855 CPU_FOREACH(cs) { 1856 cpu = X86_CPU(cs); 1857 1858 x86_cpu_after_reset(cpu); 1859 } 1860 } 1861 1862 static void pc_machine_wakeup(MachineState *machine) 1863 { 1864 cpu_synchronize_all_states(); 1865 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1866 cpu_synchronize_all_post_reset(); 1867 } 1868 1869 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1870 { 1871 X86IOMMUState *iommu = x86_iommu_get_default(); 1872 IntelIOMMUState *intel_iommu; 1873 1874 if (iommu && 1875 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1876 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1877 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1878 if (!intel_iommu->caching_mode) { 1879 error_setg(errp, "Device assignment is not allowed without " 1880 "enabling caching-mode=on for Intel IOMMU."); 1881 return false; 1882 } 1883 } 1884 1885 return true; 1886 } 1887 1888 static void pc_machine_class_init(ObjectClass *oc, void *data) 1889 { 1890 MachineClass *mc = MACHINE_CLASS(oc); 1891 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1892 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1893 1894 pcmc->pci_enabled = true; 1895 pcmc->has_acpi_build = true; 1896 pcmc->rsdp_in_ram = true; 1897 pcmc->smbios_defaults = true; 1898 pcmc->smbios_uuid_encoded = true; 1899 pcmc->gigabyte_align = true; 1900 pcmc->has_reserved_memory = true; 1901 pcmc->kvmclock_enabled = true; 1902 pcmc->enforce_aligned_dimm = true; 1903 pcmc->enforce_amd_1tb_hole = true; 1904 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1905 * to be used at the moment, 32K should be enough for a while. */ 1906 pcmc->acpi_data_size = 0x20000 + 0x8000; 1907 pcmc->pvh_enabled = true; 1908 pcmc->kvmclock_create_always = true; 1909 assert(!mc->get_hotplug_handler); 1910 mc->get_hotplug_handler = pc_get_hotplug_handler; 1911 mc->hotplug_allowed = pc_hotplug_allowed; 1912 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1913 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1914 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1915 mc->auto_enable_numa_with_memhp = true; 1916 mc->auto_enable_numa_with_memdev = true; 1917 mc->has_hotpluggable_cpus = true; 1918 mc->default_boot_order = "cad"; 1919 mc->block_default_type = IF_IDE; 1920 mc->max_cpus = 255; 1921 mc->reset = pc_machine_reset; 1922 mc->wakeup = pc_machine_wakeup; 1923 hc->pre_plug = pc_machine_device_pre_plug_cb; 1924 hc->plug = pc_machine_device_plug_cb; 1925 hc->unplug_request = pc_machine_device_unplug_request_cb; 1926 hc->unplug = pc_machine_device_unplug_cb; 1927 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1928 mc->nvdimm_supported = true; 1929 mc->smp_props.dies_supported = true; 1930 mc->default_ram_id = "pc.ram"; 1931 1932 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1933 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1934 NULL, NULL); 1935 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1936 "Maximum ram below the 4G boundary (32bit boundary)"); 1937 1938 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1939 pc_machine_get_device_memory_region_size, NULL, 1940 NULL, NULL); 1941 1942 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1943 pc_machine_get_vmport, pc_machine_set_vmport, 1944 NULL, NULL); 1945 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1946 "Enable vmport (pc & q35)"); 1947 1948 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1949 pc_machine_get_smbus, pc_machine_set_smbus); 1950 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1951 "Enable/disable system management bus"); 1952 1953 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1954 pc_machine_get_sata, pc_machine_set_sata); 1955 object_class_property_set_description(oc, PC_MACHINE_SATA, 1956 "Enable/disable Serial ATA bus"); 1957 1958 object_class_property_add_bool(oc, "hpet", 1959 pc_machine_get_hpet, pc_machine_set_hpet); 1960 object_class_property_set_description(oc, "hpet", 1961 "Enable/disable high precision event timer emulation"); 1962 1963 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1964 pc_machine_get_i8042, pc_machine_set_i8042); 1965 1966 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1967 pc_machine_get_default_bus_bypass_iommu, 1968 pc_machine_set_default_bus_bypass_iommu); 1969 1970 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1971 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1972 NULL, NULL); 1973 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1974 "Maximum combined firmware size"); 1975 1976 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1977 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1978 NULL, NULL); 1979 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1980 "SMBIOS Entry Point type [32, 64]"); 1981 } 1982 1983 static const TypeInfo pc_machine_info = { 1984 .name = TYPE_PC_MACHINE, 1985 .parent = TYPE_X86_MACHINE, 1986 .abstract = true, 1987 .instance_size = sizeof(PCMachineState), 1988 .instance_init = pc_machine_initfn, 1989 .class_size = sizeof(PCMachineClass), 1990 .class_init = pc_machine_class_init, 1991 .interfaces = (InterfaceInfo[]) { 1992 { TYPE_HOTPLUG_HANDLER }, 1993 { } 1994 }, 1995 }; 1996 1997 static void pc_machine_register_types(void) 1998 { 1999 type_register_static(&pc_machine_info); 2000 } 2001 2002 type_init(pc_machine_register_types)