fw_cfg.c (7626B)
1 /* 2 * QEMU fw_cfg helpers (X86 specific) 3 * 4 * Copyright (c) 2019 Red Hat, Inc. 5 * 6 * Author: 7 * Philippe Mathieu-Daudé <philmd@redhat.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0-or-later 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "sysemu/numa.h" 17 #include "hw/acpi/acpi.h" 18 #include "hw/acpi/aml-build.h" 19 #include "hw/firmware/smbios.h" 20 #include "hw/i386/fw_cfg.h" 21 #include "hw/timer/hpet.h" 22 #include "hw/nvram/fw_cfg.h" 23 #include "e820_memory_layout.h" 24 #include "kvm/kvm_i386.h" 25 #include "qapi/error.h" 26 #include CONFIG_DEVICES 27 28 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 29 30 const char *fw_cfg_arch_key_name(uint16_t key) 31 { 32 static const struct { 33 uint16_t key; 34 const char *name; 35 } fw_cfg_arch_wellknown_keys[] = { 36 {FW_CFG_ACPI_TABLES, "acpi_tables"}, 37 {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"}, 38 {FW_CFG_IRQ0_OVERRIDE, "irq0_override"}, 39 {FW_CFG_HPET, "hpet"}, 40 }; 41 42 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 43 if (fw_cfg_arch_wellknown_keys[i].key == key) { 44 return fw_cfg_arch_wellknown_keys[i].name; 45 } 46 } 47 return NULL; 48 } 49 50 void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg) 51 { 52 #ifdef CONFIG_SMBIOS 53 uint8_t *smbios_tables, *smbios_anchor; 54 size_t smbios_tables_len, smbios_anchor_len; 55 struct smbios_phys_mem_area *mem_array; 56 unsigned i, array_count; 57 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 58 59 /* tell smbios about cpuid version and features */ 60 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 61 62 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); 63 if (smbios_tables) { 64 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 65 smbios_tables, smbios_tables_len); 66 } 67 68 /* build the array of physical mem area from e820 table */ 69 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 70 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 71 uint64_t addr, len; 72 73 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 74 mem_array[array_count].address = addr; 75 mem_array[array_count].length = len; 76 array_count++; 77 } 78 } 79 smbios_get_tables(ms, mem_array, array_count, 80 &smbios_tables, &smbios_tables_len, 81 &smbios_anchor, &smbios_anchor_len, 82 &error_fatal); 83 g_free(mem_array); 84 85 if (smbios_anchor) { 86 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 87 smbios_tables, smbios_tables_len); 88 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 89 smbios_anchor, smbios_anchor_len); 90 } 91 #endif 92 } 93 94 FWCfgState *fw_cfg_arch_create(MachineState *ms, 95 uint16_t boot_cpus, 96 uint16_t apic_id_limit) 97 { 98 FWCfgState *fw_cfg; 99 uint64_t *numa_fw_cfg; 100 int i; 101 MachineClass *mc = MACHINE_GET_CLASS(ms); 102 const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms); 103 int nb_numa_nodes = ms->numa_state->num_nodes; 104 105 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 106 &address_space_memory); 107 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus); 108 109 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 110 * 111 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 112 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 113 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 114 * for CPU hotplug also uses APIC ID and not "CPU index". 115 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 116 * but the "limit to the APIC ID values SeaBIOS may see". 117 * 118 * So for compatibility reasons with old BIOSes we are stuck with 119 * "etc/max-cpus" actually being apic_id_limit 120 */ 121 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit); 122 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size); 123 #ifdef CONFIG_ACPI 124 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 125 acpi_tables, acpi_tables_len); 126 #endif 127 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1); 128 129 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 130 sizeof(struct e820_entry) * e820_get_num_entries()); 131 132 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 133 /* allocate memory for the NUMA channel: one (64bit) word for the number 134 * of nodes, one word for each VCPU->node and one word for each node to 135 * hold the amount of memory. 136 */ 137 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 138 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 139 for (i = 0; i < cpus->len; i++) { 140 unsigned int apic_id = cpus->cpus[i].arch_id; 141 assert(apic_id < apic_id_limit); 142 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 143 } 144 for (i = 0; i < nb_numa_nodes; i++) { 145 numa_fw_cfg[apic_id_limit + 1 + i] = 146 cpu_to_le64(ms->numa_state->nodes[i].node_mem); 147 } 148 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 149 (1 + apic_id_limit + nb_numa_nodes) * 150 sizeof(*numa_fw_cfg)); 151 152 return fw_cfg; 153 } 154 155 void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) 156 { 157 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 158 CPUX86State *env = &cpu->env; 159 uint32_t unused, ebx, ecx, edx; 160 uint64_t feature_control_bits = 0; 161 uint64_t *val; 162 163 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 164 if (ecx & CPUID_EXT_VMX) { 165 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 166 } 167 168 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 169 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 170 (env->mcg_cap & MCG_LMCE_P)) { 171 feature_control_bits |= FEATURE_CONTROL_LMCE; 172 } 173 174 if (env->cpuid_level >= 7) { 175 cpu_x86_cpuid(env, 0x7, 0, &unused, &ebx, &ecx, &unused); 176 if (ebx & CPUID_7_0_EBX_SGX) { 177 feature_control_bits |= FEATURE_CONTROL_SGX; 178 } 179 if (ecx & CPUID_7_0_ECX_SGX_LC) { 180 feature_control_bits |= FEATURE_CONTROL_SGX_LC; 181 } 182 } 183 184 if (!feature_control_bits) { 185 return; 186 } 187 188 val = g_malloc(sizeof(*val)); 189 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 190 fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 191 } 192 193 void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) 194 { 195 /* 196 * when using port i/o, the 8-bit data register *always* overlaps 197 * with half of the 16-bit control register. Hence, the total size 198 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 199 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 200 */ 201 Object *obj = OBJECT(fw_cfg); 202 uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? 203 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 204 FW_CFG_CTL_SIZE; 205 Aml *dev = aml_device("FWCF"); 206 Aml *crs = aml_resource_template(); 207 208 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 209 210 /* device present, functioning, decoding, not shown in UI */ 211 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 212 213 aml_append(crs, 214 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)); 215 216 aml_append(dev, aml_name_decl("_CRS", crs)); 217 aml_append(scope, dev); 218 }