smbus_eeprom.c (9302B)
1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/boards.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "hw/i2c/smbus_eeprom.h" 34 #include "qom/object.h" 35 36 //#define DEBUG 37 38 #define TYPE_SMBUS_EEPROM "smbus-eeprom" 39 40 OBJECT_DECLARE_SIMPLE_TYPE(SMBusEEPROMDevice, SMBUS_EEPROM) 41 42 #define SMBUS_EEPROM_SIZE 256 43 44 struct SMBusEEPROMDevice { 45 SMBusDevice smbusdev; 46 uint8_t data[SMBUS_EEPROM_SIZE]; 47 uint8_t *init_data; 48 uint8_t offset; 49 bool accessed; 50 }; 51 52 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 53 { 54 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 55 uint8_t *data = eeprom->data; 56 uint8_t val = data[eeprom->offset++]; 57 58 eeprom->accessed = true; 59 #ifdef DEBUG 60 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 61 dev->i2c.address, val); 62 #endif 63 return val; 64 } 65 66 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 67 { 68 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 69 uint8_t *data = eeprom->data; 70 71 eeprom->accessed = true; 72 #ifdef DEBUG 73 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 74 dev->i2c.address, buf[0], buf[1]); 75 #endif 76 /* len is guaranteed to be > 0 */ 77 eeprom->offset = buf[0]; 78 buf++; 79 len--; 80 81 for (; len > 0; len--) { 82 data[eeprom->offset] = *buf++; 83 eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE; 84 } 85 86 return 0; 87 } 88 89 static bool smbus_eeprom_vmstate_needed(void *opaque) 90 { 91 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 92 SMBusEEPROMDevice *eeprom = opaque; 93 94 return (eeprom->accessed || smbus_vmstate_needed(&eeprom->smbusdev)) && 95 !mc->smbus_no_migration_support; 96 } 97 98 static const VMStateDescription vmstate_smbus_eeprom = { 99 .name = "smbus-eeprom", 100 .version_id = 1, 101 .minimum_version_id = 1, 102 .needed = smbus_eeprom_vmstate_needed, 103 .fields = (VMStateField[]) { 104 VMSTATE_SMBUS_DEVICE(smbusdev, SMBusEEPROMDevice), 105 VMSTATE_UINT8_ARRAY(data, SMBusEEPROMDevice, SMBUS_EEPROM_SIZE), 106 VMSTATE_UINT8(offset, SMBusEEPROMDevice), 107 VMSTATE_BOOL(accessed, SMBusEEPROMDevice), 108 VMSTATE_END_OF_LIST() 109 } 110 }; 111 112 /* 113 * Reset the EEPROM contents to the initial state on a reset. This 114 * isn't really how an EEPROM works, of course, but the general 115 * principle of QEMU is to restore function on reset to what it would 116 * be if QEMU was stopped and started. 117 * 118 * The proper thing to do would be to have a backing blockdev to hold 119 * the contents and restore that on startup, and not do this on reset. 120 * But until that time, act as if we had been stopped and restarted. 121 */ 122 static void smbus_eeprom_reset(DeviceState *dev) 123 { 124 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 125 126 memcpy(eeprom->data, eeprom->init_data, SMBUS_EEPROM_SIZE); 127 eeprom->offset = 0; 128 } 129 130 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 131 { 132 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); 133 134 smbus_eeprom_reset(dev); 135 if (eeprom->init_data == NULL) { 136 error_setg(errp, "init_data cannot be NULL"); 137 } 138 } 139 140 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 141 { 142 DeviceClass *dc = DEVICE_CLASS(klass); 143 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 144 145 dc->realize = smbus_eeprom_realize; 146 dc->reset = smbus_eeprom_reset; 147 sc->receive_byte = eeprom_receive_byte; 148 sc->write_data = eeprom_write_data; 149 dc->vmsd = &vmstate_smbus_eeprom; 150 /* Reason: init_data */ 151 dc->user_creatable = false; 152 } 153 154 static const TypeInfo smbus_eeprom_info = { 155 .name = TYPE_SMBUS_EEPROM, 156 .parent = TYPE_SMBUS_DEVICE, 157 .instance_size = sizeof(SMBusEEPROMDevice), 158 .class_init = smbus_eeprom_class_initfn, 159 }; 160 161 static void smbus_eeprom_register_types(void) 162 { 163 type_register_static(&smbus_eeprom_info); 164 } 165 166 type_init(smbus_eeprom_register_types) 167 168 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 169 { 170 DeviceState *dev; 171 172 dev = qdev_new(TYPE_SMBUS_EEPROM); 173 qdev_prop_set_uint8(dev, "address", address); 174 /* FIXME: use an array of byte or block backend property? */ 175 SMBUS_EEPROM(dev)->init_data = eeprom_buf; 176 qdev_realize_and_unref(dev, (BusState *)smbus, &error_fatal); 177 } 178 179 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 180 const uint8_t *eeprom_spd, int eeprom_spd_size) 181 { 182 int i; 183 /* XXX: make this persistent */ 184 185 assert(nb_eeprom <= 8); 186 uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE); 187 if (eeprom_spd_size > 0) { 188 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 189 } 190 191 for (i = 0; i < nb_eeprom; i++) { 192 smbus_eeprom_init_one(smbus, 0x50 + i, 193 eeprom_buf + (i * SMBUS_EEPROM_SIZE)); 194 } 195 } 196 197 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 198 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size) 199 { 200 uint8_t *spd; 201 uint8_t nbanks; 202 uint16_t density; 203 uint32_t size; 204 int min_log2, max_log2, sz_log2; 205 int i; 206 207 switch (type) { 208 case SDR: 209 min_log2 = 2; 210 max_log2 = 9; 211 break; 212 case DDR: 213 min_log2 = 5; 214 max_log2 = 12; 215 break; 216 case DDR2: 217 min_log2 = 7; 218 max_log2 = 14; 219 break; 220 default: 221 g_assert_not_reached(); 222 } 223 size = ram_size >> 20; /* work in terms of megabytes */ 224 sz_log2 = 31 - clz32(size); 225 size = 1U << sz_log2; 226 assert(ram_size == size * MiB); 227 assert(sz_log2 >= min_log2); 228 229 nbanks = 1; 230 while (sz_log2 > max_log2 && nbanks < 8) { 231 sz_log2--; 232 nbanks *= 2; 233 } 234 235 assert(size == (1ULL << sz_log2) * nbanks); 236 237 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 238 if (nbanks == 1 && sz_log2 > min_log2) { 239 sz_log2--; 240 nbanks++; 241 } 242 243 density = 1ULL << (sz_log2 - 2); 244 switch (type) { 245 case DDR2: 246 density = (density & 0xe0) | (density >> 8 & 0x1f); 247 break; 248 case DDR: 249 density = (density & 0xf8) | (density >> 8 & 0x07); 250 break; 251 case SDR: 252 default: 253 density &= 0xff; 254 break; 255 } 256 257 spd = g_malloc0(256); 258 spd[0] = 128; /* data bytes in EEPROM */ 259 spd[1] = 8; /* log2 size of EEPROM */ 260 spd[2] = type; 261 spd[3] = 13; /* row address bits */ 262 spd[4] = 10; /* column address bits */ 263 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 264 spd[6] = 64; /* module data width */ 265 /* reserved / data width high */ 266 spd[8] = 4; /* interface voltage level */ 267 spd[9] = 0x25; /* highest CAS latency */ 268 spd[10] = 1; /* access time */ 269 /* DIMM configuration 0 = non-ECC */ 270 spd[12] = 0x82; /* refresh requirements */ 271 spd[13] = 8; /* primary SDRAM width */ 272 /* ECC SDRAM width */ 273 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 274 spd[16] = 12; /* burst lengths supported */ 275 spd[17] = 4; /* banks per SDRAM device */ 276 spd[18] = 12; /* ~CAS latencies supported */ 277 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 278 spd[20] = 2; /* DIMM type / ~WE latencies */ 279 spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */ 280 /* memory chip features */ 281 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 282 /* data access time */ 283 /* clock cycle time @ short CAS latency */ 284 /* data access time */ 285 spd[27] = 20; /* min. row precharge time */ 286 spd[28] = 15; /* min. row active row delay */ 287 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 288 spd[30] = 45; /* min. active to precharge time */ 289 spd[31] = density; 290 spd[32] = 20; /* addr/cmd setup time */ 291 spd[33] = 8; /* addr/cmd hold time */ 292 spd[34] = 20; /* data input setup time */ 293 spd[35] = 8; /* data input hold time */ 294 295 /* checksum */ 296 for (i = 0; i < 63; i++) { 297 spd[63] += spd[i]; 298 } 299 return spd; 300 }