omap_gpio.c (20851B)
1 /* 2 * TI OMAP processors GPIO emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * Copyright (C) 2007-2009 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/log.h" 23 #include "hw/irq.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/arm/omap.h" 26 #include "hw/sysbus.h" 27 #include "qemu/error-report.h" 28 #include "qemu/module.h" 29 #include "qapi/error.h" 30 31 struct omap_gpio_s { 32 qemu_irq irq; 33 qemu_irq handler[16]; 34 35 uint16_t inputs; 36 uint16_t outputs; 37 uint16_t dir; 38 uint16_t edge; 39 uint16_t mask; 40 uint16_t ints; 41 uint16_t pins; 42 }; 43 44 struct omap_gpif_s { 45 SysBusDevice parent_obj; 46 47 MemoryRegion iomem; 48 int mpu_model; 49 void *clk; 50 struct omap_gpio_s omap1; 51 }; 52 53 /* General-Purpose I/O of OMAP1 */ 54 static void omap_gpio_set(void *opaque, int line, int level) 55 { 56 struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1; 57 uint16_t prev = s->inputs; 58 59 if (level) 60 s->inputs |= 1 << line; 61 else 62 s->inputs &= ~(1 << line); 63 64 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & 65 (1 << line) & s->dir & ~s->mask) { 66 s->ints |= 1 << line; 67 qemu_irq_raise(s->irq); 68 } 69 } 70 71 static uint64_t omap_gpio_read(void *opaque, hwaddr addr, 72 unsigned size) 73 { 74 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; 75 int offset = addr & OMAP_MPUI_REG_MASK; 76 77 if (size != 2) { 78 return omap_badwidth_read16(opaque, addr); 79 } 80 81 switch (offset) { 82 case 0x00: /* DATA_INPUT */ 83 return s->inputs & s->pins; 84 85 case 0x04: /* DATA_OUTPUT */ 86 return s->outputs; 87 88 case 0x08: /* DIRECTION_CONTROL */ 89 return s->dir; 90 91 case 0x0c: /* INTERRUPT_CONTROL */ 92 return s->edge; 93 94 case 0x10: /* INTERRUPT_MASK */ 95 return s->mask; 96 97 case 0x14: /* INTERRUPT_STATUS */ 98 return s->ints; 99 100 case 0x18: /* PIN_CONTROL (not in OMAP310) */ 101 OMAP_BAD_REG(addr); 102 return s->pins; 103 } 104 105 OMAP_BAD_REG(addr); 106 return 0; 107 } 108 109 static void omap_gpio_write(void *opaque, hwaddr addr, 110 uint64_t value, unsigned size) 111 { 112 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; 113 int offset = addr & OMAP_MPUI_REG_MASK; 114 uint16_t diff; 115 int ln; 116 117 if (size != 2) { 118 omap_badwidth_write16(opaque, addr, value); 119 return; 120 } 121 122 switch (offset) { 123 case 0x00: /* DATA_INPUT */ 124 OMAP_RO_REG(addr); 125 return; 126 127 case 0x04: /* DATA_OUTPUT */ 128 diff = (s->outputs ^ value) & ~s->dir; 129 s->outputs = value; 130 while ((ln = ctz32(diff)) != 32) { 131 if (s->handler[ln]) 132 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 133 diff &= ~(1 << ln); 134 } 135 break; 136 137 case 0x08: /* DIRECTION_CONTROL */ 138 diff = s->outputs & (s->dir ^ value); 139 s->dir = value; 140 141 value = s->outputs & ~s->dir; 142 while ((ln = ctz32(diff)) != 32) { 143 if (s->handler[ln]) 144 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 145 diff &= ~(1 << ln); 146 } 147 break; 148 149 case 0x0c: /* INTERRUPT_CONTROL */ 150 s->edge = value; 151 break; 152 153 case 0x10: /* INTERRUPT_MASK */ 154 s->mask = value; 155 break; 156 157 case 0x14: /* INTERRUPT_STATUS */ 158 s->ints &= ~value; 159 if (!s->ints) 160 qemu_irq_lower(s->irq); 161 break; 162 163 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ 164 OMAP_BAD_REG(addr); 165 s->pins = value; 166 break; 167 168 default: 169 OMAP_BAD_REG(addr); 170 return; 171 } 172 } 173 174 /* *Some* sources say the memory region is 32-bit. */ 175 static const MemoryRegionOps omap_gpio_ops = { 176 .read = omap_gpio_read, 177 .write = omap_gpio_write, 178 .endianness = DEVICE_NATIVE_ENDIAN, 179 }; 180 181 static void omap_gpio_reset(struct omap_gpio_s *s) 182 { 183 s->inputs = 0; 184 s->outputs = ~0; 185 s->dir = ~0; 186 s->edge = ~0; 187 s->mask = ~0; 188 s->ints = 0; 189 s->pins = ~0; 190 } 191 192 struct omap2_gpio_s { 193 qemu_irq irq[2]; 194 qemu_irq wkup; 195 qemu_irq *handler; 196 MemoryRegion iomem; 197 198 uint8_t revision; 199 uint8_t config[2]; 200 uint32_t inputs; 201 uint32_t outputs; 202 uint32_t dir; 203 uint32_t level[2]; 204 uint32_t edge[2]; 205 uint32_t mask[2]; 206 uint32_t wumask; 207 uint32_t ints[2]; 208 uint32_t debounce; 209 uint8_t delay; 210 }; 211 212 struct omap2_gpif_s { 213 SysBusDevice parent_obj; 214 215 MemoryRegion iomem; 216 int mpu_model; 217 void *iclk; 218 void *fclk[6]; 219 int modulecount; 220 struct omap2_gpio_s *modules; 221 qemu_irq *handler; 222 int autoidle; 223 int gpo; 224 }; 225 226 /* General-Purpose Interface of OMAP2/3 */ 227 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s, 228 int line) 229 { 230 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); 231 } 232 233 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line) 234 { 235 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ 236 return; 237 if (!(s->config[0] & (3 << 3))) /* Force Idle */ 238 return; 239 if (!(s->wumask & (1 << line))) 240 return; 241 242 qemu_irq_raise(s->wkup); 243 } 244 245 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s, 246 uint32_t diff) 247 { 248 int ln; 249 250 s->outputs ^= diff; 251 diff &= ~s->dir; 252 while ((ln = ctz32(diff)) != 32) { 253 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); 254 diff &= ~(1 << ln); 255 } 256 } 257 258 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line) 259 { 260 s->ints[line] |= s->dir & 261 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); 262 omap2_gpio_module_int_update(s, line); 263 } 264 265 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line) 266 { 267 s->ints[0] |= 1 << line; 268 omap2_gpio_module_int_update(s, 0); 269 s->ints[1] |= 1 << line; 270 omap2_gpio_module_int_update(s, 1); 271 omap2_gpio_module_wake(s, line); 272 } 273 274 static void omap2_gpio_set(void *opaque, int line, int level) 275 { 276 struct omap2_gpif_s *p = opaque; 277 struct omap2_gpio_s *s = &p->modules[line >> 5]; 278 279 line &= 31; 280 if (level) { 281 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) 282 omap2_gpio_module_int(s, line); 283 s->inputs |= 1 << line; 284 } else { 285 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) 286 omap2_gpio_module_int(s, line); 287 s->inputs &= ~(1 << line); 288 } 289 } 290 291 static void omap2_gpio_module_reset(struct omap2_gpio_s *s) 292 { 293 s->config[0] = 0; 294 s->config[1] = 2; 295 s->ints[0] = 0; 296 s->ints[1] = 0; 297 s->mask[0] = 0; 298 s->mask[1] = 0; 299 s->wumask = 0; 300 s->dir = ~0; 301 s->level[0] = 0; 302 s->level[1] = 0; 303 s->edge[0] = 0; 304 s->edge[1] = 0; 305 s->debounce = 0; 306 s->delay = 0; 307 } 308 309 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) 310 { 311 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; 312 313 switch (addr) { 314 case 0x00: /* GPIO_REVISION */ 315 return s->revision; 316 317 case 0x10: /* GPIO_SYSCONFIG */ 318 return s->config[0]; 319 320 case 0x14: /* GPIO_SYSSTATUS */ 321 return 0x01; 322 323 case 0x18: /* GPIO_IRQSTATUS1 */ 324 return s->ints[0]; 325 326 case 0x1c: /* GPIO_IRQENABLE1 */ 327 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 328 case 0x64: /* GPIO_SETIRQENABLE1 */ 329 return s->mask[0]; 330 331 case 0x20: /* GPIO_WAKEUPENABLE */ 332 case 0x80: /* GPIO_CLEARWKUENA */ 333 case 0x84: /* GPIO_SETWKUENA */ 334 return s->wumask; 335 336 case 0x28: /* GPIO_IRQSTATUS2 */ 337 return s->ints[1]; 338 339 case 0x2c: /* GPIO_IRQENABLE2 */ 340 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 341 case 0x74: /* GPIO_SETIREQNEABLE2 */ 342 return s->mask[1]; 343 344 case 0x30: /* GPIO_CTRL */ 345 return s->config[1]; 346 347 case 0x34: /* GPIO_OE */ 348 return s->dir; 349 350 case 0x38: /* GPIO_DATAIN */ 351 return s->inputs; 352 353 case 0x3c: /* GPIO_DATAOUT */ 354 case 0x90: /* GPIO_CLEARDATAOUT */ 355 case 0x94: /* GPIO_SETDATAOUT */ 356 return s->outputs; 357 358 case 0x40: /* GPIO_LEVELDETECT0 */ 359 return s->level[0]; 360 361 case 0x44: /* GPIO_LEVELDETECT1 */ 362 return s->level[1]; 363 364 case 0x48: /* GPIO_RISINGDETECT */ 365 return s->edge[0]; 366 367 case 0x4c: /* GPIO_FALLINGDETECT */ 368 return s->edge[1]; 369 370 case 0x50: /* GPIO_DEBOUNCENABLE */ 371 return s->debounce; 372 373 case 0x54: /* GPIO_DEBOUNCINGTIME */ 374 return s->delay; 375 } 376 377 OMAP_BAD_REG(addr); 378 return 0; 379 } 380 381 static void omap2_gpio_module_write(void *opaque, hwaddr addr, 382 uint32_t value) 383 { 384 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; 385 uint32_t diff; 386 int ln; 387 388 switch (addr) { 389 case 0x00: /* GPIO_REVISION */ 390 case 0x14: /* GPIO_SYSSTATUS */ 391 case 0x38: /* GPIO_DATAIN */ 392 OMAP_RO_REG(addr); 393 break; 394 395 case 0x10: /* GPIO_SYSCONFIG */ 396 if (((value >> 3) & 3) == 3) { 397 qemu_log_mask(LOG_GUEST_ERROR, 398 "%s: Illegal IDLEMODE value: 3\n", __func__); 399 } 400 if (value & 2) 401 omap2_gpio_module_reset(s); 402 s->config[0] = value & 0x1d; 403 break; 404 405 case 0x18: /* GPIO_IRQSTATUS1 */ 406 if (s->ints[0] & value) { 407 s->ints[0] &= ~value; 408 omap2_gpio_module_level_update(s, 0); 409 } 410 break; 411 412 case 0x1c: /* GPIO_IRQENABLE1 */ 413 s->mask[0] = value; 414 omap2_gpio_module_int_update(s, 0); 415 break; 416 417 case 0x20: /* GPIO_WAKEUPENABLE */ 418 s->wumask = value; 419 break; 420 421 case 0x28: /* GPIO_IRQSTATUS2 */ 422 if (s->ints[1] & value) { 423 s->ints[1] &= ~value; 424 omap2_gpio_module_level_update(s, 1); 425 } 426 break; 427 428 case 0x2c: /* GPIO_IRQENABLE2 */ 429 s->mask[1] = value; 430 omap2_gpio_module_int_update(s, 1); 431 break; 432 433 case 0x30: /* GPIO_CTRL */ 434 s->config[1] = value & 7; 435 break; 436 437 case 0x34: /* GPIO_OE */ 438 diff = s->outputs & (s->dir ^ value); 439 s->dir = value; 440 441 value = s->outputs & ~s->dir; 442 while ((ln = ctz32(diff)) != 32) { 443 diff &= ~(1 << ln); 444 qemu_set_irq(s->handler[ln], (value >> ln) & 1); 445 } 446 447 omap2_gpio_module_level_update(s, 0); 448 omap2_gpio_module_level_update(s, 1); 449 break; 450 451 case 0x3c: /* GPIO_DATAOUT */ 452 omap2_gpio_module_out_update(s, s->outputs ^ value); 453 break; 454 455 case 0x40: /* GPIO_LEVELDETECT0 */ 456 s->level[0] = value; 457 omap2_gpio_module_level_update(s, 0); 458 omap2_gpio_module_level_update(s, 1); 459 break; 460 461 case 0x44: /* GPIO_LEVELDETECT1 */ 462 s->level[1] = value; 463 omap2_gpio_module_level_update(s, 0); 464 omap2_gpio_module_level_update(s, 1); 465 break; 466 467 case 0x48: /* GPIO_RISINGDETECT */ 468 s->edge[0] = value; 469 break; 470 471 case 0x4c: /* GPIO_FALLINGDETECT */ 472 s->edge[1] = value; 473 break; 474 475 case 0x50: /* GPIO_DEBOUNCENABLE */ 476 s->debounce = value; 477 break; 478 479 case 0x54: /* GPIO_DEBOUNCINGTIME */ 480 s->delay = value; 481 break; 482 483 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 484 s->mask[0] &= ~value; 485 omap2_gpio_module_int_update(s, 0); 486 break; 487 488 case 0x64: /* GPIO_SETIRQENABLE1 */ 489 s->mask[0] |= value; 490 omap2_gpio_module_int_update(s, 0); 491 break; 492 493 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 494 s->mask[1] &= ~value; 495 omap2_gpio_module_int_update(s, 1); 496 break; 497 498 case 0x74: /* GPIO_SETIREQNEABLE2 */ 499 s->mask[1] |= value; 500 omap2_gpio_module_int_update(s, 1); 501 break; 502 503 case 0x80: /* GPIO_CLEARWKUENA */ 504 s->wumask &= ~value; 505 break; 506 507 case 0x84: /* GPIO_SETWKUENA */ 508 s->wumask |= value; 509 break; 510 511 case 0x90: /* GPIO_CLEARDATAOUT */ 512 omap2_gpio_module_out_update(s, s->outputs & value); 513 break; 514 515 case 0x94: /* GPIO_SETDATAOUT */ 516 omap2_gpio_module_out_update(s, ~s->outputs & value); 517 break; 518 519 default: 520 OMAP_BAD_REG(addr); 521 return; 522 } 523 } 524 525 static uint64_t omap2_gpio_module_readp(void *opaque, hwaddr addr, 526 unsigned size) 527 { 528 return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3); 529 } 530 531 static void omap2_gpio_module_writep(void *opaque, hwaddr addr, 532 uint64_t value, unsigned size) 533 { 534 uint32_t cur = 0; 535 uint32_t mask = 0xffff; 536 537 if (size == 4) { 538 omap2_gpio_module_write(opaque, addr, value); 539 return; 540 } 541 542 switch (addr & ~3) { 543 case 0x00: /* GPIO_REVISION */ 544 case 0x14: /* GPIO_SYSSTATUS */ 545 case 0x38: /* GPIO_DATAIN */ 546 OMAP_RO_REG(addr); 547 break; 548 549 case 0x10: /* GPIO_SYSCONFIG */ 550 case 0x1c: /* GPIO_IRQENABLE1 */ 551 case 0x20: /* GPIO_WAKEUPENABLE */ 552 case 0x2c: /* GPIO_IRQENABLE2 */ 553 case 0x30: /* GPIO_CTRL */ 554 case 0x34: /* GPIO_OE */ 555 case 0x3c: /* GPIO_DATAOUT */ 556 case 0x40: /* GPIO_LEVELDETECT0 */ 557 case 0x44: /* GPIO_LEVELDETECT1 */ 558 case 0x48: /* GPIO_RISINGDETECT */ 559 case 0x4c: /* GPIO_FALLINGDETECT */ 560 case 0x50: /* GPIO_DEBOUNCENABLE */ 561 case 0x54: /* GPIO_DEBOUNCINGTIME */ 562 cur = omap2_gpio_module_read(opaque, addr & ~3) & 563 ~(mask << ((addr & 3) << 3)); 564 565 /* Fall through. */ 566 case 0x18: /* GPIO_IRQSTATUS1 */ 567 case 0x28: /* GPIO_IRQSTATUS2 */ 568 case 0x60: /* GPIO_CLEARIRQENABLE1 */ 569 case 0x64: /* GPIO_SETIRQENABLE1 */ 570 case 0x70: /* GPIO_CLEARIRQENABLE2 */ 571 case 0x74: /* GPIO_SETIREQNEABLE2 */ 572 case 0x80: /* GPIO_CLEARWKUENA */ 573 case 0x84: /* GPIO_SETWKUENA */ 574 case 0x90: /* GPIO_CLEARDATAOUT */ 575 case 0x94: /* GPIO_SETDATAOUT */ 576 value <<= (addr & 3) << 3; 577 omap2_gpio_module_write(opaque, addr, cur | value); 578 break; 579 580 default: 581 OMAP_BAD_REG(addr); 582 return; 583 } 584 } 585 586 static const MemoryRegionOps omap2_gpio_module_ops = { 587 .read = omap2_gpio_module_readp, 588 .write = omap2_gpio_module_writep, 589 .valid.min_access_size = 1, 590 .valid.max_access_size = 4, 591 .endianness = DEVICE_NATIVE_ENDIAN, 592 }; 593 594 static void omap_gpif_reset(DeviceState *dev) 595 { 596 struct omap_gpif_s *s = OMAP1_GPIO(dev); 597 598 omap_gpio_reset(&s->omap1); 599 } 600 601 static void omap2_gpif_reset(DeviceState *dev) 602 { 603 struct omap2_gpif_s *s = OMAP2_GPIO(dev); 604 int i; 605 606 for (i = 0; i < s->modulecount; i++) { 607 omap2_gpio_module_reset(&s->modules[i]); 608 } 609 s->autoidle = 0; 610 s->gpo = 0; 611 } 612 613 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, 614 unsigned size) 615 { 616 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; 617 618 switch (addr) { 619 case 0x00: /* IPGENERICOCPSPL_REVISION */ 620 return 0x18; 621 622 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 623 return s->autoidle; 624 625 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 626 return 0x01; 627 628 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 629 return 0x00; 630 631 case 0x40: /* IPGENERICOCPSPL_GPO */ 632 return s->gpo; 633 634 case 0x50: /* IPGENERICOCPSPL_GPI */ 635 return 0x00; 636 } 637 638 OMAP_BAD_REG(addr); 639 return 0; 640 } 641 642 static void omap2_gpif_top_write(void *opaque, hwaddr addr, 643 uint64_t value, unsigned size) 644 { 645 struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; 646 647 switch (addr) { 648 case 0x00: /* IPGENERICOCPSPL_REVISION */ 649 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ 650 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ 651 case 0x50: /* IPGENERICOCPSPL_GPI */ 652 OMAP_RO_REG(addr); 653 break; 654 655 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ 656 if (value & (1 << 1)) /* SOFTRESET */ 657 omap2_gpif_reset(DEVICE(s)); 658 s->autoidle = value & 1; 659 break; 660 661 case 0x40: /* IPGENERICOCPSPL_GPO */ 662 s->gpo = value & 1; 663 break; 664 665 default: 666 OMAP_BAD_REG(addr); 667 return; 668 } 669 } 670 671 static const MemoryRegionOps omap2_gpif_top_ops = { 672 .read = omap2_gpif_top_read, 673 .write = omap2_gpif_top_write, 674 .endianness = DEVICE_NATIVE_ENDIAN, 675 }; 676 677 static void omap_gpio_init(Object *obj) 678 { 679 DeviceState *dev = DEVICE(obj); 680 struct omap_gpif_s *s = OMAP1_GPIO(obj); 681 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 682 683 qdev_init_gpio_in(dev, omap_gpio_set, 16); 684 qdev_init_gpio_out(dev, s->omap1.handler, 16); 685 sysbus_init_irq(sbd, &s->omap1.irq); 686 memory_region_init_io(&s->iomem, obj, &omap_gpio_ops, &s->omap1, 687 "omap.gpio", 0x1000); 688 sysbus_init_mmio(sbd, &s->iomem); 689 } 690 691 static void omap_gpio_realize(DeviceState *dev, Error **errp) 692 { 693 struct omap_gpif_s *s = OMAP1_GPIO(dev); 694 695 if (!s->clk) { 696 error_setg(errp, "omap-gpio: clk not connected"); 697 } 698 } 699 700 static void omap2_gpio_realize(DeviceState *dev, Error **errp) 701 { 702 struct omap2_gpif_s *s = OMAP2_GPIO(dev); 703 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 704 int i; 705 706 if (!s->iclk) { 707 error_setg(errp, "omap2-gpio: iclk not connected"); 708 return; 709 } 710 711 s->modulecount = s->mpu_model < omap2430 ? 4 712 : s->mpu_model < omap3430 ? 5 713 : 6; 714 715 if (s->mpu_model < omap3430) { 716 memory_region_init_io(&s->iomem, OBJECT(dev), &omap2_gpif_top_ops, s, 717 "omap2.gpio", 0x1000); 718 sysbus_init_mmio(sbd, &s->iomem); 719 } 720 721 s->modules = g_new0(struct omap2_gpio_s, s->modulecount); 722 s->handler = g_new0(qemu_irq, s->modulecount * 32); 723 qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32); 724 qdev_init_gpio_out(dev, s->handler, s->modulecount * 32); 725 726 for (i = 0; i < s->modulecount; i++) { 727 struct omap2_gpio_s *m = &s->modules[i]; 728 729 if (!s->fclk[i]) { 730 error_setg(errp, "omap2-gpio: fclk%d not connected", i); 731 return; 732 } 733 734 m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25; 735 m->handler = &s->handler[i * 32]; 736 sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */ 737 sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */ 738 sysbus_init_irq(sbd, &m->wkup); 739 memory_region_init_io(&m->iomem, OBJECT(dev), &omap2_gpio_module_ops, m, 740 "omap.gpio-module", 0x1000); 741 sysbus_init_mmio(sbd, &m->iomem); 742 } 743 } 744 745 void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk) 746 { 747 gpio->clk = clk; 748 } 749 750 static Property omap_gpio_properties[] = { 751 DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), 752 DEFINE_PROP_END_OF_LIST(), 753 }; 754 755 static void omap_gpio_class_init(ObjectClass *klass, void *data) 756 { 757 DeviceClass *dc = DEVICE_CLASS(klass); 758 759 dc->realize = omap_gpio_realize; 760 dc->reset = omap_gpif_reset; 761 device_class_set_props(dc, omap_gpio_properties); 762 /* Reason: pointer property "clk" */ 763 dc->user_creatable = false; 764 } 765 766 static const TypeInfo omap_gpio_info = { 767 .name = TYPE_OMAP1_GPIO, 768 .parent = TYPE_SYS_BUS_DEVICE, 769 .instance_size = sizeof(struct omap_gpif_s), 770 .instance_init = omap_gpio_init, 771 .class_init = omap_gpio_class_init, 772 }; 773 774 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk) 775 { 776 gpio->iclk = clk; 777 } 778 779 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk) 780 { 781 assert(i <= 5); 782 gpio->fclk[i] = clk; 783 } 784 785 static Property omap2_gpio_properties[] = { 786 DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), 787 DEFINE_PROP_END_OF_LIST(), 788 }; 789 790 static void omap2_gpio_class_init(ObjectClass *klass, void *data) 791 { 792 DeviceClass *dc = DEVICE_CLASS(klass); 793 794 dc->realize = omap2_gpio_realize; 795 dc->reset = omap2_gpif_reset; 796 device_class_set_props(dc, omap2_gpio_properties); 797 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */ 798 dc->user_creatable = false; 799 } 800 801 static const TypeInfo omap2_gpio_info = { 802 .name = TYPE_OMAP2_GPIO, 803 .parent = TYPE_SYS_BUS_DEVICE, 804 .instance_size = sizeof(struct omap2_gpif_s), 805 .class_init = omap2_gpio_class_init, 806 }; 807 808 static void omap_gpio_register_types(void) 809 { 810 type_register_static(&omap_gpio_info); 811 type_register_static(&omap2_gpio_info); 812 } 813 814 type_init(omap_gpio_register_types)