xlnx_dp.c (49115B)
1 /* 2 * Xilinx Display Port 3 * 4 * Copyright (C) 2015 : GreenSocs Ltd 5 * http://www.greensocs.com/ , email: info@greensocs.com 6 * 7 * Developed by : 8 * Frederic Konrad <fred.konrad@greensocs.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option)any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 #include "hw/display/xlnx_dp.h" 31 #include "hw/irq.h" 32 #include "migration/vmstate.h" 33 34 #ifndef DEBUG_DP 35 #define DEBUG_DP 0 36 #endif 37 38 #define DPRINTF(fmt, ...) do { \ 39 if (DEBUG_DP) { \ 40 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \ 41 } \ 42 } while (0) 43 44 /* 45 * Register offset for DP. 46 */ 47 #define DP_LINK_BW_SET (0x0000 >> 2) 48 #define DP_LANE_COUNT_SET (0x0004 >> 2) 49 #define DP_ENHANCED_FRAME_EN (0x0008 >> 2) 50 #define DP_TRAINING_PATTERN_SET (0x000C >> 2) 51 #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2) 52 #define DP_SCRAMBLING_DISABLE (0x0014 >> 2) 53 #define DP_DOWNSPREAD_CTRL (0x0018 >> 2) 54 #define DP_SOFTWARE_RESET (0x001C >> 2) 55 #define DP_TRANSMITTER_ENABLE (0x0080 >> 2) 56 #define DP_MAIN_STREAM_ENABLE (0x0084 >> 2) 57 #define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2) 58 #define DP_VERSION_REGISTER (0x00F8 >> 2) 59 #define DP_CORE_ID (0x00FC >> 2) 60 61 #define DP_AUX_COMMAND_REGISTER (0x0100 >> 2) 62 #define AUX_ADDR_ONLY_MASK (0x1000) 63 #define AUX_COMMAND_MASK (0x0F00) 64 #define AUX_COMMAND_SHIFT (8) 65 #define AUX_COMMAND_NBYTES (0x000F) 66 67 #define DP_AUX_WRITE_FIFO (0x0104 >> 2) 68 #define DP_AUX_ADDRESS (0x0108 >> 2) 69 #define DP_AUX_CLOCK_DIVIDER (0x010C >> 2) 70 #define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2) 71 #define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2) 72 #define DP_AUX_REPLY_DATA (0x0134 >> 2) 73 #define DP_AUX_REPLY_CODE (0x0138 >> 2) 74 #define DP_AUX_REPLY_COUNT (0x013C >> 2) 75 #define DP_REPLY_DATA_COUNT (0x0148 >> 2) 76 #define DP_REPLY_STATUS (0x014C >> 2) 77 #define DP_HPD_DURATION (0x0150 >> 2) 78 #define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2) 79 #define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2) 80 #define DP_MAIN_STREAM_POLARITY (0x0188 >> 2) 81 #define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2) 82 #define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2) 83 #define DP_MAIN_STREAM_HRES (0x0194 >> 2) 84 #define DP_MAIN_STREAM_VRES (0x0198 >> 2) 85 #define DP_MAIN_STREAM_HSTART (0x019C >> 2) 86 #define DP_MAIN_STREAM_VSTART (0x01A0 >> 2) 87 #define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2) 88 #define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2) 89 #define DP_MAIN_STREAM_M_VID (0x01AC >> 2) 90 #define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2) 91 #define DP_MAIN_STREAM_N_VID (0x01B4 >> 2) 92 #define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2) 93 #define DP_MIN_BYTES_PER_TU (0x01C4 >> 2) 94 #define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2) 95 #define DP_INIT_WAIT (0x01CC >> 2) 96 #define DP_PHY_RESET (0x0200 >> 2) 97 #define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2) 98 #define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2) 99 #define DP_TRANSMIT_PRBS7 (0x0230 >> 2) 100 #define DP_PHY_CLOCK_SELECT (0x0234 >> 2) 101 #define DP_TX_PHY_POWER_DOWN (0x0238 >> 2) 102 #define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2) 103 #define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2) 104 #define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2) 105 #define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2) 106 #define DP_PHY_STATUS (0x0280 >> 2) 107 108 #define DP_TX_AUDIO_CONTROL (0x0300 >> 2) 109 #define DP_TX_AUD_CTRL (1) 110 111 #define DP_TX_AUDIO_CHANNELS (0x0304 >> 2) 112 #define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2) 113 #define DP_TX_M_AUD (0x0328 >> 2) 114 #define DP_TX_N_AUD (0x032C >> 2) 115 #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2) 116 #define DP_INT_STATUS (0x03A0 >> 2) 117 #define DP_INT_VBLNK_START (1 << 13) 118 #define DP_INT_MASK (0x03A4 >> 2) 119 #define DP_INT_EN (0x03A8 >> 2) 120 #define DP_INT_DS (0x03AC >> 2) 121 122 /* 123 * Registers offset for Audio Video Buffer configuration. 124 */ 125 #define V_BLEND_OFFSET (0xA000) 126 #define V_BLEND_BG_CLR_0 (0x0000 >> 2) 127 #define V_BLEND_BG_CLR_1 (0x0004 >> 2) 128 #define V_BLEND_BG_CLR_2 (0x0008 >> 2) 129 #define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2) 130 #define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2) 131 #define V_BLEND_LAYER0_CONTROL (0x0018 >> 2) 132 #define V_BLEND_LAYER1_CONTROL (0x001C >> 2) 133 134 #define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2) 135 #define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2) 136 137 #define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2) 138 #define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2) 139 #define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2) 140 #define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2) 141 #define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2) 142 #define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2) 143 144 #define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2) 145 146 #define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2) 147 #define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2) 148 #define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2) 149 #define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2) 150 #define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2) 151 #define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2) 152 #define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2) 153 154 /* 155 * Registers offset for Audio Video Buffer configuration. 156 */ 157 #define AV_BUF_MANAGER_OFFSET (0xB000) 158 #define AV_BUF_FORMAT (0x0000 >> 2) 159 #define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2) 160 #define AV_CHBUF0 (0x0010 >> 2) 161 #define AV_CHBUF1 (0x0014 >> 2) 162 #define AV_CHBUF2 (0x0018 >> 2) 163 #define AV_CHBUF3 (0x001C >> 2) 164 #define AV_CHBUF4 (0x0020 >> 2) 165 #define AV_CHBUF5 (0x0024 >> 2) 166 #define AV_BUF_STC_CONTROL (0x002C >> 2) 167 #define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2) 168 #define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2) 169 #define AV_BUF_STC_ADJ (0x0038 >> 2) 170 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2) 171 #define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2) 172 #define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2) 173 #define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2) 174 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2) 175 #define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2) 176 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2) 177 #define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2) 178 #define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2) 179 #define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2) 180 #define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2) 181 #define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2) 182 #define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2) 183 #define AV_BUF_DITHER_CONFIG (0x007C >> 2) 184 #define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2) 185 #define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2) 186 #define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2) 187 #define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2) 188 #define AV_BUF_SRST_REG (0x0124 >> 2) 189 #define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2) 190 #define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2) 191 192 #define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2) 193 194 #define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2) 195 196 #define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2) 197 198 #define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2) 199 200 #define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2) 201 202 #define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2) 203 204 #define AUDIO_MIXER_REGISTER_OFFSET (0xC000) 205 #define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2) 206 #define AUDIO_MIXER_META_DATA (0x0004 >> 2) 207 #define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2) 208 #define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2) 209 #define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2) 210 211 #define DP_AUDIO_DMA_CHANNEL(n) (4 + n) 212 #define DP_GRAPHIC_DMA_CHANNEL (3) 213 #define DP_VIDEO_DMA_CHANNEL (0) 214 215 enum DPGraphicFmt { 216 DP_GRAPHIC_RGBA8888 = 0 << 8, 217 DP_GRAPHIC_ABGR8888 = 1 << 8, 218 DP_GRAPHIC_RGB888 = 2 << 8, 219 DP_GRAPHIC_BGR888 = 3 << 8, 220 DP_GRAPHIC_RGBA5551 = 4 << 8, 221 DP_GRAPHIC_RGBA4444 = 5 << 8, 222 DP_GRAPHIC_RGB565 = 6 << 8, 223 DP_GRAPHIC_8BPP = 7 << 8, 224 DP_GRAPHIC_4BPP = 8 << 8, 225 DP_GRAPHIC_2BPP = 9 << 8, 226 DP_GRAPHIC_1BPP = 10 << 8, 227 DP_GRAPHIC_MASK = 0xF << 8 228 }; 229 230 enum DPVideoFmt { 231 DP_NL_VID_CB_Y0_CR_Y1 = 0, 232 DP_NL_VID_CR_Y0_CB_Y1 = 1, 233 DP_NL_VID_Y0_CR_Y1_CB = 2, 234 DP_NL_VID_Y0_CB_Y1_CR = 3, 235 DP_NL_VID_YV16 = 4, 236 DP_NL_VID_YV24 = 5, 237 DP_NL_VID_YV16CL = 6, 238 DP_NL_VID_MONO = 7, 239 DP_NL_VID_YV16CL2 = 8, 240 DP_NL_VID_YUV444 = 9, 241 DP_NL_VID_RGB888 = 10, 242 DP_NL_VID_RGBA8880 = 11, 243 DP_NL_VID_RGB888_10BPC = 12, 244 DP_NL_VID_YUV444_10BPC = 13, 245 DP_NL_VID_YV16CL2_10BPC = 14, 246 DP_NL_VID_YV16CL_10BPC = 15, 247 DP_NL_VID_YV16_10BPC = 16, 248 DP_NL_VID_YV24_10BPC = 17, 249 DP_NL_VID_Y_ONLY_10BPC = 18, 250 DP_NL_VID_YV16_420 = 19, 251 DP_NL_VID_YV16CL_420 = 20, 252 DP_NL_VID_YV16CL2_420 = 21, 253 DP_NL_VID_YV16_420_10BPC = 22, 254 DP_NL_VID_YV16CL_420_10BPC = 23, 255 DP_NL_VID_YV16CL2_420_10BPC = 24, 256 DP_NL_VID_FMT_MASK = 0x1F 257 }; 258 259 typedef enum DPGraphicFmt DPGraphicFmt; 260 typedef enum DPVideoFmt DPVideoFmt; 261 262 static const VMStateDescription vmstate_dp = { 263 .name = TYPE_XLNX_DP, 264 .version_id = 2, 265 .fields = (VMStateField[]){ 266 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState, 267 DP_CORE_REG_ARRAY_SIZE), 268 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState, 269 DP_AVBUF_REG_ARRAY_SIZE), 270 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState, 271 DP_VBLEND_REG_ARRAY_SIZE), 272 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState, 273 DP_AUDIO_REG_ARRAY_SIZE), 274 VMSTATE_PTIMER(vblank, XlnxDPState), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 #define DP_VBLANK_PTIMER_POLICY (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \ 280 PTIMER_POLICY_CONTINUOUS_TRIGGER | \ 281 PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) 282 283 static void xlnx_dp_update_irq(XlnxDPState *s); 284 285 static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size) 286 { 287 XlnxDPState *s = XLNX_DP(opaque); 288 289 offset = offset >> 2; 290 return s->audio_registers[offset]; 291 } 292 293 static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value, 294 unsigned size) 295 { 296 XlnxDPState *s = XLNX_DP(opaque); 297 298 offset = offset >> 2; 299 300 switch (offset) { 301 case AUDIO_MIXER_META_DATA: 302 s->audio_registers[offset] = value & 0x00000001; 303 break; 304 default: 305 s->audio_registers[offset] = value; 306 break; 307 } 308 } 309 310 static const MemoryRegionOps audio_ops = { 311 .read = xlnx_dp_audio_read, 312 .write = xlnx_dp_audio_write, 313 .endianness = DEVICE_NATIVE_ENDIAN, 314 }; 315 316 static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s, 317 uint8_t channel) 318 { 319 switch (channel) { 320 case 0: 321 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16); 322 case 1: 323 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16, 324 16); 325 default: 326 return 0; 327 } 328 } 329 330 static inline void xlnx_dp_audio_activate(XlnxDPState *s) 331 { 332 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL] 333 & DP_TX_AUD_CTRL) != 0); 334 AUD_set_active_out(s->amixer_output_stream, activated); 335 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0), 336 &s->audio_buffer_0); 337 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1), 338 &s->audio_buffer_1); 339 } 340 341 static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s) 342 { 343 /* 344 * Audio packets are signed and have this shape: 345 * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 346 * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 | 347 * 348 * Output audio is 16bits saturated. 349 */ 350 int i; 351 352 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) { 353 for (i = 0; i < s->audio_data_available[0] / 2; i++) { 354 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i]) 355 * xlnx_dp_audio_get_volume(s, 0) / 8192; 356 } 357 s->byte_left = s->audio_data_available[0]; 358 } else { 359 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2); 360 } 361 362 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) { 363 if ((s->audio_data_available[0] == 0) 364 || (s->audio_data_available[1] == s->audio_data_available[0])) { 365 for (i = 0; i < s->audio_data_available[1] / 2; i++) { 366 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i]) 367 * xlnx_dp_audio_get_volume(s, 1) / 8192; 368 } 369 s->byte_left = s->audio_data_available[1]; 370 } 371 } 372 373 for (i = 0; i < s->byte_left / 2; i++) { 374 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767)); 375 } 376 377 s->data_ptr = 0; 378 } 379 380 static void xlnx_dp_audio_callback(void *opaque, int avail) 381 { 382 /* 383 * Get some data from the DPDMA and compute these datas. 384 * Then wait for QEMU's audio subsystem to call this callback. 385 */ 386 XlnxDPState *s = XLNX_DP(opaque); 387 size_t written = 0; 388 389 /* If there are already some data don't get more data. */ 390 if (s->byte_left == 0) { 391 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4, 392 true); 393 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5, 394 true); 395 xlnx_dp_audio_mix_buffer(s); 396 } 397 398 /* Send the buffer through the audio. */ 399 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) { 400 if (s->byte_left != 0) { 401 written = AUD_write(s->amixer_output_stream, 402 &s->out_buffer[s->data_ptr], s->byte_left); 403 } else { 404 int len_to_copy; 405 /* 406 * There is nothing to play.. We don't have any data! Fill the 407 * buffer with zero's and send it. 408 */ 409 written = 0; 410 while (avail) { 411 len_to_copy = MIN(AUD_CHBUF_MAX_DEPTH, avail); 412 memset(s->out_buffer, 0, len_to_copy); 413 avail -= AUD_write(s->amixer_output_stream, s->out_buffer, 414 len_to_copy); 415 } 416 } 417 } else { 418 written = AUD_write(s->amixer_output_stream, 419 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE); 420 } 421 s->byte_left -= written; 422 s->data_ptr += written; 423 } 424 425 /* 426 * AUX channel related function. 427 */ 428 static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s) 429 { 430 fifo8_reset(&s->rx_fifo); 431 } 432 433 static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 434 { 435 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len); 436 fifo8_push_all(&s->rx_fifo, buf, len); 437 } 438 439 static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) 440 { 441 uint8_t ret; 442 443 if (fifo8_is_empty(&s->rx_fifo)) { 444 qemu_log_mask(LOG_GUEST_ERROR, 445 "%s: Reading empty RX_FIFO\n", 446 __func__); 447 /* 448 * The datasheet is not clear about the reset value, it seems 449 * to be unspecified. We choose to return '0'. 450 */ 451 ret = 0; 452 } else { 453 ret = fifo8_pop(&s->rx_fifo); 454 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret); 455 } 456 return ret; 457 } 458 459 static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s) 460 { 461 fifo8_reset(&s->tx_fifo); 462 } 463 464 static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len) 465 { 466 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len); 467 fifo8_push_all(&s->tx_fifo, buf, len); 468 } 469 470 static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s) 471 { 472 uint8_t ret; 473 474 if (fifo8_is_empty(&s->tx_fifo)) { 475 error_report("%s: TX_FIFO underflow", __func__); 476 abort(); 477 } 478 ret = fifo8_pop(&s->tx_fifo); 479 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret); 480 return ret; 481 } 482 483 static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s) 484 { 485 return s->core_registers[DP_AUX_ADDRESS]; 486 } 487 488 /* 489 * Get command from the register. 490 */ 491 static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value) 492 { 493 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0; 494 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT; 495 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1; 496 uint8_t buf[16]; 497 int i; 498 499 /* 500 * When an address_only command is executed nothing happen to the fifo, so 501 * just make nbytes = 0. 502 */ 503 if (address_only) { 504 nbytes = 0; 505 } 506 507 switch (cmd) { 508 case READ_AUX: 509 case READ_I2C: 510 case READ_I2C_MOT: 511 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 512 xlnx_dp_aux_get_address(s), 513 nbytes, buf); 514 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes; 515 516 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) { 517 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes); 518 } 519 break; 520 case WRITE_AUX: 521 case WRITE_I2C: 522 case WRITE_I2C_MOT: 523 for (i = 0; i < nbytes; i++) { 524 buf[i] = xlnx_dp_aux_pop_tx_fifo(s); 525 } 526 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, 527 xlnx_dp_aux_get_address(s), 528 nbytes, buf); 529 xlnx_dp_aux_clear_tx_fifo(s); 530 break; 531 case WRITE_I2C_STATUS: 532 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n"); 533 break; 534 default: 535 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command: %u", __func__, cmd); 536 return; 537 } 538 539 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04; 540 } 541 542 static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val, 543 Error **errp) 544 { 545 XlnxDPState *s = XLNX_DP(obj); 546 if (s->console) { 547 DisplaySurface *surface = qemu_console_surface(s->console); 548 XlnxDPDMAState *dma = XLNX_DPDMA(val); 549 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL, 550 surface_data(surface)); 551 } 552 } 553 554 static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s) 555 { 556 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1; 557 } 558 559 static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s) 560 { 561 /* 562 * If the alpha is totally opaque (255) we consider the alpha is disabled to 563 * reduce CPU consumption. 564 */ 565 return ((xlnx_dp_global_alpha_value(s) != 0xFF) && 566 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0)); 567 } 568 569 static void xlnx_dp_recreate_surface(XlnxDPState *s) 570 { 571 /* 572 * Two possibilities, if blending is enabled the console displays 573 * bout_plane, if not g_plane is displayed. 574 */ 575 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES]; 576 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES]; 577 DisplaySurface *current_console_surface = qemu_console_surface(s->console); 578 579 if ((width != 0) && (height != 0)) { 580 /* 581 * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the 582 * surface we need to be careful and don't free the surface associated 583 * to the console or double free will happen. 584 */ 585 if (s->bout_plane.surface != current_console_surface) { 586 qemu_free_displaysurface(s->bout_plane.surface); 587 } 588 if (s->v_plane.surface != current_console_surface) { 589 qemu_free_displaysurface(s->v_plane.surface); 590 } 591 if (s->g_plane.surface != current_console_surface) { 592 qemu_free_displaysurface(s->g_plane.surface); 593 } 594 595 s->g_plane.surface 596 = qemu_create_displaysurface_from(width, height, 597 s->g_plane.format, 0, NULL); 598 s->v_plane.surface 599 = qemu_create_displaysurface_from(width, height, 600 s->v_plane.format, 0, NULL); 601 if (xlnx_dp_global_alpha_enabled(s)) { 602 s->bout_plane.surface = 603 qemu_create_displaysurface_from(width, 604 height, 605 s->g_plane.format, 606 0, NULL); 607 dpy_gfx_replace_surface(s->console, s->bout_plane.surface); 608 } else { 609 s->bout_plane.surface = NULL; 610 dpy_gfx_replace_surface(s->console, s->g_plane.surface); 611 } 612 613 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 614 surface_data(s->g_plane.surface)); 615 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL, 616 surface_data(s->v_plane.surface)); 617 } 618 } 619 620 /* 621 * Change the graphic format of the surface. 622 */ 623 static void xlnx_dp_change_graphic_fmt(XlnxDPState *s) 624 { 625 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) { 626 case DP_GRAPHIC_RGBA8888: 627 s->g_plane.format = PIXMAN_r8g8b8a8; 628 break; 629 case DP_GRAPHIC_ABGR8888: 630 s->g_plane.format = PIXMAN_a8b8g8r8; 631 break; 632 case DP_GRAPHIC_RGB565: 633 s->g_plane.format = PIXMAN_r5g6b5; 634 break; 635 case DP_GRAPHIC_RGB888: 636 s->g_plane.format = PIXMAN_r8g8b8; 637 break; 638 case DP_GRAPHIC_BGR888: 639 s->g_plane.format = PIXMAN_b8g8r8; 640 break; 641 default: 642 error_report("%s: unsupported graphic format %u", __func__, 643 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK); 644 abort(); 645 } 646 647 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) { 648 case 0: 649 s->v_plane.format = PIXMAN_x8b8g8r8; 650 break; 651 case DP_NL_VID_Y0_CB_Y1_CR: 652 s->v_plane.format = PIXMAN_yuy2; 653 break; 654 case DP_NL_VID_RGBA8880: 655 s->v_plane.format = PIXMAN_x8b8g8r8; 656 break; 657 default: 658 error_report("%s: unsupported video format %u", __func__, 659 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK); 660 abort(); 661 } 662 663 xlnx_dp_recreate_surface(s); 664 } 665 666 static void xlnx_dp_update_irq(XlnxDPState *s) 667 { 668 uint32_t flags; 669 670 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; 671 DPRINTF("update IRQ value = %" PRIx32 "\n", flags); 672 qemu_set_irq(s->irq, flags != 0); 673 } 674 675 static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size) 676 { 677 XlnxDPState *s = XLNX_DP(opaque); 678 uint64_t ret = 0; 679 680 offset = offset >> 2; 681 682 switch (offset) { 683 case DP_TX_USER_FIFO_OVERFLOW: 684 /* This register is cleared after a read */ 685 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW]; 686 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0; 687 break; 688 case DP_AUX_REPLY_DATA: 689 ret = xlnx_dp_aux_pop_rx_fifo(s); 690 break; 691 case DP_INTERRUPT_SIGNAL_STATE: 692 /* 693 * XXX: Not sure it is the right thing to do actually. 694 * The register is not written by the device driver so it's stuck 695 * to 0x04. 696 */ 697 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE]; 698 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04; 699 break; 700 case DP_AUX_WRITE_FIFO: 701 case DP_TX_AUDIO_INFO_DATA(0): 702 case DP_TX_AUDIO_INFO_DATA(1): 703 case DP_TX_AUDIO_INFO_DATA(2): 704 case DP_TX_AUDIO_INFO_DATA(3): 705 case DP_TX_AUDIO_INFO_DATA(4): 706 case DP_TX_AUDIO_INFO_DATA(5): 707 case DP_TX_AUDIO_INFO_DATA(6): 708 case DP_TX_AUDIO_INFO_DATA(7): 709 case DP_TX_AUDIO_EXT_DATA(0): 710 case DP_TX_AUDIO_EXT_DATA(1): 711 case DP_TX_AUDIO_EXT_DATA(2): 712 case DP_TX_AUDIO_EXT_DATA(3): 713 case DP_TX_AUDIO_EXT_DATA(4): 714 case DP_TX_AUDIO_EXT_DATA(5): 715 case DP_TX_AUDIO_EXT_DATA(6): 716 case DP_TX_AUDIO_EXT_DATA(7): 717 case DP_TX_AUDIO_EXT_DATA(8): 718 /* write only registers */ 719 ret = 0; 720 break; 721 default: 722 assert(offset <= (0x3AC >> 2)); 723 if (offset == (0x3A8 >> 2) || offset == (0x3AC >> 2)) { 724 ret = s->core_registers[DP_INT_MASK]; 725 } else { 726 ret = s->core_registers[offset]; 727 } 728 break; 729 } 730 731 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret); 732 return ret; 733 } 734 735 static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, 736 unsigned size) 737 { 738 XlnxDPState *s = XLNX_DP(opaque); 739 740 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value); 741 742 offset = offset >> 2; 743 744 switch (offset) { 745 /* 746 * Only special write case are handled. 747 */ 748 case DP_LINK_BW_SET: 749 s->core_registers[offset] = value & 0x000000FF; 750 break; 751 case DP_LANE_COUNT_SET: 752 case DP_MAIN_STREAM_MISC0: 753 s->core_registers[offset] = value & 0x0000000F; 754 break; 755 case DP_TRAINING_PATTERN_SET: 756 case DP_LINK_QUAL_PATTERN_SET: 757 case DP_MAIN_STREAM_POLARITY: 758 case DP_PHY_VOLTAGE_DIFF_LANE_0: 759 case DP_PHY_VOLTAGE_DIFF_LANE_1: 760 s->core_registers[offset] = value & 0x00000003; 761 break; 762 case DP_ENHANCED_FRAME_EN: 763 case DP_SCRAMBLING_DISABLE: 764 case DP_DOWNSPREAD_CTRL: 765 case DP_MAIN_STREAM_ENABLE: 766 case DP_TRANSMIT_PRBS7: 767 s->core_registers[offset] = value & 0x00000001; 768 break; 769 case DP_PHY_CLOCK_SELECT: 770 s->core_registers[offset] = value & 0x00000007; 771 break; 772 case DP_SOFTWARE_RESET: 773 /* 774 * No need to update this bit as it's read '0'. 775 */ 776 /* 777 * TODO: reset IP. 778 */ 779 break; 780 case DP_TRANSMITTER_ENABLE: 781 s->core_registers[offset] = value & 0x01; 782 ptimer_transaction_begin(s->vblank); 783 if (value & 0x1) { 784 ptimer_run(s->vblank, 0); 785 } else { 786 ptimer_stop(s->vblank); 787 } 788 ptimer_transaction_commit(s->vblank); 789 break; 790 case DP_FORCE_SCRAMBLER_RESET: 791 /* 792 * No need to update this bit as it's read '0'. 793 */ 794 /* 795 * TODO: force a scrambler reset?? 796 */ 797 break; 798 case DP_AUX_COMMAND_REGISTER: 799 s->core_registers[offset] = value & 0x00001F0F; 800 xlnx_dp_aux_set_command(s, s->core_registers[offset]); 801 break; 802 case DP_MAIN_STREAM_HTOTAL: 803 case DP_MAIN_STREAM_VTOTAL: 804 case DP_MAIN_STREAM_HSTART: 805 case DP_MAIN_STREAM_VSTART: 806 s->core_registers[offset] = value & 0x0000FFFF; 807 break; 808 case DP_MAIN_STREAM_HRES: 809 case DP_MAIN_STREAM_VRES: 810 s->core_registers[offset] = value & 0x0000FFFF; 811 xlnx_dp_recreate_surface(s); 812 break; 813 case DP_MAIN_STREAM_HSWIDTH: 814 case DP_MAIN_STREAM_VSWIDTH: 815 s->core_registers[offset] = value & 0x00007FFF; 816 break; 817 case DP_MAIN_STREAM_MISC1: 818 s->core_registers[offset] = value & 0x00000086; 819 break; 820 case DP_MAIN_STREAM_M_VID: 821 case DP_MAIN_STREAM_N_VID: 822 s->core_registers[offset] = value & 0x00FFFFFF; 823 break; 824 case DP_MSA_TRANSFER_UNIT_SIZE: 825 case DP_MIN_BYTES_PER_TU: 826 case DP_INIT_WAIT: 827 s->core_registers[offset] = value & 0x00000007; 828 break; 829 case DP_USER_DATA_COUNT_PER_LANE: 830 s->core_registers[offset] = value & 0x0003FFFF; 831 break; 832 case DP_FRAC_BYTES_PER_TU: 833 s->core_registers[offset] = value & 0x000003FF; 834 break; 835 case DP_PHY_RESET: 836 s->core_registers[offset] = value & 0x00010003; 837 /* 838 * TODO: Reset something? 839 */ 840 break; 841 case DP_TX_PHY_POWER_DOWN: 842 s->core_registers[offset] = value & 0x0000000F; 843 /* 844 * TODO: Power down things? 845 */ 846 break; 847 case DP_AUX_WRITE_FIFO: { 848 uint8_t c = value; 849 xlnx_dp_aux_push_tx_fifo(s, &c, 1); 850 break; 851 } 852 case DP_AUX_CLOCK_DIVIDER: 853 break; 854 case DP_AUX_REPLY_COUNT: 855 /* 856 * Writing to this register clear the counter. 857 */ 858 s->core_registers[offset] = 0x00000000; 859 break; 860 case DP_AUX_ADDRESS: 861 s->core_registers[offset] = value & 0x000FFFFF; 862 break; 863 case DP_VERSION_REGISTER: 864 case DP_CORE_ID: 865 case DP_TX_USER_FIFO_OVERFLOW: 866 case DP_AUX_REPLY_DATA: 867 case DP_AUX_REPLY_CODE: 868 case DP_REPLY_DATA_COUNT: 869 case DP_REPLY_STATUS: 870 case DP_HPD_DURATION: 871 /* 872 * Write to read only location.. 873 */ 874 break; 875 case DP_TX_AUDIO_CONTROL: 876 s->core_registers[offset] = value & 0x00000001; 877 xlnx_dp_audio_activate(s); 878 break; 879 case DP_TX_AUDIO_CHANNELS: 880 s->core_registers[offset] = value & 0x00000007; 881 xlnx_dp_audio_activate(s); 882 break; 883 case DP_INT_STATUS: 884 s->core_registers[DP_INT_STATUS] &= ~value; 885 xlnx_dp_update_irq(s); 886 break; 887 case DP_INT_EN: 888 s->core_registers[DP_INT_MASK] &= ~value; 889 xlnx_dp_update_irq(s); 890 break; 891 case DP_INT_DS: 892 s->core_registers[DP_INT_MASK] |= value; 893 xlnx_dp_update_irq(s); 894 break; 895 default: 896 assert(offset <= (0x504C >> 2)); 897 s->core_registers[offset] = value; 898 break; 899 } 900 } 901 902 static const MemoryRegionOps dp_ops = { 903 .read = xlnx_dp_read, 904 .write = xlnx_dp_write, 905 .endianness = DEVICE_NATIVE_ENDIAN, 906 .valid = { 907 .min_access_size = 4, 908 .max_access_size = 4, 909 }, 910 .impl = { 911 .min_access_size = 4, 912 .max_access_size = 4, 913 }, 914 }; 915 916 /* 917 * This is to handle Read/Write to the Video Blender. 918 */ 919 static void xlnx_dp_vblend_write(void *opaque, hwaddr offset, 920 uint64_t value, unsigned size) 921 { 922 XlnxDPState *s = XLNX_DP(opaque); 923 bool alpha_was_enabled; 924 925 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 926 (uint32_t)value); 927 offset = offset >> 2; 928 929 switch (offset) { 930 case V_BLEND_BG_CLR_0: 931 case V_BLEND_BG_CLR_1: 932 case V_BLEND_BG_CLR_2: 933 s->vblend_registers[offset] = value & 0x00000FFF; 934 break; 935 case V_BLEND_SET_GLOBAL_ALPHA_REG: 936 /* 937 * A write to this register can enable or disable blending. Thus we need 938 * to recreate the surfaces. 939 */ 940 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s); 941 s->vblend_registers[offset] = value & 0x000001FF; 942 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) { 943 xlnx_dp_recreate_surface(s); 944 } 945 break; 946 case V_BLEND_OUTPUT_VID_FORMAT: 947 s->vblend_registers[offset] = value & 0x00000017; 948 break; 949 case V_BLEND_LAYER0_CONTROL: 950 case V_BLEND_LAYER1_CONTROL: 951 s->vblend_registers[offset] = value & 0x00000103; 952 break; 953 case V_BLEND_RGB2YCBCR_COEFF(0): 954 case V_BLEND_RGB2YCBCR_COEFF(1): 955 case V_BLEND_RGB2YCBCR_COEFF(2): 956 case V_BLEND_RGB2YCBCR_COEFF(3): 957 case V_BLEND_RGB2YCBCR_COEFF(4): 958 case V_BLEND_RGB2YCBCR_COEFF(5): 959 case V_BLEND_RGB2YCBCR_COEFF(6): 960 case V_BLEND_RGB2YCBCR_COEFF(7): 961 case V_BLEND_RGB2YCBCR_COEFF(8): 962 case V_BLEND_IN1CSC_COEFF(0): 963 case V_BLEND_IN1CSC_COEFF(1): 964 case V_BLEND_IN1CSC_COEFF(2): 965 case V_BLEND_IN1CSC_COEFF(3): 966 case V_BLEND_IN1CSC_COEFF(4): 967 case V_BLEND_IN1CSC_COEFF(5): 968 case V_BLEND_IN1CSC_COEFF(6): 969 case V_BLEND_IN1CSC_COEFF(7): 970 case V_BLEND_IN1CSC_COEFF(8): 971 case V_BLEND_IN2CSC_COEFF(0): 972 case V_BLEND_IN2CSC_COEFF(1): 973 case V_BLEND_IN2CSC_COEFF(2): 974 case V_BLEND_IN2CSC_COEFF(3): 975 case V_BLEND_IN2CSC_COEFF(4): 976 case V_BLEND_IN2CSC_COEFF(5): 977 case V_BLEND_IN2CSC_COEFF(6): 978 case V_BLEND_IN2CSC_COEFF(7): 979 case V_BLEND_IN2CSC_COEFF(8): 980 s->vblend_registers[offset] = value & 0x0000FFFF; 981 break; 982 case V_BLEND_LUMA_IN1CSC_OFFSET: 983 case V_BLEND_CR_IN1CSC_OFFSET: 984 case V_BLEND_CB_IN1CSC_OFFSET: 985 case V_BLEND_LUMA_IN2CSC_OFFSET: 986 case V_BLEND_CR_IN2CSC_OFFSET: 987 case V_BLEND_CB_IN2CSC_OFFSET: 988 case V_BLEND_LUMA_OUTCSC_OFFSET: 989 case V_BLEND_CR_OUTCSC_OFFSET: 990 case V_BLEND_CB_OUTCSC_OFFSET: 991 s->vblend_registers[offset] = value & 0x3FFF7FFF; 992 break; 993 case V_BLEND_CHROMA_KEY_ENABLE: 994 s->vblend_registers[offset] = value & 0x00000003; 995 break; 996 case V_BLEND_CHROMA_KEY_COMP1: 997 case V_BLEND_CHROMA_KEY_COMP2: 998 case V_BLEND_CHROMA_KEY_COMP3: 999 s->vblend_registers[offset] = value & 0x0FFF0FFF; 1000 break; 1001 default: 1002 s->vblend_registers[offset] = value; 1003 break; 1004 } 1005 } 1006 1007 static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset, 1008 unsigned size) 1009 { 1010 XlnxDPState *s = XLNX_DP(opaque); 1011 1012 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 1013 s->vblend_registers[offset >> 2]); 1014 return s->vblend_registers[offset >> 2]; 1015 } 1016 1017 static const MemoryRegionOps vblend_ops = { 1018 .read = xlnx_dp_vblend_read, 1019 .write = xlnx_dp_vblend_write, 1020 .endianness = DEVICE_NATIVE_ENDIAN, 1021 .valid = { 1022 .min_access_size = 4, 1023 .max_access_size = 4, 1024 }, 1025 .impl = { 1026 .min_access_size = 4, 1027 .max_access_size = 4, 1028 }, 1029 }; 1030 1031 /* 1032 * This is to handle Read/Write to the Audio Video buffer manager. 1033 */ 1034 static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value, 1035 unsigned size) 1036 { 1037 XlnxDPState *s = XLNX_DP(opaque); 1038 1039 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset, 1040 (uint32_t)value); 1041 offset = offset >> 2; 1042 1043 switch (offset) { 1044 case AV_BUF_FORMAT: 1045 s->avbufm_registers[offset] = value & 0x00000FFF; 1046 xlnx_dp_change_graphic_fmt(s); 1047 break; 1048 case AV_CHBUF0: 1049 case AV_CHBUF1: 1050 case AV_CHBUF2: 1051 case AV_CHBUF3: 1052 case AV_CHBUF4: 1053 case AV_CHBUF5: 1054 s->avbufm_registers[offset] = value & 0x0000007F; 1055 break; 1056 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: 1057 s->avbufm_registers[offset] = value & 0x0000007F; 1058 break; 1059 case AV_BUF_DITHER_CONFIG: 1060 s->avbufm_registers[offset] = value & 0x000007FF; 1061 break; 1062 case AV_BUF_DITHER_CONFIG_MAX: 1063 case AV_BUF_DITHER_CONFIG_MIN: 1064 s->avbufm_registers[offset] = value & 0x00000FFF; 1065 break; 1066 case AV_BUF_PATTERN_GEN_SELECT: 1067 s->avbufm_registers[offset] = value & 0xFFFFFF03; 1068 break; 1069 case AV_BUF_AUD_VID_CLK_SOURCE: 1070 s->avbufm_registers[offset] = value & 0x00000007; 1071 break; 1072 case AV_BUF_SRST_REG: 1073 s->avbufm_registers[offset] = value & 0x00000002; 1074 break; 1075 case AV_BUF_AUDIO_CH_CONFIG: 1076 s->avbufm_registers[offset] = value & 0x00000003; 1077 break; 1078 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0): 1079 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1): 1080 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2): 1081 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0): 1082 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1): 1083 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2): 1084 s->avbufm_registers[offset] = value & 0x0000FFFF; 1085 break; 1086 case AV_BUF_LIVE_VIDEO_COMP_SF(0): 1087 case AV_BUF_LIVE_VIDEO_COMP_SF(1): 1088 case AV_BUF_LIVE_VIDEO_COMP_SF(2): 1089 case AV_BUF_LIVE_VID_CONFIG: 1090 case AV_BUF_LIVE_GFX_COMP_SF(0): 1091 case AV_BUF_LIVE_GFX_COMP_SF(1): 1092 case AV_BUF_LIVE_GFX_COMP_SF(2): 1093 case AV_BUF_LIVE_GFX_CONFIG: 1094 case AV_BUF_NON_LIVE_LATENCY: 1095 case AV_BUF_STC_CONTROL: 1096 case AV_BUF_STC_INIT_VALUE0: 1097 case AV_BUF_STC_INIT_VALUE1: 1098 case AV_BUF_STC_ADJ: 1099 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0: 1100 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1: 1101 case AV_BUF_STC_EXT_VSYNC_TS_REG0: 1102 case AV_BUF_STC_EXT_VSYNC_TS_REG1: 1103 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0: 1104 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1: 1105 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: 1106 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: 1107 case AV_BUF_STC_SNAPSHOT0: 1108 case AV_BUF_STC_SNAPSHOT1: 1109 case AV_BUF_HCOUNT_VCOUNT_INT0: 1110 case AV_BUF_HCOUNT_VCOUNT_INT1: 1111 qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04" 1112 PRIx64 "\n", 1113 offset << 2); 1114 break; 1115 default: 1116 s->avbufm_registers[offset] = value; 1117 break; 1118 } 1119 } 1120 1121 static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset, 1122 unsigned size) 1123 { 1124 XlnxDPState *s = XLNX_DP(opaque); 1125 1126 offset = offset >> 2; 1127 return s->avbufm_registers[offset]; 1128 } 1129 1130 static const MemoryRegionOps avbufm_ops = { 1131 .read = xlnx_dp_avbufm_read, 1132 .write = xlnx_dp_avbufm_write, 1133 .endianness = DEVICE_NATIVE_ENDIAN, 1134 .valid = { 1135 .min_access_size = 4, 1136 .max_access_size = 4, 1137 }, 1138 .impl = { 1139 .min_access_size = 4, 1140 .max_access_size = 4, 1141 }, 1142 }; 1143 1144 /* 1145 * This is a global alpha blending using pixman. 1146 * Both graphic and video planes are multiplied with the global alpha 1147 * coefficient and added. 1148 */ 1149 static inline void xlnx_dp_blend_surface(XlnxDPState *s) 1150 { 1151 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1), 1152 pixman_double_to_fixed(1), 1153 pixman_double_to_fixed(1.0) }; 1154 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1), 1155 pixman_double_to_fixed(1), 1156 pixman_double_to_fixed(1.0) }; 1157 1158 if ((surface_width(s->g_plane.surface) 1159 != surface_width(s->v_plane.surface)) || 1160 (surface_height(s->g_plane.surface) 1161 != surface_height(s->v_plane.surface))) { 1162 return; 1163 } 1164 1165 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s)) 1166 / 256.0); 1167 alpha2[2] = pixman_double_to_fixed((255.0 1168 - (double)xlnx_dp_global_alpha_value(s)) 1169 / 256.0); 1170 1171 pixman_image_set_filter(s->g_plane.surface->image, 1172 PIXMAN_FILTER_CONVOLUTION, alpha1, 3); 1173 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0, 1174 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1175 surface_width(s->g_plane.surface), 1176 surface_height(s->g_plane.surface)); 1177 pixman_image_set_filter(s->v_plane.surface->image, 1178 PIXMAN_FILTER_CONVOLUTION, alpha2, 3); 1179 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0, 1180 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0, 1181 surface_width(s->g_plane.surface), 1182 surface_height(s->g_plane.surface)); 1183 } 1184 1185 static void xlnx_dp_update_display(void *opaque) 1186 { 1187 XlnxDPState *s = XLNX_DP(opaque); 1188 1189 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { 1190 return; 1191 } 1192 1193 xlnx_dpdma_trigger_vsync_irq(s->dpdma); 1194 1195 /* 1196 * Trigger the DMA channel. 1197 */ 1198 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) { 1199 /* 1200 * An error occurred don't do anything with the data.. 1201 * Trigger an underflow interrupt. 1202 */ 1203 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1204 xlnx_dp_update_irq(s); 1205 return; 1206 } 1207 1208 if (xlnx_dp_global_alpha_enabled(s)) { 1209 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { 1210 s->core_registers[DP_INT_STATUS] |= (1 << 21); 1211 xlnx_dp_update_irq(s); 1212 return; 1213 } 1214 xlnx_dp_blend_surface(s); 1215 } 1216 1217 /* 1218 * XXX: We might want to update only what changed. 1219 */ 1220 dpy_gfx_update_full(s->console); 1221 } 1222 1223 static const GraphicHwOps xlnx_dp_gfx_ops = { 1224 .gfx_update = xlnx_dp_update_display, 1225 }; 1226 1227 static void xlnx_dp_init(Object *obj) 1228 { 1229 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1230 XlnxDPState *s = XLNX_DP(obj); 1231 1232 memory_region_init(&s->container, obj, TYPE_XLNX_DP, DP_CONTAINER_SIZE); 1233 1234 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP 1235 ".core", sizeof(s->core_registers)); 1236 memory_region_add_subregion(&s->container, DP_CORE_REG_OFFSET, 1237 &s->core_iomem); 1238 1239 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP 1240 ".v_blend", sizeof(s->vblend_registers)); 1241 memory_region_add_subregion(&s->container, DP_VBLEND_REG_OFFSET, 1242 &s->vblend_iomem); 1243 1244 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP 1245 ".av_buffer_manager", sizeof(s->avbufm_registers)); 1246 memory_region_add_subregion(&s->container, DP_AVBUF_REG_OFFSET, 1247 &s->avbufm_iomem); 1248 1249 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP 1250 ".audio", sizeof(s->audio_registers)); 1251 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem); 1252 1253 sysbus_init_mmio(sbd, &s->container); 1254 sysbus_init_irq(sbd, &s->irq); 1255 1256 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA, 1257 (Object **) &s->dpdma, 1258 xlnx_dp_set_dpdma, 1259 OBJ_PROP_LINK_STRONG); 1260 1261 /* 1262 * Initialize AUX Bus. 1263 */ 1264 s->aux_bus = aux_bus_init(DEVICE(obj), "aux"); 1265 1266 /* 1267 * Initialize DPCD and EDID.. 1268 */ 1269 s->dpcd = DPCD(qdev_new("dpcd")); 1270 object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd)); 1271 1272 s->edid = I2CDDC(qdev_new("i2c-ddc")); 1273 i2c_slave_set_address(I2C_SLAVE(s->edid), 0x50); 1274 object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid)); 1275 1276 fifo8_create(&s->rx_fifo, 16); 1277 fifo8_create(&s->tx_fifo, 16); 1278 } 1279 1280 static void xlnx_dp_finalize(Object *obj) 1281 { 1282 XlnxDPState *s = XLNX_DP(obj); 1283 1284 fifo8_destroy(&s->tx_fifo); 1285 fifo8_destroy(&s->rx_fifo); 1286 } 1287 1288 static void vblank_hit(void *opaque) 1289 { 1290 XlnxDPState *s = XLNX_DP(opaque); 1291 1292 s->core_registers[DP_INT_STATUS] |= DP_INT_VBLNK_START; 1293 xlnx_dp_update_irq(s); 1294 } 1295 1296 static void xlnx_dp_realize(DeviceState *dev, Error **errp) 1297 { 1298 XlnxDPState *s = XLNX_DP(dev); 1299 DisplaySurface *surface; 1300 struct audsettings as; 1301 1302 aux_bus_realize(s->aux_bus); 1303 1304 qdev_realize(DEVICE(s->dpcd), BUS(s->aux_bus), &error_fatal); 1305 aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000); 1306 1307 qdev_realize_and_unref(DEVICE(s->edid), BUS(aux_get_i2c_bus(s->aux_bus)), 1308 &error_fatal); 1309 1310 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s); 1311 surface = qemu_console_surface(s->console); 1312 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL, 1313 surface_data(surface)); 1314 1315 as.freq = 44100; 1316 as.nchannels = 2; 1317 as.fmt = AUDIO_FORMAT_S16; 1318 as.endianness = 0; 1319 1320 AUD_register_card("xlnx_dp.audio", &s->aud_card); 1321 1322 s->amixer_output_stream = AUD_open_out(&s->aud_card, 1323 s->amixer_output_stream, 1324 "xlnx_dp.audio.out", 1325 s, 1326 xlnx_dp_audio_callback, 1327 &as); 1328 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255); 1329 xlnx_dp_audio_activate(s); 1330 s->vblank = ptimer_init(vblank_hit, s, DP_VBLANK_PTIMER_POLICY); 1331 ptimer_transaction_begin(s->vblank); 1332 ptimer_set_freq(s->vblank, 30); 1333 ptimer_transaction_commit(s->vblank); 1334 } 1335 1336 static void xlnx_dp_reset(DeviceState *dev) 1337 { 1338 XlnxDPState *s = XLNX_DP(dev); 1339 1340 memset(s->core_registers, 0, sizeof(s->core_registers)); 1341 s->core_registers[DP_VERSION_REGISTER] = 0x04010000; 1342 s->core_registers[DP_CORE_ID] = 0x01020000; 1343 s->core_registers[DP_REPLY_STATUS] = 0x00000010; 1344 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040; 1345 s->core_registers[DP_INIT_WAIT] = 0x00000020; 1346 s->core_registers[DP_PHY_RESET] = 0x00010003; 1347 s->core_registers[DP_INT_MASK] = 0xFFFFF03F; 1348 s->core_registers[DP_PHY_STATUS] = 0x00000043; 1349 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001; 1350 1351 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000; 1352 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000; 1353 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000; 1354 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000; 1355 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000; 1356 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000; 1357 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000; 1358 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000; 1359 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000; 1360 1361 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180; 1362 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008; 1363 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF; 1364 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101; 1365 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101; 1366 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101; 1367 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101; 1368 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101; 1369 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101; 1370 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101; 1371 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101; 1372 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101; 1373 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101; 1374 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101; 1375 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101; 1376 1377 memset(s->audio_registers, 0, sizeof(s->audio_registers)); 1378 s->byte_left = 0; 1379 1380 xlnx_dp_aux_clear_rx_fifo(s); 1381 xlnx_dp_change_graphic_fmt(s); 1382 xlnx_dp_update_irq(s); 1383 } 1384 1385 static void xlnx_dp_class_init(ObjectClass *oc, void *data) 1386 { 1387 DeviceClass *dc = DEVICE_CLASS(oc); 1388 1389 dc->realize = xlnx_dp_realize; 1390 dc->vmsd = &vmstate_dp; 1391 dc->reset = xlnx_dp_reset; 1392 } 1393 1394 static const TypeInfo xlnx_dp_info = { 1395 .name = TYPE_XLNX_DP, 1396 .parent = TYPE_SYS_BUS_DEVICE, 1397 .instance_size = sizeof(XlnxDPState), 1398 .instance_init = xlnx_dp_init, 1399 .instance_finalize = xlnx_dp_finalize, 1400 .class_init = xlnx_dp_class_init, 1401 }; 1402 1403 static void xlnx_dp_register_types(void) 1404 { 1405 type_register_static(&xlnx_dp_info); 1406 } 1407 1408 type_init(xlnx_dp_register_types)