ati_2d.c (8527B)
1 /* 2 * QEMU ATI SVGA emulation 3 * 2D engine functions 4 * 5 * Copyright (c) 2019 BALATON Zoltan 6 * 7 * This work is licensed under the GNU GPL license version 2 or later. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "ati_int.h" 12 #include "ati_regs.h" 13 #include "qemu/log.h" 14 #include "ui/pixel_ops.h" 15 #include "ui/console.h" 16 17 /* 18 * NOTE: 19 * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to 20 * reinvent the wheel (unlikely to get better with a naive implementation than 21 * existing libraries) and avoid (poorly) reimplementing gfx primitives. 22 * That is unnecessary and would become a performance problem. Instead, try to 23 * map to and reuse existing optimised facilities (e.g. pixman) wherever 24 * possible. 25 */ 26 27 static int ati_bpp_from_datatype(ATIVGAState *s) 28 { 29 switch (s->regs.dp_datatype & 0xf) { 30 case 2: 31 return 8; 32 case 3: 33 case 4: 34 return 16; 35 case 5: 36 return 24; 37 case 6: 38 return 32; 39 default: 40 qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n", 41 s->regs.dp_datatype & 0xf); 42 return 0; 43 } 44 } 45 46 #define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL) 47 48 void ati_2d_blt(ATIVGAState *s) 49 { 50 /* FIXME it is probably more complex than this and may need to be */ 51 /* rewritten but for now as a start just to get some output: */ 52 DisplaySurface *ds = qemu_console_surface(s->vga.con); 53 DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, 54 s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), 55 surface_bits_per_pixel(ds), 56 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); 57 unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? 58 s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); 59 unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 60 s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); 61 int bpp = ati_bpp_from_datatype(s); 62 if (!bpp) { 63 qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); 64 return; 65 } 66 int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch; 67 if (!dst_stride) { 68 qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); 69 return; 70 } 71 uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? 72 s->regs.dst_offset : s->regs.default_offset); 73 74 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 75 dst_bits += s->regs.crtc_offset & 0x07ffffff; 76 dst_stride *= bpp; 77 } 78 uint8_t *end = s->vga.vram_ptr + s->vga.vram_size; 79 if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >= end 80 || dst_bits + dst_x 81 + (dst_y + s->regs.dst_height) * dst_stride >= end) { 82 qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); 83 return; 84 } 85 DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", 86 s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, 87 s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, 88 s->regs.src_x, s->regs.src_y, dst_x, dst_y, 89 s->regs.dst_width, s->regs.dst_height, 90 (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), 91 (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); 92 switch (s->regs.dp_mix & GMC_ROP3_MASK) { 93 case ROP3_SRCCOPY: 94 { 95 unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? 96 s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width); 97 unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 98 s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height); 99 int src_stride = DEFAULT_CNTL ? 100 s->regs.src_pitch : s->regs.default_pitch; 101 if (!src_stride) { 102 qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); 103 return; 104 } 105 uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? 106 s->regs.src_offset : s->regs.default_offset); 107 108 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 109 src_bits += s->regs.crtc_offset & 0x07ffffff; 110 src_stride *= bpp; 111 } 112 if (src_x > 0x3fff || src_y > 0x3fff || src_bits >= end 113 || src_bits + src_x 114 + (src_y + s->regs.dst_height) * src_stride >= end) { 115 qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); 116 return; 117 } 118 119 src_stride /= sizeof(uint32_t); 120 dst_stride /= sizeof(uint32_t); 121 DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n", 122 src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, 123 src_x, src_y, dst_x, dst_y, 124 s->regs.dst_width, s->regs.dst_height); 125 if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && 126 s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { 127 pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, 128 src_stride, dst_stride, bpp, bpp, 129 src_x, src_y, dst_x, dst_y, 130 s->regs.dst_width, s->regs.dst_height); 131 } else { 132 /* FIXME: We only really need a temporary if src and dst overlap */ 133 int llb = s->regs.dst_width * (bpp / 8); 134 int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t)); 135 uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) * 136 s->regs.dst_height); 137 pixman_blt((uint32_t *)src_bits, tmp, 138 src_stride, tmp_stride, bpp, bpp, 139 src_x, src_y, 0, 0, 140 s->regs.dst_width, s->regs.dst_height); 141 pixman_blt(tmp, (uint32_t *)dst_bits, 142 tmp_stride, dst_stride, bpp, bpp, 143 0, 0, dst_x, dst_y, 144 s->regs.dst_width, s->regs.dst_height); 145 g_free(tmp); 146 } 147 if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && 148 dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + 149 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { 150 memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + 151 s->regs.dst_offset + 152 dst_y * surface_stride(ds), 153 s->regs.dst_height * surface_stride(ds)); 154 } 155 s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? 156 dst_x + s->regs.dst_width : dst_x); 157 s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 158 dst_y + s->regs.dst_height : dst_y); 159 break; 160 } 161 case ROP3_PATCOPY: 162 case ROP3_BLACKNESS: 163 case ROP3_WHITENESS: 164 { 165 uint32_t filler = 0; 166 167 switch (s->regs.dp_mix & GMC_ROP3_MASK) { 168 case ROP3_PATCOPY: 169 filler = s->regs.dp_brush_frgd_clr; 170 break; 171 case ROP3_BLACKNESS: 172 filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0], 173 s->vga.palette[1], s->vga.palette[2]); 174 break; 175 case ROP3_WHITENESS: 176 filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3], 177 s->vga.palette[4], s->vga.palette[5]); 178 break; 179 } 180 181 dst_stride /= sizeof(uint32_t); 182 DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", 183 dst_bits, dst_stride, bpp, 184 dst_x, dst_y, 185 s->regs.dst_width, s->regs.dst_height, 186 filler); 187 pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, 188 dst_x, dst_y, 189 s->regs.dst_width, s->regs.dst_height, 190 filler); 191 if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && 192 dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + 193 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { 194 memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + 195 s->regs.dst_offset + 196 dst_y * surface_stride(ds), 197 s->regs.dst_height * surface_stride(ds)); 198 } 199 s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 200 dst_y + s->regs.dst_height : dst_y); 201 break; 202 } 203 default: 204 qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", 205 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); 206 } 207 }