arm11mpcore.c (5906B)
1 /* 2 * ARM11MPCore internal peripheral emulation. 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "qemu/module.h" 13 #include "hw/cpu/arm11mpcore.h" 14 #include "hw/intc/realview_gic.h" 15 #include "hw/irq.h" 16 #include "hw/qdev-properties.h" 17 18 #define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 19 20 static void mpcore_priv_set_irq(void *opaque, int irq, int level) 21 { 22 ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; 23 24 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); 25 } 26 27 static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) 28 { 29 int i; 30 SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); 31 DeviceState *gicdev = DEVICE(&s->gic); 32 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); 33 SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); 34 SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); 35 36 memory_region_add_subregion(&s->container, 0, 37 sysbus_mmio_get_region(scubusdev, 0)); 38 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs 39 * at 0x200, 0x300... 40 */ 41 for (i = 0; i < (s->num_cpu + 1); i++) { 42 hwaddr offset = 0x100 + (i * 0x100); 43 memory_region_add_subregion(&s->container, offset, 44 sysbus_mmio_get_region(gicbusdev, i + 1)); 45 } 46 /* Add the regions for timer and watchdog for "current CPU" and 47 * for each specific CPU. 48 */ 49 for (i = 0; i < (s->num_cpu + 1); i++) { 50 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ 51 hwaddr offset = 0x600 + i * 0x100; 52 memory_region_add_subregion(&s->container, offset, 53 sysbus_mmio_get_region(timerbusdev, i)); 54 memory_region_add_subregion(&s->container, offset + 0x20, 55 sysbus_mmio_get_region(wdtbusdev, i)); 56 } 57 memory_region_add_subregion(&s->container, 0x1000, 58 sysbus_mmio_get_region(gicbusdev, 0)); 59 /* Wire up the interrupt from each watchdog and timer. 60 * For each core the timer is PPI 29 and the watchdog PPI 30. 61 */ 62 for (i = 0; i < s->num_cpu; i++) { 63 int ppibase = (s->num_irq - 32) + i * 32; 64 sysbus_connect_irq(timerbusdev, i, 65 qdev_get_gpio_in(gicdev, ppibase + 29)); 66 sysbus_connect_irq(wdtbusdev, i, 67 qdev_get_gpio_in(gicdev, ppibase + 30)); 68 } 69 } 70 71 static void mpcore_priv_realize(DeviceState *dev, Error **errp) 72 { 73 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 74 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); 75 DeviceState *scudev = DEVICE(&s->scu); 76 DeviceState *gicdev = DEVICE(&s->gic); 77 DeviceState *mptimerdev = DEVICE(&s->mptimer); 78 DeviceState *wdtimerdev = DEVICE(&s->wdtimer); 79 80 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); 81 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 82 return; 83 } 84 85 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); 86 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); 87 qdev_prop_set_uint32(gicdev, "num-priority-bits", 88 ARM11MPCORE_NUM_GIC_PRIORITY_BITS); 89 90 91 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { 92 return; 93 } 94 95 /* Pass through outbound IRQ lines from the GIC */ 96 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); 97 98 /* Pass through inbound GPIO lines to the GIC */ 99 qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); 100 101 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); 102 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { 103 return; 104 } 105 106 qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); 107 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), errp)) { 108 return; 109 } 110 111 mpcore_priv_map_setup(s); 112 } 113 114 static void mpcore_priv_initfn(Object *obj) 115 { 116 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 117 ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); 118 119 memory_region_init(&s->container, OBJECT(s), 120 "mpcore-priv-container", 0x2000); 121 sysbus_init_mmio(sbd, &s->container); 122 123 object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU); 124 125 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); 126 /* Request the legacy 11MPCore GIC behaviour: */ 127 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); 128 129 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); 130 131 object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER); 132 } 133 134 static Property mpcore_priv_properties[] = { 135 DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), 136 /* The ARM11 MPCORE TRM says the on-chip controller may have 137 * anything from 0 to 224 external interrupt IRQ lines (with another 138 * 32 internal). We default to 32+32, which is the number provided by 139 * the ARM11 MPCore test chip in the Realview Versatile Express 140 * coretile. Other boards may differ and should set this property 141 * appropriately. Some Linux kernels may not boot if the hardware 142 * has more IRQ lines than the kernel expects. 143 */ 144 DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), 145 DEFINE_PROP_END_OF_LIST(), 146 }; 147 148 static void mpcore_priv_class_init(ObjectClass *klass, void *data) 149 { 150 DeviceClass *dc = DEVICE_CLASS(klass); 151 152 dc->realize = mpcore_priv_realize; 153 device_class_set_props(dc, mpcore_priv_properties); 154 } 155 156 static const TypeInfo mpcore_priv_info = { 157 .name = TYPE_ARM11MPCORE_PRIV, 158 .parent = TYPE_SYS_BUS_DEVICE, 159 .instance_size = sizeof(ARM11MPCorePriveState), 160 .instance_init = mpcore_priv_initfn, 161 .class_init = mpcore_priv_class_init, 162 }; 163 164 static void arm11mpcore_register_types(void) 165 { 166 type_register_static(&mpcore_priv_info); 167 } 168 169 type_init(arm11mpcore_register_types)