xilinx_uartlite.c (6845B)
1 /* 2 * QEMU model of Xilinx uartlite. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/log.h" 27 #include "hw/irq.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/qdev-properties-system.h" 30 #include "hw/sysbus.h" 31 #include "qemu/module.h" 32 #include "chardev/char-fe.h" 33 #include "qom/object.h" 34 35 #define DUART(x) 36 37 #define R_RX 0 38 #define R_TX 1 39 #define R_STATUS 2 40 #define R_CTRL 3 41 #define R_MAX 4 42 43 #define STATUS_RXVALID 0x01 44 #define STATUS_RXFULL 0x02 45 #define STATUS_TXEMPTY 0x04 46 #define STATUS_TXFULL 0x08 47 #define STATUS_IE 0x10 48 #define STATUS_OVERRUN 0x20 49 #define STATUS_FRAME 0x40 50 #define STATUS_PARITY 0x80 51 52 #define CONTROL_RST_TX 0x01 53 #define CONTROL_RST_RX 0x02 54 #define CONTROL_IE 0x10 55 56 #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" 57 OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) 58 59 struct XilinxUARTLite { 60 SysBusDevice parent_obj; 61 62 MemoryRegion mmio; 63 CharBackend chr; 64 qemu_irq irq; 65 66 uint8_t rx_fifo[8]; 67 unsigned int rx_fifo_pos; 68 unsigned int rx_fifo_len; 69 70 uint32_t regs[R_MAX]; 71 }; 72 73 static void uart_update_irq(XilinxUARTLite *s) 74 { 75 unsigned int irq; 76 77 if (s->rx_fifo_len) 78 s->regs[R_STATUS] |= STATUS_IE; 79 80 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); 81 qemu_set_irq(s->irq, irq); 82 } 83 84 static void uart_update_status(XilinxUARTLite *s) 85 { 86 uint32_t r; 87 88 r = s->regs[R_STATUS]; 89 r &= ~7; 90 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */ 91 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; 92 r |= (!!s->rx_fifo_len); 93 s->regs[R_STATUS] = r; 94 } 95 96 static void xilinx_uartlite_reset(DeviceState *dev) 97 { 98 uart_update_status(XILINX_UARTLITE(dev)); 99 } 100 101 static uint64_t 102 uart_read(void *opaque, hwaddr addr, unsigned int size) 103 { 104 XilinxUARTLite *s = opaque; 105 uint32_t r = 0; 106 addr >>= 2; 107 switch (addr) 108 { 109 case R_RX: 110 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; 111 if (s->rx_fifo_len) 112 s->rx_fifo_len--; 113 uart_update_status(s); 114 uart_update_irq(s); 115 qemu_chr_fe_accept_input(&s->chr); 116 break; 117 118 default: 119 if (addr < ARRAY_SIZE(s->regs)) 120 r = s->regs[addr]; 121 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r)); 122 break; 123 } 124 return r; 125 } 126 127 static void 128 uart_write(void *opaque, hwaddr addr, 129 uint64_t val64, unsigned int size) 130 { 131 XilinxUARTLite *s = opaque; 132 uint32_t value = val64; 133 unsigned char ch = value; 134 135 addr >>= 2; 136 switch (addr) 137 { 138 case R_STATUS: 139 qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n", 140 __func__); 141 break; 142 143 case R_CTRL: 144 if (value & CONTROL_RST_RX) { 145 s->rx_fifo_pos = 0; 146 s->rx_fifo_len = 0; 147 } 148 s->regs[addr] = value; 149 break; 150 151 case R_TX: 152 /* XXX this blocks entire thread. Rewrite to use 153 * qemu_chr_fe_write and background I/O callbacks */ 154 qemu_chr_fe_write_all(&s->chr, &ch, 1); 155 s->regs[addr] = value; 156 157 /* hax. */ 158 s->regs[R_STATUS] |= STATUS_IE; 159 break; 160 161 default: 162 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value)); 163 if (addr < ARRAY_SIZE(s->regs)) 164 s->regs[addr] = value; 165 break; 166 } 167 uart_update_status(s); 168 uart_update_irq(s); 169 } 170 171 static const MemoryRegionOps uart_ops = { 172 .read = uart_read, 173 .write = uart_write, 174 .endianness = DEVICE_NATIVE_ENDIAN, 175 .valid = { 176 .min_access_size = 1, 177 .max_access_size = 4 178 } 179 }; 180 181 static Property xilinx_uartlite_properties[] = { 182 DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), 183 DEFINE_PROP_END_OF_LIST(), 184 }; 185 186 static void uart_rx(void *opaque, const uint8_t *buf, int size) 187 { 188 XilinxUARTLite *s = opaque; 189 190 /* Got a byte. */ 191 if (s->rx_fifo_len >= 8) { 192 printf("WARNING: UART dropped char.\n"); 193 return; 194 } 195 s->rx_fifo[s->rx_fifo_pos] = *buf; 196 s->rx_fifo_pos++; 197 s->rx_fifo_pos &= 0x7; 198 s->rx_fifo_len++; 199 200 uart_update_status(s); 201 uart_update_irq(s); 202 } 203 204 static int uart_can_rx(void *opaque) 205 { 206 XilinxUARTLite *s = opaque; 207 208 return s->rx_fifo_len < sizeof(s->rx_fifo); 209 } 210 211 static void uart_event(void *opaque, QEMUChrEvent event) 212 { 213 214 } 215 216 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp) 217 { 218 XilinxUARTLite *s = XILINX_UARTLITE(dev); 219 220 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, 221 uart_event, NULL, s, NULL, true); 222 } 223 224 static void xilinx_uartlite_init(Object *obj) 225 { 226 XilinxUARTLite *s = XILINX_UARTLITE(obj); 227 228 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 229 230 memory_region_init_io(&s->mmio, obj, &uart_ops, s, 231 "xlnx.xps-uartlite", R_MAX * 4); 232 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 233 } 234 235 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) 236 { 237 DeviceClass *dc = DEVICE_CLASS(klass); 238 239 dc->reset = xilinx_uartlite_reset; 240 dc->realize = xilinx_uartlite_realize; 241 device_class_set_props(dc, xilinx_uartlite_properties); 242 } 243 244 static const TypeInfo xilinx_uartlite_info = { 245 .name = TYPE_XILINX_UARTLITE, 246 .parent = TYPE_SYS_BUS_DEVICE, 247 .instance_size = sizeof(XilinxUARTLite), 248 .instance_init = xilinx_uartlite_init, 249 .class_init = xilinx_uartlite_class_init, 250 }; 251 252 static void xilinx_uart_register_types(void) 253 { 254 type_register_static(&xilinx_uartlite_info); 255 } 256 257 type_init(xilinx_uart_register_types)