xlnx-versal.c (28775B)
1 /* 2 * Xilinx Versal SoC model. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/units.h" 14 #include "qapi/error.h" 15 #include "qemu/module.h" 16 #include "hw/sysbus.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/kvm.h" 20 #include "hw/arm/boot.h" 21 #include "kvm_arm.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/arm/xlnx-versal.h" 24 #include "qemu/log.h" 25 #include "hw/sysbus.h" 26 27 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") 28 #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") 29 #define GEM_REVISION 0x40070106 30 31 #define VERSAL_NUM_PMC_APB_IRQS 3 32 #define NUM_OSPI_IRQ_LINES 3 33 34 static void versal_create_apu_cpus(Versal *s) 35 { 36 int i; 37 38 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, 39 TYPE_CPU_CLUSTER); 40 qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); 41 42 for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { 43 Object *obj; 44 45 object_initialize_child(OBJECT(&s->fpd.apu.cluster), 46 "apu-cpu[*]", &s->fpd.apu.cpu[i], 47 XLNX_VERSAL_ACPU_TYPE); 48 obj = OBJECT(&s->fpd.apu.cpu[i]); 49 if (i) { 50 /* Secondary CPUs start in powered-down state */ 51 object_property_set_bool(obj, "start-powered-off", true, 52 &error_abort); 53 } 54 55 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), 56 &error_abort); 57 object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr), 58 &error_abort); 59 qdev_realize(DEVICE(obj), NULL, &error_fatal); 60 } 61 62 qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); 63 } 64 65 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) 66 { 67 static const uint64_t addrs[] = { 68 MM_GIC_APU_DIST_MAIN, 69 MM_GIC_APU_REDIST_0 70 }; 71 SysBusDevice *gicbusdev; 72 DeviceState *gicdev; 73 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); 74 int i; 75 76 object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, 77 gicv3_class_name()); 78 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); 79 gicdev = DEVICE(&s->fpd.apu.gic); 80 qdev_prop_set_uint32(gicdev, "revision", 3); 81 qdev_prop_set_uint32(gicdev, "num-cpu", nr_apu_cpus); 82 qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); 83 qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); 84 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", nr_apu_cpus); 85 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 86 87 sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); 88 89 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 90 MemoryRegion *mr; 91 92 mr = sysbus_mmio_get_region(gicbusdev, i); 93 memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); 94 } 95 96 for (i = 0; i < nr_apu_cpus; i++) { 97 DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); 98 int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 99 qemu_irq maint_irq; 100 int ti; 101 /* Mapping from the output timer irq lines from the CPU to the 102 * GIC PPI inputs. 103 */ 104 const int timer_irq[] = { 105 [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, 106 [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, 107 [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, 108 [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, 109 }; 110 111 for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { 112 qdev_connect_gpio_out(cpudev, ti, 113 qdev_get_gpio_in(gicdev, 114 ppibase + timer_irq[ti])); 115 } 116 maint_irq = qdev_get_gpio_in(gicdev, 117 ppibase + VERSAL_GIC_MAINT_IRQ); 118 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 119 0, maint_irq); 120 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 121 sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, 122 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 123 sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, 124 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 125 sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, 126 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 127 } 128 129 for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { 130 pic[i] = qdev_get_gpio_in(gicdev, i); 131 } 132 } 133 134 static void versal_create_rpu_cpus(Versal *s) 135 { 136 int i; 137 138 object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, 139 TYPE_CPU_CLUSTER); 140 qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); 141 142 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 143 Object *obj; 144 145 object_initialize_child(OBJECT(&s->lpd.rpu.cluster), 146 "rpu-cpu[*]", &s->lpd.rpu.cpu[i], 147 XLNX_VERSAL_RCPU_TYPE); 148 obj = OBJECT(&s->lpd.rpu.cpu[i]); 149 object_property_set_bool(obj, "start-powered-off", true, 150 &error_abort); 151 152 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort); 153 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu), 154 &error_abort); 155 object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), 156 &error_abort); 157 qdev_realize(DEVICE(obj), NULL, &error_fatal); 158 } 159 160 qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); 161 } 162 163 static void versal_create_uarts(Versal *s, qemu_irq *pic) 164 { 165 int i; 166 167 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 168 static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; 169 static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; 170 char *name = g_strdup_printf("uart%d", i); 171 DeviceState *dev; 172 MemoryRegion *mr; 173 174 object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], 175 TYPE_PL011); 176 dev = DEVICE(&s->lpd.iou.uart[i]); 177 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 178 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 179 180 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 181 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 182 183 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 184 g_free(name); 185 } 186 } 187 188 static void versal_create_usbs(Versal *s, qemu_irq *pic) 189 { 190 DeviceState *dev; 191 MemoryRegion *mr; 192 193 object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, 194 TYPE_XILINX_VERSAL_USB2); 195 dev = DEVICE(&s->lpd.iou.usb); 196 197 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 198 &error_abort); 199 qdev_prop_set_uint32(dev, "intrs", 1); 200 qdev_prop_set_uint32(dev, "slots", 2); 201 202 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 203 204 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 205 memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); 206 207 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); 208 209 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 210 memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); 211 } 212 213 static void versal_create_gems(Versal *s, qemu_irq *pic) 214 { 215 int i; 216 217 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 218 static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; 219 static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; 220 char *name = g_strdup_printf("gem%d", i); 221 NICInfo *nd = &nd_table[i]; 222 DeviceState *dev; 223 MemoryRegion *mr; 224 225 object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], 226 TYPE_CADENCE_GEM); 227 dev = DEVICE(&s->lpd.iou.gem[i]); 228 /* FIXME use qdev NIC properties instead of nd_table[] */ 229 if (nd->used) { 230 qemu_check_nic_model(nd, "cadence_gem"); 231 qdev_set_nic_properties(dev, nd); 232 } 233 object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); 234 object_property_set_int(OBJECT(dev), "num-priority-queues", 2, 235 &error_abort); 236 object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 237 &error_abort); 238 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 239 240 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 241 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); 242 243 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); 244 g_free(name); 245 } 246 } 247 248 static void versal_create_admas(Versal *s, qemu_irq *pic) 249 { 250 int i; 251 252 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 253 char *name = g_strdup_printf("adma%d", i); 254 DeviceState *dev; 255 MemoryRegion *mr; 256 257 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 258 TYPE_XLNX_ZDMA); 259 dev = DEVICE(&s->lpd.iou.adma[i]); 260 object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort); 261 object_property_set_link(OBJECT(dev), "dma", 262 OBJECT(get_system_memory()), &error_fatal); 263 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 264 265 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 266 memory_region_add_subregion(&s->mr_ps, 267 MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); 268 269 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); 270 g_free(name); 271 } 272 } 273 274 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ 275 static void versal_create_sds(Versal *s, qemu_irq *pic) 276 { 277 int i; 278 279 for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { 280 DeviceState *dev; 281 MemoryRegion *mr; 282 283 object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], 284 TYPE_SYSBUS_SDHCI); 285 dev = DEVICE(&s->pmc.iou.sd[i]); 286 287 object_property_set_uint(OBJECT(dev), "sd-spec-version", 3, 288 &error_fatal); 289 object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES, 290 &error_fatal); 291 object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal); 292 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 293 294 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 295 memory_region_add_subregion(&s->mr_ps, 296 MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); 297 298 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 299 pic[VERSAL_SD0_IRQ_0 + i * 2]); 300 } 301 } 302 303 static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) 304 { 305 DeviceState *orgate; 306 307 /* 308 * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following 309 * models: 310 * - RTC 311 * - BBRAM 312 * - PMC SLCR 313 */ 314 object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", 315 &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); 316 orgate = DEVICE(&s->pmc.apb_irq_orgate); 317 object_property_set_int(OBJECT(orgate), 318 "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal); 319 qdev_realize(orgate, NULL, &error_fatal); 320 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); 321 } 322 323 static void versal_create_rtc(Versal *s, qemu_irq *pic) 324 { 325 SysBusDevice *sbd; 326 MemoryRegion *mr; 327 328 object_initialize_child(OBJECT(s), "rtc", &s->pmc.rtc, 329 TYPE_XLNX_ZYNQMP_RTC); 330 sbd = SYS_BUS_DEVICE(&s->pmc.rtc); 331 sysbus_realize(SYS_BUS_DEVICE(sbd), &error_fatal); 332 333 mr = sysbus_mmio_get_region(sbd, 0); 334 memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); 335 336 /* 337 * TODO: Connect the ALARM and SECONDS interrupts once our RTC model 338 * supports them. 339 */ 340 sysbus_connect_irq(sbd, 1, 341 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); 342 } 343 344 static void versal_create_xrams(Versal *s, qemu_irq *pic) 345 { 346 int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl); 347 DeviceState *orgate; 348 int i; 349 350 /* XRAM IRQs get ORed into a single line. */ 351 object_initialize_child(OBJECT(s), "xram-irq-orgate", 352 &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); 353 orgate = DEVICE(&s->lpd.xram.irq_orgate); 354 object_property_set_int(OBJECT(orgate), 355 "num-lines", nr_xrams, &error_fatal); 356 qdev_realize(orgate, NULL, &error_fatal); 357 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]); 358 359 for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) { 360 SysBusDevice *sbd; 361 MemoryRegion *mr; 362 363 object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i], 364 TYPE_XLNX_XRAM_CTRL); 365 sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]); 366 sysbus_realize(sbd, &error_fatal); 367 368 mr = sysbus_mmio_get_region(sbd, 0); 369 memory_region_add_subregion(&s->mr_ps, 370 MM_XRAMC + i * MM_XRAMC_SIZE, mr); 371 mr = sysbus_mmio_get_region(sbd, 1); 372 memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr); 373 374 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i)); 375 } 376 } 377 378 static void versal_create_bbram(Versal *s, qemu_irq *pic) 379 { 380 SysBusDevice *sbd; 381 382 object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, 383 sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, 384 &error_fatal, 385 "crc-zpads", "0", 386 NULL); 387 sbd = SYS_BUS_DEVICE(&s->pmc.bbram); 388 389 sysbus_realize(sbd, &error_fatal); 390 memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, 391 sysbus_mmio_get_region(sbd, 0)); 392 sysbus_connect_irq(sbd, 0, 393 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1)); 394 } 395 396 static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) 397 { 398 SysBusDevice *part = SYS_BUS_DEVICE(dev); 399 400 object_property_set_link(OBJECT(part), "efuse", 401 OBJECT(&s->pmc.efuse), &error_abort); 402 403 sysbus_realize(part, &error_abort); 404 memory_region_add_subregion(&s->mr_ps, base, 405 sysbus_mmio_get_region(part, 0)); 406 } 407 408 static void versal_create_efuse(Versal *s, qemu_irq *pic) 409 { 410 Object *bits = OBJECT(&s->pmc.efuse); 411 Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); 412 Object *cache = OBJECT(&s->pmc.efuse_cache); 413 414 object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, 415 TYPE_XLNX_VERSAL_EFUSE_CTRL); 416 417 object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, 418 TYPE_XLNX_VERSAL_EFUSE_CACHE); 419 420 object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, 421 sizeof(s->pmc.efuse), 422 TYPE_XLNX_EFUSE, &error_abort, 423 "efuse-nr", "3", 424 "efuse-size", "8192", 425 NULL); 426 427 qdev_realize(DEVICE(bits), NULL, &error_abort); 428 versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); 429 versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); 430 431 sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); 432 } 433 434 static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) 435 { 436 SysBusDevice *sbd; 437 438 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, 439 TYPE_XILINX_VERSAL_PMC_IOU_SLCR); 440 441 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); 442 sysbus_realize(sbd, &error_fatal); 443 444 memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, 445 sysbus_mmio_get_region(sbd, 0)); 446 447 sysbus_connect_irq(sbd, 0, 448 qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); 449 } 450 451 static void versal_create_ospi(Versal *s, qemu_irq *pic) 452 { 453 SysBusDevice *sbd; 454 MemoryRegion *mr_dac; 455 qemu_irq ospi_mux_sel; 456 DeviceState *orgate; 457 458 memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), 459 "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); 460 461 object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi, 462 TYPE_XILINX_VERSAL_OSPI); 463 464 mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1); 465 memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); 466 467 /* Create the OSPI destination DMA */ 468 object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", 469 &s->pmc.iou.ospi.dma_dst, 470 TYPE_XLNX_CSU_DMA); 471 472 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), 473 "dma", OBJECT(get_system_memory()), 474 &error_abort); 475 476 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); 477 sysbus_realize(sbd, &error_fatal); 478 479 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, 480 sysbus_mmio_get_region(sbd, 0)); 481 482 /* Create the OSPI source DMA */ 483 object_initialize_child(OBJECT(s), "versal-ospi-dma-src", 484 &s->pmc.iou.ospi.dma_src, 485 TYPE_XLNX_CSU_DMA); 486 487 object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", 488 false, &error_abort); 489 490 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 491 "dma", OBJECT(mr_dac), &error_abort); 492 493 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), 494 "stream-connected-dma", 495 OBJECT(&s->pmc.iou.ospi.dma_dst), 496 &error_abort); 497 498 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); 499 sysbus_realize(sbd, &error_fatal); 500 501 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, 502 sysbus_mmio_get_region(sbd, 0)); 503 504 /* Realize the OSPI */ 505 object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", 506 OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort); 507 508 sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); 509 sysbus_realize(sbd, &error_fatal); 510 511 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, 512 sysbus_mmio_get_region(sbd, 0)); 513 514 memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, 515 &s->pmc.iou.ospi.linear_mr); 516 517 /* ospi_mux_sel */ 518 ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi), 519 "ospi-mux-sel", 0); 520 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, 521 ospi_mux_sel); 522 523 /* OSPI irq */ 524 object_initialize_child(OBJECT(s), "ospi-irq-orgate", 525 &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ); 526 object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate), 527 "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); 528 529 orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate); 530 qdev_realize(orgate, NULL, &error_fatal); 531 532 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, 533 qdev_get_gpio_in(orgate, 0)); 534 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, 535 qdev_get_gpio_in(orgate, 1)); 536 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, 537 qdev_get_gpio_in(orgate, 2)); 538 539 qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); 540 } 541 542 static void versal_create_crl(Versal *s, qemu_irq *pic) 543 { 544 SysBusDevice *sbd; 545 int i; 546 547 object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, 548 TYPE_XLNX_VERSAL_CRL); 549 sbd = SYS_BUS_DEVICE(&s->lpd.crl); 550 551 for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { 552 g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); 553 554 object_property_set_link(OBJECT(&s->lpd.crl), 555 name, OBJECT(&s->lpd.rpu.cpu[i]), 556 &error_abort); 557 } 558 559 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { 560 g_autofree gchar *name = g_strdup_printf("gem[%d]", i); 561 562 object_property_set_link(OBJECT(&s->lpd.crl), 563 name, OBJECT(&s->lpd.iou.gem[i]), 564 &error_abort); 565 } 566 567 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { 568 g_autofree gchar *name = g_strdup_printf("adma[%d]", i); 569 570 object_property_set_link(OBJECT(&s->lpd.crl), 571 name, OBJECT(&s->lpd.iou.adma[i]), 572 &error_abort); 573 } 574 575 for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { 576 g_autofree gchar *name = g_strdup_printf("uart[%d]", i); 577 578 object_property_set_link(OBJECT(&s->lpd.crl), 579 name, OBJECT(&s->lpd.iou.uart[i]), 580 &error_abort); 581 } 582 583 object_property_set_link(OBJECT(&s->lpd.crl), 584 "usb", OBJECT(&s->lpd.iou.usb), 585 &error_abort); 586 587 sysbus_realize(sbd, &error_fatal); 588 memory_region_add_subregion(&s->mr_ps, MM_CRL, 589 sysbus_mmio_get_region(sbd, 0)); 590 sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); 591 } 592 593 /* This takes the board allocated linear DDR memory and creates aliases 594 * for each split DDR range/aperture on the Versal address map. 595 */ 596 static void versal_map_ddr(Versal *s) 597 { 598 uint64_t size = memory_region_size(s->cfg.mr_ddr); 599 /* Describes the various split DDR access regions. */ 600 static const struct { 601 uint64_t base; 602 uint64_t size; 603 } addr_ranges[] = { 604 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 605 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 606 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 607 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 608 }; 609 uint64_t offset = 0; 610 int i; 611 612 assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); 613 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 614 char *name; 615 uint64_t mapsize; 616 617 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 618 name = g_strdup_printf("noc-ddr-range%d", i); 619 /* Create the MR alias. */ 620 memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), 621 name, s->cfg.mr_ddr, 622 offset, mapsize); 623 624 /* Map it onto the NoC MR. */ 625 memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, 626 &s->noc.mr_ddr_ranges[i]); 627 offset += mapsize; 628 size -= mapsize; 629 g_free(name); 630 } 631 } 632 633 static void versal_unimp_area(Versal *s, const char *name, 634 MemoryRegion *mr, 635 hwaddr base, hwaddr size) 636 { 637 DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 638 MemoryRegion *mr_dev; 639 640 qdev_prop_set_string(dev, "name", name); 641 qdev_prop_set_uint64(dev, "size", size); 642 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 643 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 644 645 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 646 memory_region_add_subregion(mr, base, mr_dev); 647 } 648 649 static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level) 650 { 651 qemu_log_mask(LOG_UNIMP, 652 "Selecting between enabling SD mode or eMMC mode on " 653 "controller %d is not yet implemented\n", n); 654 } 655 656 static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level) 657 { 658 qemu_log_mask(LOG_UNIMP, 659 "Selecting between enabling the QSPI or OSPI linear address " 660 "region is not yet implemented\n"); 661 } 662 663 static void versal_unimp_irq_parity_imr(void *opaque, int n, int level) 664 { 665 qemu_log_mask(LOG_UNIMP, 666 "PMC SLCR parity interrupt behaviour " 667 "is not yet implemented\n"); 668 } 669 670 static void versal_unimp(Versal *s) 671 { 672 qemu_irq gpio_in; 673 674 versal_unimp_area(s, "psm", &s->mr_ps, 675 MM_PSM_START, MM_PSM_END - MM_PSM_START); 676 versal_unimp_area(s, "crf", &s->mr_ps, 677 MM_FPD_CRF, MM_FPD_CRF_SIZE); 678 versal_unimp_area(s, "apu", &s->mr_ps, 679 MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE); 680 versal_unimp_area(s, "crp", &s->mr_ps, 681 MM_PMC_CRP, MM_PMC_CRP_SIZE); 682 versal_unimp_area(s, "iou-scntr", &s->mr_ps, 683 MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); 684 versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, 685 MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); 686 687 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, 688 "sd-emmc-sel-dummy", 2); 689 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel, 690 "qspi-ospi-mux-sel-dummy", 1); 691 qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr, 692 "irq-parity-imr-dummy", 1); 693 694 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0); 695 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, 696 gpio_in); 697 698 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1); 699 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, 700 gpio_in); 701 702 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); 703 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 704 "qspi-ospi-mux-sel", 0, 705 gpio_in); 706 707 gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); 708 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), 709 SYSBUS_DEVICE_GPIO_IRQ, 0, 710 gpio_in); 711 } 712 713 static void versal_realize(DeviceState *dev, Error **errp) 714 { 715 Versal *s = XLNX_VERSAL(dev); 716 qemu_irq pic[XLNX_VERSAL_NR_IRQS]; 717 718 versal_create_apu_cpus(s); 719 versal_create_apu_gic(s, pic); 720 versal_create_rpu_cpus(s); 721 versal_create_uarts(s, pic); 722 versal_create_usbs(s, pic); 723 versal_create_gems(s, pic); 724 versal_create_admas(s, pic); 725 versal_create_sds(s, pic); 726 versal_create_pmc_apb_irq_orgate(s, pic); 727 versal_create_rtc(s, pic); 728 versal_create_xrams(s, pic); 729 versal_create_bbram(s, pic); 730 versal_create_efuse(s, pic); 731 versal_create_pmc_iou_slcr(s, pic); 732 versal_create_ospi(s, pic); 733 versal_create_crl(s, pic); 734 versal_map_ddr(s); 735 versal_unimp(s); 736 737 /* Create the On Chip Memory (OCM). */ 738 memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", 739 MM_OCM_SIZE, &error_fatal); 740 741 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); 742 memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); 743 memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, 744 &s->lpd.rpu.mr_ps_alias, 0); 745 } 746 747 static void versal_init(Object *obj) 748 { 749 Versal *s = XLNX_VERSAL(obj); 750 751 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); 752 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); 753 memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); 754 memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), 755 "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); 756 } 757 758 static Property versal_properties[] = { 759 DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, 760 MemoryRegion *), 761 DEFINE_PROP_END_OF_LIST() 762 }; 763 764 static void versal_class_init(ObjectClass *klass, void *data) 765 { 766 DeviceClass *dc = DEVICE_CLASS(klass); 767 768 dc->realize = versal_realize; 769 device_class_set_props(dc, versal_properties); 770 /* No VMSD since we haven't got any top-level SoC state to save. */ 771 } 772 773 static const TypeInfo versal_info = { 774 .name = TYPE_XLNX_VERSAL, 775 .parent = TYPE_SYS_BUS_DEVICE, 776 .instance_size = sizeof(Versal), 777 .instance_init = versal_init, 778 .class_init = versal_class_init, 779 }; 780 781 static void versal_register_types(void) 782 { 783 type_register_static(&versal_info); 784 } 785 786 type_init(versal_register_types);