stm32f405_soc.c (12678B)
1 /* 2 * STM32F405 SoC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qapi/error.h" 27 #include "exec/address-spaces.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/arm/stm32f405_soc.h" 30 #include "hw/qdev-clock.h" 31 #include "hw/misc/unimp.h" 32 33 #define SYSCFG_ADD 0x40013800 34 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, 35 0x40004C00, 0x40005000, 0x40011400, 36 0x40007800, 0x40007C00 }; 37 /* At the moment only Timer 2 to 5 are modelled */ 38 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, 39 0x40000800, 0x40000C00 }; 40 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200, 41 0x40012300, 0x40012400, 0x40012500 }; 42 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, 43 0x40013400, 0x40015000, 0x40015400 }; 44 #define EXTI_ADDR 0x40013C00 45 46 #define SYSCFG_IRQ 71 47 static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 }; 48 static const int timer_irq[] = { 28, 29, 30, 50 }; 49 #define ADC_IRQ 18 50 static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 }; 51 static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40, 52 40, 40, 40, 40, 40} ; 53 54 55 static void stm32f405_soc_initfn(Object *obj) 56 { 57 STM32F405State *s = STM32F405_SOC(obj); 58 int i; 59 60 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 61 62 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG); 63 64 for (i = 0; i < STM_NUM_USARTS; i++) { 65 object_initialize_child(obj, "usart[*]", &s->usart[i], 66 TYPE_STM32F2XX_USART); 67 } 68 69 for (i = 0; i < STM_NUM_TIMERS; i++) { 70 object_initialize_child(obj, "timer[*]", &s->timer[i], 71 TYPE_STM32F2XX_TIMER); 72 } 73 74 for (i = 0; i < STM_NUM_ADCS; i++) { 75 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); 76 } 77 78 for (i = 0; i < STM_NUM_SPIS; i++) { 79 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); 80 } 81 82 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI); 83 84 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 85 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); 86 } 87 88 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) 89 { 90 STM32F405State *s = STM32F405_SOC(dev_soc); 91 MemoryRegion *system_memory = get_system_memory(); 92 DeviceState *dev, *armv7m; 93 SysBusDevice *busdev; 94 Error *err = NULL; 95 int i; 96 97 /* 98 * We use s->refclk internally and only define it with qdev_init_clock_in() 99 * so it is correctly parented and not leaked on an init/deinit; it is not 100 * intended as an externally exposed clock. 101 */ 102 if (clock_has_source(s->refclk)) { 103 error_setg(errp, "refclk clock must not be wired up by the board code"); 104 return; 105 } 106 107 if (!clock_has_source(s->sysclk)) { 108 error_setg(errp, "sysclk clock must be wired up by the board code"); 109 return; 110 } 111 112 /* 113 * TODO: ideally we should model the SoC RCC and its ability to 114 * change the sysclk frequency and define different sysclk sources. 115 */ 116 117 /* The refclk always runs at frequency HCLK / 8 */ 118 clock_set_mul_div(s->refclk, 8, 1); 119 clock_set_source(s->refclk, s->sysclk); 120 121 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash", 122 FLASH_SIZE, &err); 123 if (err != NULL) { 124 error_propagate(errp, err); 125 return; 126 } 127 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 128 "STM32F405.flash.alias", &s->flash, 0, 129 FLASH_SIZE); 130 131 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); 132 memory_region_add_subregion(system_memory, 0, &s->flash_alias); 133 134 memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, 135 &err); 136 if (err != NULL) { 137 error_propagate(errp, err); 138 return; 139 } 140 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); 141 142 armv7m = DEVICE(&s->armv7m); 143 qdev_prop_set_uint32(armv7m, "num-irq", 96); 144 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 145 qdev_prop_set_bit(armv7m, "enable-bitband", true); 146 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 147 qdev_connect_clock_in(armv7m, "refclk", s->refclk); 148 object_property_set_link(OBJECT(&s->armv7m), "memory", 149 OBJECT(system_memory), &error_abort); 150 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 151 return; 152 } 153 154 /* System configuration controller */ 155 dev = DEVICE(&s->syscfg); 156 if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) { 157 return; 158 } 159 busdev = SYS_BUS_DEVICE(dev); 160 sysbus_mmio_map(busdev, 0, SYSCFG_ADD); 161 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); 162 163 /* Attach UART (uses USART registers) and USART controllers */ 164 for (i = 0; i < STM_NUM_USARTS; i++) { 165 dev = DEVICE(&(s->usart[i])); 166 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 167 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { 168 return; 169 } 170 busdev = SYS_BUS_DEVICE(dev); 171 sysbus_mmio_map(busdev, 0, usart_addr[i]); 172 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); 173 } 174 175 /* Timer 2 to 5 */ 176 for (i = 0; i < STM_NUM_TIMERS; i++) { 177 dev = DEVICE(&(s->timer[i])); 178 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); 179 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { 180 return; 181 } 182 busdev = SYS_BUS_DEVICE(dev); 183 sysbus_mmio_map(busdev, 0, timer_addr[i]); 184 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); 185 } 186 187 /* ADC device, the IRQs are ORed together */ 188 if (!object_initialize_child_with_props(OBJECT(s), "adc-orirq", 189 &s->adc_irqs, sizeof(s->adc_irqs), 190 TYPE_OR_IRQ, errp, NULL)) { 191 return; 192 } 193 object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS, 194 &error_abort); 195 if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, errp)) { 196 return; 197 } 198 qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, 199 qdev_get_gpio_in(armv7m, ADC_IRQ)); 200 201 for (i = 0; i < STM_NUM_ADCS; i++) { 202 dev = DEVICE(&(s->adc[i])); 203 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) { 204 return; 205 } 206 busdev = SYS_BUS_DEVICE(dev); 207 sysbus_mmio_map(busdev, 0, adc_addr[i]); 208 sysbus_connect_irq(busdev, 0, 209 qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); 210 } 211 212 /* SPI devices */ 213 for (i = 0; i < STM_NUM_SPIS; i++) { 214 dev = DEVICE(&(s->spi[i])); 215 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 216 return; 217 } 218 busdev = SYS_BUS_DEVICE(dev); 219 sysbus_mmio_map(busdev, 0, spi_addr[i]); 220 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); 221 } 222 223 /* EXTI device */ 224 dev = DEVICE(&s->exti); 225 if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) { 226 return; 227 } 228 busdev = SYS_BUS_DEVICE(dev); 229 sysbus_mmio_map(busdev, 0, EXTI_ADDR); 230 for (i = 0; i < 16; i++) { 231 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); 232 } 233 for (i = 0; i < 16; i++) { 234 qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i)); 235 } 236 237 create_unimplemented_device("timer[7]", 0x40001400, 0x400); 238 create_unimplemented_device("timer[12]", 0x40001800, 0x400); 239 create_unimplemented_device("timer[6]", 0x40001000, 0x400); 240 create_unimplemented_device("timer[13]", 0x40001C00, 0x400); 241 create_unimplemented_device("timer[14]", 0x40002000, 0x400); 242 create_unimplemented_device("RTC and BKP", 0x40002800, 0x400); 243 create_unimplemented_device("WWDG", 0x40002C00, 0x400); 244 create_unimplemented_device("IWDG", 0x40003000, 0x400); 245 create_unimplemented_device("I2S2ext", 0x40003000, 0x400); 246 create_unimplemented_device("I2S3ext", 0x40004000, 0x400); 247 create_unimplemented_device("I2C1", 0x40005400, 0x400); 248 create_unimplemented_device("I2C2", 0x40005800, 0x400); 249 create_unimplemented_device("I2C3", 0x40005C00, 0x400); 250 create_unimplemented_device("CAN1", 0x40006400, 0x400); 251 create_unimplemented_device("CAN2", 0x40006800, 0x400); 252 create_unimplemented_device("PWR", 0x40007000, 0x400); 253 create_unimplemented_device("DAC", 0x40007400, 0x400); 254 create_unimplemented_device("timer[1]", 0x40010000, 0x400); 255 create_unimplemented_device("timer[8]", 0x40010400, 0x400); 256 create_unimplemented_device("SDIO", 0x40012C00, 0x400); 257 create_unimplemented_device("timer[9]", 0x40014000, 0x400); 258 create_unimplemented_device("timer[10]", 0x40014400, 0x400); 259 create_unimplemented_device("timer[11]", 0x40014800, 0x400); 260 create_unimplemented_device("GPIOA", 0x40020000, 0x400); 261 create_unimplemented_device("GPIOB", 0x40020400, 0x400); 262 create_unimplemented_device("GPIOC", 0x40020800, 0x400); 263 create_unimplemented_device("GPIOD", 0x40020C00, 0x400); 264 create_unimplemented_device("GPIOE", 0x40021000, 0x400); 265 create_unimplemented_device("GPIOF", 0x40021400, 0x400); 266 create_unimplemented_device("GPIOG", 0x40021800, 0x400); 267 create_unimplemented_device("GPIOH", 0x40021C00, 0x400); 268 create_unimplemented_device("GPIOI", 0x40022000, 0x400); 269 create_unimplemented_device("CRC", 0x40023000, 0x400); 270 create_unimplemented_device("RCC", 0x40023800, 0x400); 271 create_unimplemented_device("Flash Int", 0x40023C00, 0x400); 272 create_unimplemented_device("BKPSRAM", 0x40024000, 0x400); 273 create_unimplemented_device("DMA1", 0x40026000, 0x400); 274 create_unimplemented_device("DMA2", 0x40026400, 0x400); 275 create_unimplemented_device("Ethernet", 0x40028000, 0x1400); 276 create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000); 277 create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000); 278 create_unimplemented_device("DCMI", 0x50050000, 0x400); 279 create_unimplemented_device("RNG", 0x50060800, 0x400); 280 } 281 282 static Property stm32f405_soc_properties[] = { 283 DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), 284 DEFINE_PROP_END_OF_LIST(), 285 }; 286 287 static void stm32f405_soc_class_init(ObjectClass *klass, void *data) 288 { 289 DeviceClass *dc = DEVICE_CLASS(klass); 290 291 dc->realize = stm32f405_soc_realize; 292 device_class_set_props(dc, stm32f405_soc_properties); 293 /* No vmstate or reset required: device has no internal state */ 294 } 295 296 static const TypeInfo stm32f405_soc_info = { 297 .name = TYPE_STM32F405_SOC, 298 .parent = TYPE_SYS_BUS_DEVICE, 299 .instance_size = sizeof(STM32F405State), 300 .instance_init = stm32f405_soc_initfn, 301 .class_init = stm32f405_soc_class_init, 302 }; 303 304 static void stm32f405_soc_types(void) 305 { 306 type_register_static(&stm32f405_soc_info); 307 } 308 309 type_init(stm32f405_soc_types)