integratorcp.c (22033B)
1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "hw/boards.h" 16 #include "hw/arm/boot.h" 17 #include "hw/misc/arm_integrator_debug.h" 18 #include "hw/net/smc91c111.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/runstate.h" 22 #include "sysemu/sysemu.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "hw/char/pl011.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sd/sd.h" 29 #include "qom/object.h" 30 31 #define TYPE_INTEGRATOR_CM "integrator_core" 32 OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM) 33 34 struct IntegratorCMState { 35 /*< private >*/ 36 SysBusDevice parent_obj; 37 /*< public >*/ 38 39 MemoryRegion iomem; 40 uint32_t memsz; 41 MemoryRegion flash; 42 uint32_t cm_osc; 43 uint32_t cm_ctrl; 44 uint32_t cm_lock; 45 uint32_t cm_auxosc; 46 uint32_t cm_sdram; 47 uint32_t cm_init; 48 uint32_t cm_flags; 49 uint32_t cm_nvflags; 50 uint32_t cm_refcnt_offset; 51 uint32_t int_level; 52 uint32_t irq_enabled; 53 uint32_t fiq_enabled; 54 }; 55 56 static uint8_t integrator_spd[128] = { 57 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 58 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 59 }; 60 61 static const VMStateDescription vmstate_integratorcm = { 62 .name = "integratorcm", 63 .version_id = 1, 64 .minimum_version_id = 1, 65 .fields = (VMStateField[]) { 66 VMSTATE_UINT32(cm_osc, IntegratorCMState), 67 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 68 VMSTATE_UINT32(cm_lock, IntegratorCMState), 69 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 70 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 71 VMSTATE_UINT32(cm_init, IntegratorCMState), 72 VMSTATE_UINT32(cm_flags, IntegratorCMState), 73 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 74 VMSTATE_UINT32(int_level, IntegratorCMState), 75 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 76 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 77 VMSTATE_END_OF_LIST() 78 } 79 }; 80 81 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 82 unsigned size) 83 { 84 IntegratorCMState *s = opaque; 85 if (offset >= 0x100 && offset < 0x200) { 86 /* CM_SPD */ 87 if (offset >= 0x180) 88 return 0; 89 return integrator_spd[offset >> 2]; 90 } 91 switch (offset >> 2) { 92 case 0: /* CM_ID */ 93 return 0x411a3001; 94 case 1: /* CM_PROC */ 95 return 0; 96 case 2: /* CM_OSC */ 97 return s->cm_osc; 98 case 3: /* CM_CTRL */ 99 return s->cm_ctrl; 100 case 4: /* CM_STAT */ 101 return 0x00100000; 102 case 5: /* CM_LOCK */ 103 if (s->cm_lock == 0xa05f) { 104 return 0x1a05f; 105 } else { 106 return s->cm_lock; 107 } 108 case 6: /* CM_LMBUSCNT */ 109 /* ??? High frequency timer. */ 110 hw_error("integratorcm_read: CM_LMBUSCNT"); 111 case 7: /* CM_AUXOSC */ 112 return s->cm_auxosc; 113 case 8: /* CM_SDRAM */ 114 return s->cm_sdram; 115 case 9: /* CM_INIT */ 116 return s->cm_init; 117 case 10: /* CM_REFCNT */ 118 /* This register, CM_REFCNT, provides a 32-bit count value. 119 * The count increments at the fixed reference clock frequency of 24MHz 120 * and can be used as a real-time counter. 121 */ 122 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 123 1000) - s->cm_refcnt_offset; 124 case 12: /* CM_FLAGS */ 125 return s->cm_flags; 126 case 14: /* CM_NVFLAGS */ 127 return s->cm_nvflags; 128 case 16: /* CM_IRQ_STAT */ 129 return s->int_level & s->irq_enabled; 130 case 17: /* CM_IRQ_RSTAT */ 131 return s->int_level; 132 case 18: /* CM_IRQ_ENSET */ 133 return s->irq_enabled; 134 case 20: /* CM_SOFT_INTSET */ 135 return s->int_level & 1; 136 case 24: /* CM_FIQ_STAT */ 137 return s->int_level & s->fiq_enabled; 138 case 25: /* CM_FIQ_RSTAT */ 139 return s->int_level; 140 case 26: /* CM_FIQ_ENSET */ 141 return s->fiq_enabled; 142 case 32: /* CM_VOLTAGE_CTL0 */ 143 case 33: /* CM_VOLTAGE_CTL1 */ 144 case 34: /* CM_VOLTAGE_CTL2 */ 145 case 35: /* CM_VOLTAGE_CTL3 */ 146 /* ??? Voltage control unimplemented. */ 147 return 0; 148 default: 149 qemu_log_mask(LOG_UNIMP, 150 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", 151 __func__, offset); 152 return 0; 153 } 154 } 155 156 static void integratorcm_do_remap(IntegratorCMState *s) 157 { 158 /* Sync memory region state with CM_CTRL REMAP bit: 159 * bit 0 => flash at address 0; bit 1 => RAM 160 */ 161 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 162 } 163 164 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 165 { 166 if (value & 8) { 167 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 168 } 169 if ((s->cm_ctrl ^ value) & 1) { 170 /* (value & 1) != 0 means the green "MISC LED" is lit. 171 * We don't have any nice place to display LEDs. printf is a bad 172 * idea because Linux uses the LED as a heartbeat and the output 173 * will swamp anything else on the terminal. 174 */ 175 } 176 /* Note that the RESET bit [3] always reads as zero */ 177 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 178 integratorcm_do_remap(s); 179 } 180 181 static void integratorcm_update(IntegratorCMState *s) 182 { 183 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 184 are active. */ 185 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 186 hw_error("Core module interrupt\n"); 187 } 188 189 static void integratorcm_write(void *opaque, hwaddr offset, 190 uint64_t value, unsigned size) 191 { 192 IntegratorCMState *s = opaque; 193 switch (offset >> 2) { 194 case 2: /* CM_OSC */ 195 if (s->cm_lock == 0xa05f) 196 s->cm_osc = value; 197 break; 198 case 3: /* CM_CTRL */ 199 integratorcm_set_ctrl(s, value); 200 break; 201 case 5: /* CM_LOCK */ 202 s->cm_lock = value & 0xffff; 203 break; 204 case 7: /* CM_AUXOSC */ 205 if (s->cm_lock == 0xa05f) 206 s->cm_auxosc = value; 207 break; 208 case 8: /* CM_SDRAM */ 209 s->cm_sdram = value; 210 break; 211 case 9: /* CM_INIT */ 212 /* ??? This can change the memory bus frequency. */ 213 s->cm_init = value; 214 break; 215 case 12: /* CM_FLAGSS */ 216 s->cm_flags |= value; 217 break; 218 case 13: /* CM_FLAGSC */ 219 s->cm_flags &= ~value; 220 break; 221 case 14: /* CM_NVFLAGSS */ 222 s->cm_nvflags |= value; 223 break; 224 case 15: /* CM_NVFLAGSS */ 225 s->cm_nvflags &= ~value; 226 break; 227 case 18: /* CM_IRQ_ENSET */ 228 s->irq_enabled |= value; 229 integratorcm_update(s); 230 break; 231 case 19: /* CM_IRQ_ENCLR */ 232 s->irq_enabled &= ~value; 233 integratorcm_update(s); 234 break; 235 case 20: /* CM_SOFT_INTSET */ 236 s->int_level |= (value & 1); 237 integratorcm_update(s); 238 break; 239 case 21: /* CM_SOFT_INTCLR */ 240 s->int_level &= ~(value & 1); 241 integratorcm_update(s); 242 break; 243 case 26: /* CM_FIQ_ENSET */ 244 s->fiq_enabled |= value; 245 integratorcm_update(s); 246 break; 247 case 27: /* CM_FIQ_ENCLR */ 248 s->fiq_enabled &= ~value; 249 integratorcm_update(s); 250 break; 251 case 32: /* CM_VOLTAGE_CTL0 */ 252 case 33: /* CM_VOLTAGE_CTL1 */ 253 case 34: /* CM_VOLTAGE_CTL2 */ 254 case 35: /* CM_VOLTAGE_CTL3 */ 255 /* ??? Voltage control unimplemented. */ 256 break; 257 default: 258 qemu_log_mask(LOG_UNIMP, 259 "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", 260 __func__, offset); 261 break; 262 } 263 } 264 265 /* Integrator/CM control registers. */ 266 267 static const MemoryRegionOps integratorcm_ops = { 268 .read = integratorcm_read, 269 .write = integratorcm_write, 270 .endianness = DEVICE_NATIVE_ENDIAN, 271 }; 272 273 static void integratorcm_init(Object *obj) 274 { 275 IntegratorCMState *s = INTEGRATOR_CM(obj); 276 277 s->cm_osc = 0x01000048; 278 /* ??? What should the high bits of this value be? */ 279 s->cm_auxosc = 0x0007feff; 280 s->cm_sdram = 0x00011122; 281 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 282 s->cm_init = 0x00000112; 283 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 284 1000); 285 286 /* ??? Save/restore. */ 287 } 288 289 static void integratorcm_realize(DeviceState *d, Error **errp) 290 { 291 IntegratorCMState *s = INTEGRATOR_CM(d); 292 SysBusDevice *dev = SYS_BUS_DEVICE(d); 293 Error *local_err = NULL; 294 295 memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000, 296 &local_err); 297 if (local_err) { 298 error_propagate(errp, local_err); 299 return; 300 } 301 302 memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, 303 "integratorcm", 0x00800000); 304 sysbus_init_mmio(dev, &s->iomem); 305 306 integratorcm_do_remap(s); 307 308 if (s->memsz >= 256) { 309 integrator_spd[31] = 64; 310 s->cm_sdram |= 0x10; 311 } else if (s->memsz >= 128) { 312 integrator_spd[31] = 32; 313 s->cm_sdram |= 0x0c; 314 } else if (s->memsz >= 64) { 315 integrator_spd[31] = 16; 316 s->cm_sdram |= 0x08; 317 } else if (s->memsz >= 32) { 318 integrator_spd[31] = 4; 319 s->cm_sdram |= 0x04; 320 } else { 321 integrator_spd[31] = 2; 322 } 323 } 324 325 /* Integrator/CP hardware emulation. */ 326 /* Primary interrupt controller. */ 327 328 #define TYPE_INTEGRATOR_PIC "integrator_pic" 329 OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state, INTEGRATOR_PIC) 330 331 struct icp_pic_state { 332 /*< private >*/ 333 SysBusDevice parent_obj; 334 /*< public >*/ 335 336 MemoryRegion iomem; 337 uint32_t level; 338 uint32_t irq_enabled; 339 uint32_t fiq_enabled; 340 qemu_irq parent_irq; 341 qemu_irq parent_fiq; 342 }; 343 344 static const VMStateDescription vmstate_icp_pic = { 345 .name = "icp_pic", 346 .version_id = 1, 347 .minimum_version_id = 1, 348 .fields = (VMStateField[]) { 349 VMSTATE_UINT32(level, icp_pic_state), 350 VMSTATE_UINT32(irq_enabled, icp_pic_state), 351 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 352 VMSTATE_END_OF_LIST() 353 } 354 }; 355 356 static void icp_pic_update(icp_pic_state *s) 357 { 358 uint32_t flags; 359 360 flags = (s->level & s->irq_enabled); 361 qemu_set_irq(s->parent_irq, flags != 0); 362 flags = (s->level & s->fiq_enabled); 363 qemu_set_irq(s->parent_fiq, flags != 0); 364 } 365 366 static void icp_pic_set_irq(void *opaque, int irq, int level) 367 { 368 icp_pic_state *s = (icp_pic_state *)opaque; 369 if (level) 370 s->level |= 1 << irq; 371 else 372 s->level &= ~(1 << irq); 373 icp_pic_update(s); 374 } 375 376 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 377 unsigned size) 378 { 379 icp_pic_state *s = (icp_pic_state *)opaque; 380 381 switch (offset >> 2) { 382 case 0: /* IRQ_STATUS */ 383 return s->level & s->irq_enabled; 384 case 1: /* IRQ_RAWSTAT */ 385 return s->level; 386 case 2: /* IRQ_ENABLESET */ 387 return s->irq_enabled; 388 case 4: /* INT_SOFTSET */ 389 return s->level & 1; 390 case 8: /* FRQ_STATUS */ 391 return s->level & s->fiq_enabled; 392 case 9: /* FRQ_RAWSTAT */ 393 return s->level; 394 case 10: /* FRQ_ENABLESET */ 395 return s->fiq_enabled; 396 case 3: /* IRQ_ENABLECLR */ 397 case 5: /* INT_SOFTCLR */ 398 case 11: /* FRQ_ENABLECLR */ 399 default: 400 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 401 __func__, offset); 402 return 0; 403 } 404 } 405 406 static void icp_pic_write(void *opaque, hwaddr offset, 407 uint64_t value, unsigned size) 408 { 409 icp_pic_state *s = (icp_pic_state *)opaque; 410 411 switch (offset >> 2) { 412 case 2: /* IRQ_ENABLESET */ 413 s->irq_enabled |= value; 414 break; 415 case 3: /* IRQ_ENABLECLR */ 416 s->irq_enabled &= ~value; 417 break; 418 case 4: /* INT_SOFTSET */ 419 if (value & 1) 420 icp_pic_set_irq(s, 0, 1); 421 break; 422 case 5: /* INT_SOFTCLR */ 423 if (value & 1) 424 icp_pic_set_irq(s, 0, 0); 425 break; 426 case 10: /* FRQ_ENABLESET */ 427 s->fiq_enabled |= value; 428 break; 429 case 11: /* FRQ_ENABLECLR */ 430 s->fiq_enabled &= ~value; 431 break; 432 case 0: /* IRQ_STATUS */ 433 case 1: /* IRQ_RAWSTAT */ 434 case 8: /* FRQ_STATUS */ 435 case 9: /* FRQ_RAWSTAT */ 436 default: 437 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 438 __func__, offset); 439 return; 440 } 441 icp_pic_update(s); 442 } 443 444 static const MemoryRegionOps icp_pic_ops = { 445 .read = icp_pic_read, 446 .write = icp_pic_write, 447 .endianness = DEVICE_NATIVE_ENDIAN, 448 }; 449 450 static void icp_pic_init(Object *obj) 451 { 452 DeviceState *dev = DEVICE(obj); 453 icp_pic_state *s = INTEGRATOR_PIC(obj); 454 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 455 456 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 457 sysbus_init_irq(sbd, &s->parent_irq); 458 sysbus_init_irq(sbd, &s->parent_fiq); 459 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 460 "icp-pic", 0x00800000); 461 sysbus_init_mmio(sbd, &s->iomem); 462 } 463 464 /* CP control registers. */ 465 466 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 467 OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState, ICP_CONTROL_REGS) 468 469 struct ICPCtrlRegsState { 470 /*< private >*/ 471 SysBusDevice parent_obj; 472 /*< public >*/ 473 474 MemoryRegion iomem; 475 476 qemu_irq mmc_irq; 477 uint32_t intreg_state; 478 }; 479 480 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 481 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 482 483 #define ICP_INTREG_WPROT (1 << 0) 484 #define ICP_INTREG_CARDIN (1 << 3) 485 486 static const VMStateDescription vmstate_icp_control = { 487 .name = "icp_control", 488 .version_id = 1, 489 .minimum_version_id = 1, 490 .fields = (VMStateField[]) { 491 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 492 VMSTATE_END_OF_LIST() 493 } 494 }; 495 496 static uint64_t icp_control_read(void *opaque, hwaddr offset, 497 unsigned size) 498 { 499 ICPCtrlRegsState *s = opaque; 500 501 switch (offset >> 2) { 502 case 0: /* CP_IDFIELD */ 503 return 0x41034003; 504 case 1: /* CP_FLASHPROG */ 505 return 0; 506 case 2: /* CP_INTREG */ 507 return s->intreg_state; 508 case 3: /* CP_DECODE */ 509 return 0x11; 510 default: 511 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 512 __func__, offset); 513 return 0; 514 } 515 } 516 517 static void icp_control_write(void *opaque, hwaddr offset, 518 uint64_t value, unsigned size) 519 { 520 ICPCtrlRegsState *s = opaque; 521 522 switch (offset >> 2) { 523 case 2: /* CP_INTREG */ 524 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 525 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 526 break; 527 case 1: /* CP_FLASHPROG */ 528 case 3: /* CP_DECODE */ 529 /* Nothing interesting implemented yet. */ 530 break; 531 default: 532 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 533 __func__, offset); 534 } 535 } 536 537 static const MemoryRegionOps icp_control_ops = { 538 .read = icp_control_read, 539 .write = icp_control_write, 540 .endianness = DEVICE_NATIVE_ENDIAN, 541 }; 542 543 static void icp_control_mmc_wprot(void *opaque, int line, int level) 544 { 545 ICPCtrlRegsState *s = opaque; 546 547 s->intreg_state &= ~ICP_INTREG_WPROT; 548 if (level) { 549 s->intreg_state |= ICP_INTREG_WPROT; 550 } 551 } 552 553 static void icp_control_mmc_cardin(void *opaque, int line, int level) 554 { 555 ICPCtrlRegsState *s = opaque; 556 557 /* line is released by writing to CP_INTREG */ 558 if (level) { 559 s->intreg_state |= ICP_INTREG_CARDIN; 560 qemu_set_irq(s->mmc_irq, 1); 561 } 562 } 563 564 static void icp_control_init(Object *obj) 565 { 566 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 567 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 568 DeviceState *dev = DEVICE(obj); 569 570 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 571 "icp_ctrl_regs", 0x00800000); 572 sysbus_init_mmio(sbd, &s->iomem); 573 574 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 575 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 576 ICP_GPIO_MMC_CARDIN, 1); 577 sysbus_init_irq(sbd, &s->mmc_irq); 578 } 579 580 581 /* Board init. */ 582 583 static struct arm_boot_info integrator_binfo = { 584 .loader_start = 0x0, 585 .board_id = 0x113, 586 }; 587 588 static void integratorcp_init(MachineState *machine) 589 { 590 ram_addr_t ram_size = machine->ram_size; 591 Object *cpuobj; 592 ARMCPU *cpu; 593 MemoryRegion *address_space_mem = get_system_memory(); 594 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 595 qemu_irq pic[32]; 596 DeviceState *dev, *sic, *icp; 597 DriveInfo *dinfo; 598 int i; 599 600 cpuobj = object_new(machine->cpu_type); 601 602 /* By default ARM1176 CPUs have EL3 enabled. This board does not 603 * currently support EL3 so the CPU EL3 property is disabled before 604 * realization. 605 */ 606 if (object_property_find(cpuobj, "has_el3")) { 607 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 608 } 609 610 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 611 612 cpu = ARM_CPU(cpuobj); 613 614 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 615 /* ??? RAM should repeat to fill physical memory space. */ 616 /* SDRAM at address zero*/ 617 memory_region_add_subregion(address_space_mem, 0, machine->ram); 618 /* And again at address 0x80000000 */ 619 memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram, 620 0, ram_size); 621 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 622 623 dev = qdev_new(TYPE_INTEGRATOR_CM); 624 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 625 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 626 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 627 628 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 629 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 630 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 631 NULL); 632 for (i = 0; i < 32; i++) { 633 pic[i] = qdev_get_gpio_in(dev, i); 634 } 635 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 636 sysbus_create_varargs("integrator_pit", 0x13000000, 637 pic[5], pic[6], pic[7], NULL); 638 sysbus_create_simple("pl031", 0x15000000, pic[8]); 639 pl011_create(0x16000000, pic[1], serial_hd(0)); 640 pl011_create(0x17000000, pic[2], serial_hd(1)); 641 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 642 qdev_get_gpio_in(sic, 3)); 643 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 644 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 645 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 646 647 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 648 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 649 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 650 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 651 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 652 dinfo = drive_get(IF_SD, 0, 0); 653 if (dinfo) { 654 DeviceState *card; 655 656 card = qdev_new(TYPE_SD_CARD); 657 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 658 &error_fatal); 659 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 660 &error_fatal); 661 } 662 663 sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL); 664 665 if (nd_table[0].used) 666 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 667 668 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 669 670 integrator_binfo.ram_size = ram_size; 671 arm_load_kernel(cpu, machine, &integrator_binfo); 672 } 673 674 static void integratorcp_machine_init(MachineClass *mc) 675 { 676 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 677 mc->init = integratorcp_init; 678 mc->ignore_memory_transaction_failures = true; 679 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 680 mc->default_ram_id = "integrator.ram"; 681 } 682 683 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 684 685 static Property core_properties[] = { 686 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 687 DEFINE_PROP_END_OF_LIST(), 688 }; 689 690 static void core_class_init(ObjectClass *klass, void *data) 691 { 692 DeviceClass *dc = DEVICE_CLASS(klass); 693 694 device_class_set_props(dc, core_properties); 695 dc->realize = integratorcm_realize; 696 dc->vmsd = &vmstate_integratorcm; 697 } 698 699 static void icp_pic_class_init(ObjectClass *klass, void *data) 700 { 701 DeviceClass *dc = DEVICE_CLASS(klass); 702 703 dc->vmsd = &vmstate_icp_pic; 704 } 705 706 static void icp_control_class_init(ObjectClass *klass, void *data) 707 { 708 DeviceClass *dc = DEVICE_CLASS(klass); 709 710 dc->vmsd = &vmstate_icp_control; 711 } 712 713 static const TypeInfo core_info = { 714 .name = TYPE_INTEGRATOR_CM, 715 .parent = TYPE_SYS_BUS_DEVICE, 716 .instance_size = sizeof(IntegratorCMState), 717 .instance_init = integratorcm_init, 718 .class_init = core_class_init, 719 }; 720 721 static const TypeInfo icp_pic_info = { 722 .name = TYPE_INTEGRATOR_PIC, 723 .parent = TYPE_SYS_BUS_DEVICE, 724 .instance_size = sizeof(icp_pic_state), 725 .instance_init = icp_pic_init, 726 .class_init = icp_pic_class_init, 727 }; 728 729 static const TypeInfo icp_ctrl_regs_info = { 730 .name = TYPE_ICP_CONTROL_REGS, 731 .parent = TYPE_SYS_BUS_DEVICE, 732 .instance_size = sizeof(ICPCtrlRegsState), 733 .instance_init = icp_control_init, 734 .class_init = icp_control_class_init, 735 }; 736 737 static void integratorcp_register_types(void) 738 { 739 type_register_static(&icp_pic_info); 740 type_register_static(&core_info); 741 type_register_static(&icp_ctrl_regs_info); 742 } 743 744 type_init(integratorcp_register_types)