fsl-imx6.c (17180B)
1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "hw/usb/imx-usb-phy.h" 26 #include "hw/boards.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/sysemu.h" 29 #include "chardev/char.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 34 35 #define NAME_SIZE 20 36 37 static void fsl_imx6_init(Object *obj) 38 { 39 MachineState *ms = MACHINE(qdev_get_machine()); 40 FslIMX6State *s = FSL_IMX6(obj); 41 char name[NAME_SIZE]; 42 int i; 43 44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { 45 snprintf(name, NAME_SIZE, "cpu%d", i); 46 object_initialize_child(obj, name, &s->cpu[i], 47 ARM_CPU_TYPE_NAME("cortex-a9")); 48 } 49 50 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); 51 52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); 53 54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 55 56 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 57 snprintf(name, NAME_SIZE, "uart%d", i + 1); 58 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 59 } 60 61 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT); 62 63 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 64 snprintf(name, NAME_SIZE, "epit%d", i + 1); 65 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 66 } 67 68 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 69 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 70 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 71 } 72 73 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 74 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 75 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 76 } 77 78 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 79 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 80 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC); 81 } 82 83 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 84 snprintf(name, NAME_SIZE, "usbphy%d", i); 85 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 86 } 87 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 88 snprintf(name, NAME_SIZE, "usb%d", i); 89 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 90 } 91 92 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 93 snprintf(name, NAME_SIZE, "spi%d", i + 1); 94 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 95 } 96 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 97 snprintf(name, NAME_SIZE, "wdt%d", i); 98 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 99 } 100 101 102 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); 103 } 104 105 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 106 { 107 MachineState *ms = MACHINE(qdev_get_machine()); 108 FslIMX6State *s = FSL_IMX6(dev); 109 uint16_t i; 110 Error *err = NULL; 111 unsigned int smp_cpus = ms->smp.cpus; 112 113 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 114 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 115 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 116 return; 117 } 118 119 for (i = 0; i < smp_cpus; i++) { 120 121 /* On uniprocessor, the CBAR is set to 0 */ 122 if (smp_cpus > 1) { 123 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 124 FSL_IMX6_A9MPCORE_ADDR, &error_abort); 125 } 126 127 /* All CPU but CPU 0 start in power off mode */ 128 if (i) { 129 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 130 true, &error_abort); 131 } 132 133 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 134 return; 135 } 136 } 137 138 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, 139 &error_abort); 140 141 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", 142 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); 143 144 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { 145 return; 146 } 147 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 148 149 for (i = 0; i < smp_cpus; i++) { 150 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 151 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 153 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 154 } 155 156 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { 157 return; 158 } 159 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 160 161 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) { 162 return; 163 } 164 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 165 166 /* Initialize all UARTs */ 167 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 168 static const struct { 169 hwaddr addr; 170 unsigned int irq; 171 } serial_table[FSL_IMX6_NUM_UARTS] = { 172 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 173 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 174 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 175 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 176 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 177 }; 178 179 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 180 181 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { 182 return; 183 } 184 185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 186 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 187 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 188 serial_table[i].irq)); 189 } 190 191 s->gpt.ccm = IMX_CCM(&s->ccm); 192 193 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { 194 return; 195 } 196 197 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 198 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 199 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 200 FSL_IMX6_GPT_IRQ)); 201 202 /* Initialize all EPIT timers */ 203 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 204 static const struct { 205 hwaddr addr; 206 unsigned int irq; 207 } epit_table[FSL_IMX6_NUM_EPITS] = { 208 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 209 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 210 }; 211 212 s->epit[i].ccm = IMX_CCM(&s->ccm); 213 214 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { 215 return; 216 } 217 218 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 219 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 220 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 221 epit_table[i].irq)); 222 } 223 224 /* Initialize all I2C */ 225 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 226 static const struct { 227 hwaddr addr; 228 unsigned int irq; 229 } i2c_table[FSL_IMX6_NUM_I2CS] = { 230 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 231 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 232 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 233 }; 234 235 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { 236 return; 237 } 238 239 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 240 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 241 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 242 i2c_table[i].irq)); 243 } 244 245 /* Initialize all GPIOs */ 246 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 247 static const struct { 248 hwaddr addr; 249 unsigned int irq_low; 250 unsigned int irq_high; 251 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 252 { 253 FSL_IMX6_GPIO1_ADDR, 254 FSL_IMX6_GPIO1_LOW_IRQ, 255 FSL_IMX6_GPIO1_HIGH_IRQ 256 }, 257 { 258 FSL_IMX6_GPIO2_ADDR, 259 FSL_IMX6_GPIO2_LOW_IRQ, 260 FSL_IMX6_GPIO2_HIGH_IRQ 261 }, 262 { 263 FSL_IMX6_GPIO3_ADDR, 264 FSL_IMX6_GPIO3_LOW_IRQ, 265 FSL_IMX6_GPIO3_HIGH_IRQ 266 }, 267 { 268 FSL_IMX6_GPIO4_ADDR, 269 FSL_IMX6_GPIO4_LOW_IRQ, 270 FSL_IMX6_GPIO4_HIGH_IRQ 271 }, 272 { 273 FSL_IMX6_GPIO5_ADDR, 274 FSL_IMX6_GPIO5_LOW_IRQ, 275 FSL_IMX6_GPIO5_HIGH_IRQ 276 }, 277 { 278 FSL_IMX6_GPIO6_ADDR, 279 FSL_IMX6_GPIO6_LOW_IRQ, 280 FSL_IMX6_GPIO6_HIGH_IRQ 281 }, 282 { 283 FSL_IMX6_GPIO7_ADDR, 284 FSL_IMX6_GPIO7_LOW_IRQ, 285 FSL_IMX6_GPIO7_HIGH_IRQ 286 }, 287 }; 288 289 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 290 &error_abort); 291 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 292 true, &error_abort); 293 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { 294 return; 295 } 296 297 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 299 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 300 gpio_table[i].irq_low)); 301 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 302 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 303 gpio_table[i].irq_high)); 304 } 305 306 /* Initialize all SDHC */ 307 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 308 static const struct { 309 hwaddr addr; 310 unsigned int irq; 311 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 312 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 313 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 314 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 315 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 316 }; 317 318 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 319 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, 320 &error_abort); 321 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 322 IMX6_ESDHC_CAPABILITIES, &error_abort); 323 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 324 SDHCI_VENDOR_IMX, &error_abort); 325 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { 326 return; 327 } 328 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 330 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 331 esdhc_table[i].irq)); 332 } 333 334 /* USB */ 335 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 336 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 338 FSL_IMX6_USBPHY1_ADDR + i * 0x1000); 339 } 340 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 341 static const int FSL_IMX6_USBn_IRQ[] = { 342 FSL_IMX6_USB_OTG_IRQ, 343 FSL_IMX6_USB_HOST1_IRQ, 344 FSL_IMX6_USB_HOST2_IRQ, 345 FSL_IMX6_USB_HOST3_IRQ, 346 }; 347 348 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 350 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); 351 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 352 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 353 FSL_IMX6_USBn_IRQ[i])); 354 } 355 356 /* Initialize all ECSPI */ 357 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 358 static const struct { 359 hwaddr addr; 360 unsigned int irq; 361 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 362 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 363 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 364 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 365 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 366 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 367 }; 368 369 /* Initialize the SPI */ 370 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 371 return; 372 } 373 374 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 375 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 376 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 377 spi_table[i].irq)); 378 } 379 380 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err); 381 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 382 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { 383 return; 384 } 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 387 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 388 FSL_IMX6_ENET_MAC_IRQ)); 389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 390 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 391 FSL_IMX6_ENET_MAC_1588_IRQ)); 392 393 /* 394 * Watchdog 395 */ 396 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 397 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { 398 FSL_IMX6_WDOG1_ADDR, 399 FSL_IMX6_WDOG2_ADDR, 400 }; 401 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { 402 FSL_IMX6_WDOG1_IRQ, 403 FSL_IMX6_WDOG2_IRQ, 404 }; 405 406 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 407 true, &error_abort); 408 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 409 410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); 411 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 412 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 413 FSL_IMX6_WDOGn_IRQ[i])); 414 } 415 416 /* ROM memory */ 417 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", 418 FSL_IMX6_ROM_SIZE, &err); 419 if (err) { 420 error_propagate(errp, err); 421 return; 422 } 423 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 424 &s->rom); 425 426 /* CAAM memory */ 427 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", 428 FSL_IMX6_CAAM_MEM_SIZE, &err); 429 if (err) { 430 error_propagate(errp, err); 431 return; 432 } 433 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 434 &s->caam); 435 436 /* OCRAM memory */ 437 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, 438 &err); 439 if (err) { 440 error_propagate(errp, err); 441 return; 442 } 443 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 444 &s->ocram); 445 446 /* internal OCRAM (256 KB) is aliased over 1 MB */ 447 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", 448 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 449 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 450 &s->ocram_alias); 451 } 452 453 static Property fsl_imx6_properties[] = { 454 DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), 455 DEFINE_PROP_END_OF_LIST(), 456 }; 457 458 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 459 { 460 DeviceClass *dc = DEVICE_CLASS(oc); 461 462 device_class_set_props(dc, fsl_imx6_properties); 463 dc->realize = fsl_imx6_realize; 464 dc->desc = "i.MX6 SOC"; 465 /* Reason: Uses serial_hd() in the realize() function */ 466 dc->user_creatable = false; 467 } 468 469 static const TypeInfo fsl_imx6_type_info = { 470 .name = TYPE_FSL_IMX6, 471 .parent = TYPE_DEVICE, 472 .instance_size = sizeof(FslIMX6State), 473 .instance_init = fsl_imx6_init, 474 .class_init = fsl_imx6_class_init, 475 }; 476 477 static void fsl_imx6_register_types(void) 478 { 479 type_register_static(&fsl_imx6_type_info); 480 } 481 482 type_init(fsl_imx6_register_types)