nuvoton.rst (3191B)
1 Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) 2 ================================================================ 3 4 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are 5 designed to be used as Baseboard Management Controllers (BMCs) in various 6 servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an 7 assortment of peripherals targeted for either Enterprise or Data Center / 8 Hyperscale applications. The former is a superset of the latter, so NPCM750 has 9 all the peripherals of NPCM730 and more. 10 11 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ 12 13 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise 14 segment. The following machines are based on this chip : 15 16 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board 17 18 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and 19 Hyperscale applications. The following machines are based on this chip : 20 21 - ``quanta-gbs-bmc`` Quanta GBS server BMC 22 - ``quanta-gsj`` Quanta GSJ server BMC 23 - ``kudo-bmc`` Fii USA Kudo server BMC 24 - ``mori-bmc`` Fii USA Mori server BMC 25 26 There are also two more SoCs, NPCM710 and NPCM705, which are single-core 27 variants of NPCM750 and NPCM730, respectively. These are currently not 28 supported by QEMU. 29 30 Supported devices 31 ----------------- 32 33 * SMP (Dual Core Cortex-A9) 34 * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer 35 and Watchdog. 36 * SRAM, ROM and DRAM mappings 37 * System Global Control Registers (GCR) 38 * Clock and reset controller (CLK) 39 * Timer controller (TIM) 40 * Serial ports (16550-based) 41 * DDR4 memory controller (dummy interface indicating memory training is done) 42 * OTP controllers (no protection features) 43 * Flash Interface Unit (FIU; no protection features) 44 * Random Number Generator (RNG) 45 * USB host (USBH) 46 * GPIO controller 47 * Analog to Digital Converter (ADC) 48 * Pulse Width Modulation (PWM) 49 * SMBus controller (SMBF) 50 * Ethernet controller (EMC) 51 * Tachometer 52 53 Missing devices 54 --------------- 55 56 * LPC/eSPI host-to-BMC interface, including 57 58 * Keyboard and mouse controller interface (KBCI) 59 * Keyboard Controller Style (KCS) channels 60 * BIOS POST code FIFO 61 * System Wake-up Control (SWC) 62 * Shared memory (SHM) 63 * eSPI slave interface 64 65 * Ethernet controller (GMAC) 66 * USB device (USBD) 67 * Peripheral SPI controller (PSPI) 68 * SD/MMC host 69 * PECI interface 70 * PCI and PCIe root complex and bridges 71 * VDM and MCTP support 72 * Serial I/O expansion 73 * LPC/eSPI host 74 * Coprocessor 75 * Graphics 76 * Video capture 77 * Encoding compression engine 78 * Security features 79 80 Boot options 81 ------------ 82 83 The Nuvoton machines can boot from an OpenBMC firmware image, or directly into 84 a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and 85 possibly others can be downloaded from the OpenBMC jenkins : 86 87 https://jenkins.openbmc.org/ 88 89 The firmware image should be attached as an MTD drive. Example : 90 91 .. code-block:: bash 92 93 $ qemu-system-arm -machine quanta-gsj -nographic \ 94 -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw 95 96 The default root password for test images is usually ``0penBmc``.