lj_target_ppc.h (7518B)
1 /* 2 ** Definitions for PPC CPUs. 3 ** Copyright (C) 2005-2016 Mike Pall. See Copyright Notice in luajit.h 4 */ 5 6 #ifndef _LJ_TARGET_PPC_H 7 #define _LJ_TARGET_PPC_H 8 9 /* -- Registers IDs ------------------------------------------------------- */ 10 11 #define GPRDEF(_) \ 12 _(R0) _(SP) _(SYS1) _(R3) _(R4) _(R5) _(R6) _(R7) \ 13 _(R8) _(R9) _(R10) _(R11) _(R12) _(SYS2) _(R14) _(R15) \ 14 _(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \ 15 _(R24) _(R25) _(R26) _(R27) _(R28) _(R29) _(R30) _(R31) 16 #define FPRDEF(_) \ 17 _(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \ 18 _(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \ 19 _(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \ 20 _(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31) 21 #define VRIDDEF(_) 22 23 #define RIDENUM(name) RID_##name, 24 25 enum { 26 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */ 27 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */ 28 RID_MAX, 29 RID_TMP = RID_R0, 30 31 /* Calling conventions. */ 32 RID_RET = RID_R3, 33 RID_RETHI = RID_R3, 34 RID_RETLO = RID_R4, 35 RID_FPRET = RID_F1, 36 37 /* These definitions must match with the *.dasc file(s): */ 38 RID_BASE = RID_R14, /* Interpreter BASE. */ 39 RID_LPC = RID_R16, /* Interpreter PC. */ 40 RID_DISPATCH = RID_R17, /* Interpreter DISPATCH table. */ 41 RID_LREG = RID_R18, /* Interpreter L. */ 42 RID_JGL = RID_R31, /* On-trace: global_State + 32768. */ 43 44 /* Register ranges [min, max) and number of registers. */ 45 RID_MIN_GPR = RID_R0, 46 RID_MAX_GPR = RID_R31+1, 47 RID_MIN_FPR = RID_F0, 48 RID_MAX_FPR = RID_F31+1, 49 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR, 50 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR 51 }; 52 53 #define RID_NUM_KREF RID_NUM_GPR 54 #define RID_MIN_KREF RID_R0 55 56 /* -- Register sets ------------------------------------------------------- */ 57 58 /* Make use of all registers, except TMP, SP, SYS1, SYS2 and JGL. */ 59 #define RSET_FIXED \ 60 (RID2RSET(RID_TMP)|RID2RSET(RID_SP)|RID2RSET(RID_SYS1)|\ 61 RID2RSET(RID_SYS2)|RID2RSET(RID_JGL)) 62 #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED) 63 #define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR) 64 #define RSET_ALL (RSET_GPR|RSET_FPR) 65 #define RSET_INIT RSET_ALL 66 67 #define RSET_SCRATCH_GPR (RSET_RANGE(RID_R3, RID_R12+1)) 68 #define RSET_SCRATCH_FPR (RSET_RANGE(RID_F0, RID_F13+1)) 69 #define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR) 70 #define REGARG_FIRSTGPR RID_R3 71 #define REGARG_LASTGPR RID_R10 72 #define REGARG_NUMGPR 8 73 #define REGARG_FIRSTFPR RID_F1 74 #define REGARG_LASTFPR RID_F8 75 #define REGARG_NUMFPR 8 76 77 /* -- Spill slots --------------------------------------------------------- */ 78 79 /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs. 80 ** 81 ** SPS_FIXED: Available fixed spill slots in interpreter frame. 82 ** This definition must match with the *.dasc file(s). 83 ** 84 ** SPS_FIRST: First spill slot for general use. 85 ** [sp+12] tmplo word \ 86 ** [sp+ 8] tmphi word / tmp dword, parameter area for callee 87 ** [sp+ 4] tmpw, LR of callee 88 ** [sp+ 0] stack chain 89 */ 90 #define SPS_FIXED 7 91 #define SPS_FIRST 4 92 93 /* Stack offsets for temporary slots. Used for FP<->int conversions etc. */ 94 #define SPOFS_TMPW 4 95 #define SPOFS_TMP 8 96 #define SPOFS_TMPHI 8 97 #define SPOFS_TMPLO 12 98 99 #define sps_scale(slot) (4 * (int32_t)(slot)) 100 #define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3) 101 102 /* -- Exit state ---------------------------------------------------------- */ 103 104 /* This definition must match with the *.dasc file(s). */ 105 typedef struct { 106 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */ 107 intptr_t gpr[RID_NUM_GPR]; /* General-purpose registers. */ 108 int32_t spill[256]; /* Spill slots. */ 109 } ExitState; 110 111 /* Highest exit + 1 indicates stack check. */ 112 #define EXITSTATE_CHECKEXIT 1 113 114 /* Return the address of a per-trace exit stub. */ 115 static LJ_AINLINE uint32_t *exitstub_trace_addr_(uint32_t *p, uint32_t exitno) 116 { 117 while (*p == 0x60000000) p++; /* Skip PPCI_NOP. */ 118 return p + 3 + exitno; 119 } 120 /* Avoid dependence on lj_jit.h if only including lj_target.h. */ 121 #define exitstub_trace_addr(T, exitno) \ 122 exitstub_trace_addr_((MCode *)((char *)(T)->mcode + (T)->szmcode), (exitno)) 123 124 /* -- Instructions -------------------------------------------------------- */ 125 126 /* Instruction fields. */ 127 #define PPCF_CC(cc) ((((cc) & 3) << 16) | (((cc) & 4) << 22)) 128 #define PPCF_T(r) ((r) << 21) 129 #define PPCF_A(r) ((r) << 16) 130 #define PPCF_B(r) ((r) << 11) 131 #define PPCF_C(r) ((r) << 6) 132 #define PPCF_MB(n) ((n) << 6) 133 #define PPCF_ME(n) ((n) << 1) 134 #define PPCF_Y 0x00200000 135 #define PPCF_DOT 0x00000001 136 137 typedef enum PPCIns { 138 /* Integer instructions. */ 139 PPCI_MR = 0x7c000378, 140 PPCI_NOP = 0x60000000, 141 142 PPCI_LI = 0x38000000, 143 PPCI_LIS = 0x3c000000, 144 145 PPCI_ADD = 0x7c000214, 146 PPCI_ADDC = 0x7c000014, 147 PPCI_ADDO = 0x7c000614, 148 PPCI_ADDE = 0x7c000114, 149 PPCI_ADDZE = 0x7c000194, 150 PPCI_ADDME = 0x7c0001d4, 151 PPCI_ADDI = 0x38000000, 152 PPCI_ADDIS = 0x3c000000, 153 PPCI_ADDIC = 0x30000000, 154 PPCI_ADDICDOT = 0x34000000, 155 156 PPCI_SUBF = 0x7c000050, 157 PPCI_SUBFC = 0x7c000010, 158 PPCI_SUBFO = 0x7c000450, 159 PPCI_SUBFE = 0x7c000110, 160 PPCI_SUBFZE = 0x7c000190, 161 PPCI_SUBFME = 0x7c0001d0, 162 PPCI_SUBFIC = 0x20000000, 163 164 PPCI_NEG = 0x7c0000d0, 165 166 PPCI_AND = 0x7c000038, 167 PPCI_ANDC = 0x7c000078, 168 PPCI_NAND = 0x7c0003b8, 169 PPCI_ANDIDOT = 0x70000000, 170 PPCI_ANDISDOT = 0x74000000, 171 172 PPCI_OR = 0x7c000378, 173 PPCI_NOR = 0x7c0000f8, 174 PPCI_ORI = 0x60000000, 175 PPCI_ORIS = 0x64000000, 176 177 PPCI_XOR = 0x7c000278, 178 PPCI_EQV = 0x7c000238, 179 PPCI_XORI = 0x68000000, 180 PPCI_XORIS = 0x6c000000, 181 182 PPCI_CMPW = 0x7c000000, 183 PPCI_CMPLW = 0x7c000040, 184 PPCI_CMPWI = 0x2c000000, 185 PPCI_CMPLWI = 0x28000000, 186 187 PPCI_MULLW = 0x7c0001d6, 188 PPCI_MULLI = 0x1c000000, 189 PPCI_MULLWO = 0x7c0005d6, 190 191 PPCI_EXTSB = 0x7c000774, 192 PPCI_EXTSH = 0x7c000734, 193 194 PPCI_SLW = 0x7c000030, 195 PPCI_SRW = 0x7c000430, 196 PPCI_SRAW = 0x7c000630, 197 PPCI_SRAWI = 0x7c000670, 198 199 PPCI_RLWNM = 0x5c000000, 200 PPCI_RLWINM = 0x54000000, 201 PPCI_RLWIMI = 0x50000000, 202 203 PPCI_B = 0x48000000, 204 PPCI_BL = 0x48000001, 205 PPCI_BC = 0x40800000, 206 PPCI_BCL = 0x40800001, 207 PPCI_BCTR = 0x4e800420, 208 PPCI_BCTRL = 0x4e800421, 209 210 PPCI_CRANDC = 0x4c000102, 211 PPCI_CRXOR = 0x4c000182, 212 PPCI_CRAND = 0x4c000202, 213 PPCI_CREQV = 0x4c000242, 214 PPCI_CRORC = 0x4c000342, 215 PPCI_CROR = 0x4c000382, 216 217 PPCI_MFLR = 0x7c0802a6, 218 PPCI_MTCTR = 0x7c0903a6, 219 220 PPCI_MCRXR = 0x7c000400, 221 222 /* Load/store instructions. */ 223 PPCI_LWZ = 0x80000000, 224 PPCI_LBZ = 0x88000000, 225 PPCI_STW = 0x90000000, 226 PPCI_STB = 0x98000000, 227 PPCI_LHZ = 0xa0000000, 228 PPCI_LHA = 0xa8000000, 229 PPCI_STH = 0xb0000000, 230 231 PPCI_STWU = 0x94000000, 232 233 PPCI_LFS = 0xc0000000, 234 PPCI_LFD = 0xc8000000, 235 PPCI_STFS = 0xd0000000, 236 PPCI_STFD = 0xd8000000, 237 238 PPCI_LWZX = 0x7c00002e, 239 PPCI_LBZX = 0x7c0000ae, 240 PPCI_STWX = 0x7c00012e, 241 PPCI_STBX = 0x7c0001ae, 242 PPCI_LHZX = 0x7c00022e, 243 PPCI_LHAX = 0x7c0002ae, 244 PPCI_STHX = 0x7c00032e, 245 246 PPCI_LWBRX = 0x7c00042c, 247 PPCI_STWBRX = 0x7c00052c, 248 249 PPCI_LFSX = 0x7c00042e, 250 PPCI_LFDX = 0x7c0004ae, 251 PPCI_STFSX = 0x7c00052e, 252 PPCI_STFDX = 0x7c0005ae, 253 254 /* FP instructions. */ 255 PPCI_FMR = 0xfc000090, 256 PPCI_FNEG = 0xfc000050, 257 PPCI_FABS = 0xfc000210, 258 259 PPCI_FRSP = 0xfc000018, 260 PPCI_FCTIWZ = 0xfc00001e, 261 262 PPCI_FADD = 0xfc00002a, 263 PPCI_FSUB = 0xfc000028, 264 PPCI_FMUL = 0xfc000032, 265 PPCI_FDIV = 0xfc000024, 266 PPCI_FSQRT = 0xfc00002c, 267 268 PPCI_FMADD = 0xfc00003a, 269 PPCI_FMSUB = 0xfc000038, 270 PPCI_FNMSUB = 0xfc00003c, 271 272 PPCI_FCMPU = 0xfc000000, 273 PPCI_FSEL = 0xfc00002e, 274 } PPCIns; 275 276 typedef enum PPCCC { 277 CC_GE, CC_LE, CC_NE, CC_NS, CC_LT, CC_GT, CC_EQ, CC_SO 278 } PPCCC; 279 280 #endif