lj_target_arm64.h (2994B)
1 /* 2 ** Definitions for ARM64 CPUs. 3 ** Copyright (C) 2005-2016 Mike Pall. See Copyright Notice in luajit.h 4 */ 5 6 #ifndef _LJ_TARGET_ARM64_H 7 #define _LJ_TARGET_ARM64_H 8 9 /* -- Registers IDs ------------------------------------------------------- */ 10 11 #define GPRDEF(_) \ 12 _(X0) _(X1) _(X2) _(X3) _(X4) _(X5) _(X6) _(X7) \ 13 _(X8) _(X9) _(X10) _(X11) _(X12) _(X13) _(X14) _(X15) \ 14 _(X16) _(X17) _(X18) _(X19) _(X20) _(X21) _(X22) _(X23) \ 15 _(X24) _(X25) _(X26) _(X27) _(X28) _(FP) _(LR) _(SP) 16 #define FPRDEF(_) \ 17 _(D0) _(D1) _(D2) _(D3) _(D4) _(D5) _(D6) _(D7) \ 18 _(D8) _(D9) _(D10) _(D11) _(D12) _(D13) _(D14) _(D15) \ 19 _(D16) _(D17) _(D18) _(D19) _(D20) _(D21) _(D22) _(D23) \ 20 _(D24) _(D25) _(D26) _(D27) _(D28) _(D29) _(D30) _(D31) 21 #define VRIDDEF(_) 22 23 #define RIDENUM(name) RID_##name, 24 25 enum { 26 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */ 27 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */ 28 RID_MAX, 29 RID_TMP = RID_LR, 30 RID_ZERO = RID_SP, 31 32 /* Calling conventions. */ 33 RID_RET = RID_X0, 34 RID_FPRET = RID_D0, 35 36 /* These definitions must match with the *.dasc file(s): */ 37 RID_BASE = RID_X19, /* Interpreter BASE. */ 38 RID_LPC = RID_X21, /* Interpreter PC. */ 39 RID_GL = RID_X22, /* Interpreter GL. */ 40 RID_LREG = RID_X23, /* Interpreter L. */ 41 42 /* Register ranges [min, max) and number of registers. */ 43 RID_MIN_GPR = RID_X0, 44 RID_MAX_GPR = RID_SP+1, 45 RID_MIN_FPR = RID_MAX_GPR, 46 RID_MAX_FPR = RID_D31+1, 47 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR, 48 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR 49 }; 50 51 #define RID_NUM_KREF RID_NUM_GPR 52 #define RID_MIN_KREF RID_X0 53 54 /* -- Register sets ------------------------------------------------------- */ 55 56 /* Make use of all registers, except for x18, fp, lr and sp. */ 57 #define RSET_FIXED \ 58 (RID2RSET(RID_X18)|RID2RSET(RID_FP)|RID2RSET(RID_LR)|RID2RSET(RID_SP)) 59 #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED) 60 #define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR) 61 #define RSET_ALL (RSET_GPR|RSET_FPR) 62 #define RSET_INIT RSET_ALL 63 64 /* lr is an implicit scratch register. */ 65 #define RSET_SCRATCH_GPR (RSET_RANGE(RID_X0, RID_X17+1)) 66 #define RSET_SCRATCH_FPR \ 67 (RSET_RANGE(RID_D0, RID_D7+1)|RSET_RANGE(RID_D16, RID_D31+1)) 68 #define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR) 69 #define REGARG_FIRSTGPR RID_X0 70 #define REGARG_LASTGPR RID_X7 71 #define REGARG_NUMGPR 8 72 #define REGARG_FIRSTFPR RID_D0 73 #define REGARG_LASTFPR RID_D7 74 #define REGARG_NUMFPR 8 75 76 /* -- Instructions -------------------------------------------------------- */ 77 78 /* Instruction fields. */ 79 #define A64F_D(r) (r) 80 #define A64F_N(r) ((r) << 5) 81 #define A64F_A(r) ((r) << 10) 82 #define A64F_M(r) ((r) << 16) 83 #define A64F_U16(x) ((x) << 5) 84 #define A64F_S26(x) (x) 85 #define A64F_S19(x) ((x) << 5) 86 87 typedef enum A64Ins { 88 A64I_MOVZw = 0x52800000, 89 A64I_MOVZx = 0xd2800000, 90 A64I_LDRLw = 0x18000000, 91 A64I_LDRLx = 0x58000000, 92 A64I_NOP = 0xd503201f, 93 A64I_B = 0x14000000, 94 A64I_BR = 0xd61f0000, 95 } A64Ins; 96 97 #endif