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Charalampos Mitrodimas a1f44e0c59 tests/tcg/riscv64: Add test for MEPC bit masking ... Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an illegal instruction exception, copies STVEC to MEPC in the trap handler, and verifies that MEPC masks bits [1:0] correctly for IALIGN=32. Without the fix, MEPC retains the mode bits (returns non-zero/FAIL). With the fix, MEPC clears bits [1:0] (returns 0/PASS). Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-3-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 weeks ago
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Makefile.softmmu-target	tests/tcg/riscv64: Add test for MEPC bit masking	2 weeks ago
Makefile.target	tests: riscv64: Use 'zfa' instead of 'Zfa'	1 year ago
issue1060.S	target/riscv: Set env->bins in gen_exception_illegal	3 years ago
noexec.c	target/riscv: Make translator stop before the end of a page	3 years ago
semicall.h	tests/tcg: update licenses to GPLv2 as intended	1 year ago
semihost.ld	target/riscv: Set env->bins in gen_exception_illegal	3 years ago
test-aes.c	tests/multiarch: Add test-aes	2 years ago
test-div.c	…
test-fcvtmod.c	riscv: Add support for the Zfa extension	2 years ago
test-mepc-masking.S	tests/tcg/riscv64: Add test for MEPC bit masking	2 weeks ago
test-noc.S	target/riscv: Set pc_succ_insn for !rvc illegal insn	3 years ago