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470 lines
12 KiB
C
470 lines
12 KiB
C
/*
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* QEMU ICH9 TCO emulation tests
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*
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* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci.h"
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#include "libqos/pci-pc.h"
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#include "qapi/qmp/qdict.h"
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#include "hw/pci/pci_regs.h"
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#include "hw/southbridge/ich9.h"
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#include "hw/acpi/ich9.h"
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#include "hw/acpi/ich9_tco.h"
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#define RCBA_BASE_ADDR 0xfed1c000
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#define PM_IO_BASE_ADDR 0xb000
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enum {
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TCO_RLD_DEFAULT = 0x0000,
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TCO_DAT_IN_DEFAULT = 0x00,
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TCO_DAT_OUT_DEFAULT = 0x00,
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TCO1_STS_DEFAULT = 0x0000,
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TCO2_STS_DEFAULT = 0x0000,
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TCO1_CNT_DEFAULT = 0x0000,
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TCO2_CNT_DEFAULT = 0x0008,
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TCO_MESSAGE1_DEFAULT = 0x00,
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TCO_MESSAGE2_DEFAULT = 0x00,
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TCO_WDCNT_DEFAULT = 0x00,
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TCO_TMR_DEFAULT = 0x0004,
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SW_IRQ_GEN_DEFAULT = 0x03,
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};
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#define TCO_SECS_TO_TICKS(secs) (((secs) * 10) / 6)
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#define TCO_TICKS_TO_SECS(ticks) (((ticks) * 6) / 10)
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typedef struct {
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const char *args;
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bool noreboot;
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QPCIDevice *dev;
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QPCIBar tco_io_bar;
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QPCIBus *bus;
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QTestState *qts;
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} TestData;
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static void test_end(TestData *d)
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{
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g_free(d->dev);
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qpci_free_pc(d->bus);
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qtest_quit(d->qts);
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}
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static void test_init(TestData *d)
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{
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QTestState *qs;
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qs = qtest_initf("-machine q35 %s %s",
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d->noreboot ? "-global ICH9-LPC.noreboot=true" : "",
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!d->args ? "" : d->args);
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qtest_irq_intercept_in(qs, "ioapic");
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d->bus = qpci_new_pc(qs, NULL);
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d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
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g_assert(d->dev != NULL);
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qpci_device_enable(d->dev);
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/* set ACPI PM I/O space base address */
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qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
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/* enable ACPI I/O */
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qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
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/* set Root Complex BAR */
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qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
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d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
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d->qts = qs;
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}
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static void stop_tco(const TestData *d)
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{
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uint32_t val;
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val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
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val |= TCO_TMR_HLT;
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qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
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}
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static void start_tco(const TestData *d)
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{
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uint32_t val;
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val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
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val &= ~TCO_TMR_HLT;
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qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
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}
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static void load_tco(const TestData *d)
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{
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qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
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}
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static void set_tco_timeout(const TestData *d, uint16_t ticks)
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{
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qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
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}
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static void clear_tco_status(const TestData *d)
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{
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qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
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qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
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qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
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}
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static void reset_on_second_timeout(const TestData *td, bool enable)
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{
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uint32_t val;
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val = qtest_readl(td->qts, RCBA_BASE_ADDR + ICH9_CC_GCS);
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if (enable) {
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val &= ~ICH9_CC_GCS_NO_REBOOT;
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} else {
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val |= ICH9_CC_GCS_NO_REBOOT;
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}
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qtest_writel(td->qts, RCBA_BASE_ADDR + ICH9_CC_GCS, val);
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}
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static void test_tco_defaults(void)
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{
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TestData d;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
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TCO_RLD_DEFAULT);
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/* TCO_DAT_IN & TCO_DAT_OUT */
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
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(TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
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/* TCO1_STS & TCO2_STS */
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g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
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(TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
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/* TCO1_CNT & TCO2_CNT */
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g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
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(TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
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/* TCO_MESSAGE1 & TCO_MESSAGE2 */
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
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(TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
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g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
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TCO_WDCNT_DEFAULT);
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g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
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SW_IRQ_GEN_DEFAULT);
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
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TCO_TMR_DEFAULT);
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test_end(&d);
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}
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static void test_tco_timeout(void)
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{
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TestData d;
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const uint16_t ticks = TCO_SECS_TO_TICKS(4);
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uint32_t val;
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int ret;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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stop_tco(&d);
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clear_tco_status(&d);
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reset_on_second_timeout(&d, false);
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set_tco_timeout(&d, ticks);
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load_tco(&d);
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start_tco(&d);
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qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
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/* test first timeout */
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
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ret = val & TCO_TIMEOUT ? 1 : 0;
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g_assert(ret == 1);
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/* test clearing timeout bit */
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val |= TCO_TIMEOUT;
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qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
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ret = val & TCO_TIMEOUT ? 1 : 0;
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g_assert(ret == 0);
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/* test second timeout */
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qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
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ret = val & TCO_TIMEOUT ? 1 : 0;
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g_assert(ret == 1);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
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ret = val & TCO_SECOND_TO_STS ? 1 : 0;
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g_assert(ret == 1);
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stop_tco(&d);
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test_end(&d);
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}
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static void test_tco_max_timeout(void)
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{
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TestData d;
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const uint16_t ticks = 0xffff;
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uint32_t val;
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int ret;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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stop_tco(&d);
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clear_tco_status(&d);
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reset_on_second_timeout(&d, false);
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set_tco_timeout(&d, ticks);
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load_tco(&d);
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start_tco(&d);
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qtest_clock_step(d.qts, ((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
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g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
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ret = val & TCO_TIMEOUT ? 1 : 0;
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g_assert(ret == 0);
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qtest_clock_step(d.qts, TCO_TICK_NSEC);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
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ret = val & TCO_TIMEOUT ? 1 : 0;
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g_assert(ret == 1);
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stop_tco(&d);
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test_end(&d);
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}
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static QDict *get_watchdog_action(const TestData *td)
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{
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QDict *ev = qtest_qmp_eventwait_ref(td->qts, "WATCHDOG");
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QDict *data;
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data = qdict_get_qdict(ev, "data");
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qobject_ref(data);
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qobject_unref(ev);
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return data;
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}
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static void test_tco_second_timeout_pause(void)
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{
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TestData td;
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const uint16_t ticks = TCO_SECS_TO_TICKS(32);
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QDict *ad;
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td.args = "-watchdog-action pause";
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td.noreboot = false;
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test_init(&td);
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stop_tco(&td);
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clear_tco_status(&td);
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reset_on_second_timeout(&td, true);
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set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
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load_tco(&td);
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start_tco(&td);
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qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
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ad = get_watchdog_action(&td);
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g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
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qobject_unref(ad);
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stop_tco(&td);
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test_end(&td);
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}
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static void test_tco_second_timeout_reset(void)
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{
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TestData td;
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const uint16_t ticks = TCO_SECS_TO_TICKS(16);
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QDict *ad;
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td.args = "-watchdog-action reset";
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td.noreboot = false;
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test_init(&td);
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stop_tco(&td);
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clear_tco_status(&td);
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reset_on_second_timeout(&td, true);
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set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
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load_tco(&td);
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start_tco(&td);
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qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
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ad = get_watchdog_action(&td);
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g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
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qobject_unref(ad);
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stop_tco(&td);
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test_end(&td);
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}
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static void test_tco_second_timeout_shutdown(void)
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{
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TestData td;
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const uint16_t ticks = TCO_SECS_TO_TICKS(128);
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QDict *ad;
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td.args = "-watchdog-action shutdown";
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td.noreboot = false;
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test_init(&td);
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stop_tco(&td);
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clear_tco_status(&td);
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reset_on_second_timeout(&td, true);
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set_tco_timeout(&td, ticks);
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load_tco(&td);
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start_tco(&td);
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qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
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ad = get_watchdog_action(&td);
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g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
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qobject_unref(ad);
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stop_tco(&td);
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test_end(&td);
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}
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static void test_tco_second_timeout_none(void)
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{
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TestData td;
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const uint16_t ticks = TCO_SECS_TO_TICKS(256);
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QDict *ad;
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td.args = "-watchdog-action none";
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td.noreboot = false;
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test_init(&td);
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stop_tco(&td);
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clear_tco_status(&td);
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reset_on_second_timeout(&td, true);
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set_tco_timeout(&td, ticks);
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load_tco(&td);
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start_tco(&td);
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qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
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ad = get_watchdog_action(&td);
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g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
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qobject_unref(ad);
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stop_tco(&td);
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test_end(&td);
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}
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static void test_tco_ticks_counter(void)
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{
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TestData d;
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uint16_t ticks = TCO_SECS_TO_TICKS(8);
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uint16_t rld;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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stop_tco(&d);
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clear_tco_status(&d);
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reset_on_second_timeout(&d, false);
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set_tco_timeout(&d, ticks);
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load_tco(&d);
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start_tco(&d);
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do {
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rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
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g_assert_cmpint(rld, ==, ticks);
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qtest_clock_step(d.qts, TCO_TICK_NSEC);
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ticks--;
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} while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));
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stop_tco(&d);
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test_end(&d);
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}
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static void test_tco1_control_bits(void)
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{
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TestData d;
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uint16_t val;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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val = TCO_LOCK;
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qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
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val &= ~TCO_LOCK;
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qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
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TCO_LOCK);
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test_end(&d);
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}
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static void test_tco1_status_bits(void)
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{
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TestData d;
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uint16_t ticks = 8;
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uint16_t val;
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int ret;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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stop_tco(&d);
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clear_tco_status(&d);
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reset_on_second_timeout(&d, false);
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set_tco_timeout(&d, ticks);
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load_tco(&d);
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start_tco(&d);
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qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
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qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
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qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
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ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
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g_assert(ret == 1);
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qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
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test_end(&d);
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}
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static void test_tco2_status_bits(void)
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{
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TestData d;
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uint16_t ticks = 8;
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uint16_t val;
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int ret;
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d.args = NULL;
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d.noreboot = true;
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test_init(&d);
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stop_tco(&d);
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clear_tco_status(&d);
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reset_on_second_timeout(&d, true);
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set_tco_timeout(&d, ticks);
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load_tco(&d);
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start_tco(&d);
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qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC * 2);
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val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
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ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
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g_assert(ret == 1);
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qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
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g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
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test_end(&d);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("tco/defaults", test_tco_defaults);
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qtest_add_func("tco/timeout/no_action", test_tco_timeout);
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qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
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qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
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qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
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qtest_add_func("tco/second_timeout/shutdown",
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test_tco_second_timeout_shutdown);
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qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
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qtest_add_func("tco/counter", test_tco_ticks_counter);
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qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
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qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
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qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
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return g_test_run();
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}
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