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589 lines
20 KiB
C
589 lines
20 KiB
C
/*
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* QTest testcase for STM32L4x5_GPIO
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*
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* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#include "stm32l4x5.h"
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#define GPIO_BASE_ADDR 0x48000000
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#define GPIO_SIZE 0x400
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#define NUM_GPIOS 8
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#define NUM_GPIO_PINS 16
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#define GPIO_A 0x48000000
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#define GPIO_B 0x48000400
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#define GPIO_C 0x48000800
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#define GPIO_D 0x48000C00
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#define GPIO_E 0x48001000
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#define GPIO_F 0x48001400
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#define GPIO_G 0x48001800
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#define GPIO_H 0x48001C00
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#define MODER 0x00
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#define OTYPER 0x04
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#define PUPDR 0x0C
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#define IDR 0x10
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#define ODR 0x14
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#define BSRR 0x18
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#define BRR 0x28
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#define MODER_INPUT 0
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#define MODER_OUTPUT 1
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#define PUPDR_NONE 0
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#define PUPDR_PULLUP 1
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#define PUPDR_PULLDOWN 2
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#define OTYPER_PUSH_PULL 0
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#define OTYPER_OPEN_DRAIN 1
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/* SoC forwards GPIOs to SysCfg */
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#define SYSCFG "/machine/soc"
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const uint32_t moder_reset[NUM_GPIOS] = {
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0xABFFFFFF,
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0xFFFFFEBF,
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0xFFFFFFFF,
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0xFFFFFFFF,
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0xFFFFFFFF,
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0xFFFFFFFF,
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0xFFFFFFFF,
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0x0000000F
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};
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const uint32_t pupdr_reset[NUM_GPIOS] = {
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0x64000000,
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0x00000100,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000
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};
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const uint32_t idr_reset[NUM_GPIOS] = {
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0x0000A000,
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0x00000010,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000
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};
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#define PIN_MASK 0xF
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#define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
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static inline void *test_data(uint32_t gpio_addr, uint8_t pin)
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{
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return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK));
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}
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#define test_gpio_addr(data) ((uintptr_t)(data) & GPIO_ADDR_MASK)
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#define test_pin(data) ((uintptr_t)(data) & PIN_MASK)
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static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
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{
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return readl(gpio + offset);
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}
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static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
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{
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writel(gpio + offset, value);
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}
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static void gpio_set_bit(unsigned int gpio, unsigned int reg,
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unsigned int pin, uint32_t value)
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{
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uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
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gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
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}
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static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
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unsigned int pin, uint32_t value)
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{
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uint32_t offset = 2 * pin;
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uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
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gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
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}
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static unsigned int get_gpio_id(uint32_t gpio_addr)
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{
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return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
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}
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static void gpio_set_irq(unsigned int gpio, int num, int level)
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{
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g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
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get_gpio_id(gpio) + 'a');
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qtest_set_irq_in(global_qtest, name, NULL, num, level);
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}
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static void disconnect_all_pins(unsigned int gpio)
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{
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g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
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get_gpio_id(gpio) + 'a');
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QDict *r;
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r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
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"{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
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path, 0xFFFF);
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g_assert_false(qdict_haskey(r, "error"));
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qobject_unref(r);
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}
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static uint32_t get_disconnected_pins(unsigned int gpio)
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{
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g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
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get_gpio_id(gpio) + 'a');
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uint32_t disconnected_pins = 0;
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QDict *r;
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r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
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" { 'path': %s, 'property': 'disconnected-pins'} }", path);
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g_assert_false(qdict_haskey(r, "error"));
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disconnected_pins = qdict_get_int(r, "return");
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qobject_unref(r);
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return disconnected_pins;
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}
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static uint32_t reset(uint32_t gpio, unsigned int offset)
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{
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switch (offset) {
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case MODER:
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return moder_reset[get_gpio_id(gpio)];
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case PUPDR:
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return pupdr_reset[get_gpio_id(gpio)];
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case IDR:
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return idr_reset[get_gpio_id(gpio)];
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}
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return 0x0;
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}
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static void system_reset(void)
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{
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QDict *r;
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r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
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g_assert_false(qdict_haskey(r, "error"));
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qobject_unref(r);
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}
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static void test_idr_reset_value(void)
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{
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/*
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* Checks that the values in MODER, OTYPER, PUPDR and ODR
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* after reset are correct, and that the value in IDR is
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* coherent.
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* Since AF and analog modes aren't implemented, IDR reset
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* values aren't the same as with a real board.
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*
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* Register IDR contains the actual values of all GPIO pins.
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* Its value depends on the pins' configuration
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* (intput/output/analog : register MODER, push-pull/open-drain :
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* register OTYPER, pull-up/pull-down/none : register PUPDR)
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* and on the values stored in register ODR
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* (in case the pin is in output mode).
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*/
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gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
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gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
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gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
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gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
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gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
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gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
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gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
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gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
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gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
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gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
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gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
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gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
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gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
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gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
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gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
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gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
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system_reset();
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uint32_t moder = gpio_readl(GPIO_A, MODER);
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uint32_t odr = gpio_readl(GPIO_A, ODR);
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uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
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uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
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uint32_t idr = gpio_readl(GPIO_A, IDR);
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/* 15: AF, 14: AF, 13: AF, 12: Analog ... */
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/* here AF is the same as Analog and Input mode */
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g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
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g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
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g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
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/* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
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g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
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/* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
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g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
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moder = gpio_readl(GPIO_B, MODER);
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odr = gpio_readl(GPIO_B, ODR);
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otyper = gpio_readl(GPIO_B, OTYPER);
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pupdr = gpio_readl(GPIO_B, PUPDR);
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idr = gpio_readl(GPIO_B, IDR);
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/* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
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/* here AF is the same as Analog and Input mode */
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g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
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g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
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g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
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/* ... 5: neither, 4: pull-up, 3: neither ... */
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g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
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/* ... 5 : reset value, 4 : 1, 3 : reset value ... */
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g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
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moder = gpio_readl(GPIO_C, MODER);
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odr = gpio_readl(GPIO_C, ODR);
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otyper = gpio_readl(GPIO_C, OTYPER);
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pupdr = gpio_readl(GPIO_C, PUPDR);
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idr = gpio_readl(GPIO_C, IDR);
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/* Analog, same as Input mode*/
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g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
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g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
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g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
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/* no pull-up or pull-down */
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g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
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/* reset value */
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g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
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moder = gpio_readl(GPIO_H, MODER);
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odr = gpio_readl(GPIO_H, ODR);
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otyper = gpio_readl(GPIO_H, OTYPER);
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pupdr = gpio_readl(GPIO_H, PUPDR);
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idr = gpio_readl(GPIO_H, IDR);
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/* Analog, same as Input mode */
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g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
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g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
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g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
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/* no pull-up or pull-down */
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g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
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/* reset value */
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g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
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}
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static void test_gpio_output_mode(const void *data)
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{
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/*
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* Checks that setting a bit in ODR sets the corresponding
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* GPIO line high : it should set the right bit in IDR
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* and send an irq to syscfg.
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* Additionally, it checks that values written to ODR
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* when not in output mode are stored and not discarded.
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*/
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, SYSCFG);
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/* Set a bit in ODR and check nothing happens */
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gpio_set_bit(gpio, ODR, pin, 1);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
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g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Configure the relevant line as output and check the pin is high */
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gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
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g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Reset the bit in ODR and check the pin is low */
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gpio_set_bit(gpio, ODR, pin, 0);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
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g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Clean the test */
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gpio_writel(gpio, ODR, reset(gpio, ODR));
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gpio_writel(gpio, MODER, reset(gpio, MODER));
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
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g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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}
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static void test_gpio_input_mode(const void *data)
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{
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/*
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* Test that setting a line high/low externally sets the
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* corresponding GPIO line high/low : it should set the
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* right bit in IDR and send an irq to syscfg.
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*/
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, SYSCFG);
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/* Configure a line as input, raise it, and check that the pin is high */
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gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
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gpio_set_irq(gpio, pin, 1);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
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g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Lower the line and check that the pin is low */
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gpio_set_irq(gpio, pin, 0);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
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g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Clean the test */
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gpio_writel(gpio, MODER, reset(gpio, MODER));
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disconnect_all_pins(gpio);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
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}
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static void test_pull_up_pull_down(const void *data)
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{
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/*
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* Test that a floating pin with pull-up sets the pin
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* high and vice-versa.
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*/
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, SYSCFG);
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/* Configure a line as input with pull-up, check the line is set high */
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gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
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gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
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g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Configure the line with pull-down, check the line is low */
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gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
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g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
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/* Clean the test */
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gpio_writel(gpio, MODER, reset(gpio, MODER));
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gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
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}
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static void test_push_pull(const void *data)
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{
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/*
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* Test that configuring a line in push-pull output mode
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* disconnects the pin, that the pin can't be set or reset
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* externally afterwards.
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*/
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
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qtest_irq_intercept_in(global_qtest, SYSCFG);
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/* Setting a line high externally, configuring it in push-pull output */
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/* And checking the pin was disconnected */
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gpio_set_irq(gpio, pin, 1);
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gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
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g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
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/* Setting a line low externally, configuring it in push-pull output */
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/* And checking the pin was disconnected */
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gpio_set_irq(gpio2, pin, 0);
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gpio_set_bit(gpio2, ODR, pin, 1);
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gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
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g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
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g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
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/* Trying to set a push-pull output pin, checking it doesn't work */
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gpio_set_irq(gpio, pin, 1);
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g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
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g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
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/* Trying to reset a push-pull output pin, checking it doesn't work */
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gpio_set_irq(gpio2, pin, 0);
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g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
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g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
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/* Clean the test */
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gpio_writel(gpio, MODER, reset(gpio, MODER));
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gpio_writel(gpio2, ODR, reset(gpio2, ODR));
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gpio_writel(gpio2, MODER, reset(gpio2, MODER));
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}
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static void test_open_drain(const void *data)
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{
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/*
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* Test that configuring a line in open-drain output mode
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* disconnects a pin set high externally and that the pin
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* can't be set high externally while configured in open-drain.
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*
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* However a pin set low externally shouldn't be disconnected,
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* and it can be set low externally when in open-drain mode.
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|
*/
|
|
unsigned int pin = test_pin(data);
|
|
uint32_t gpio = test_gpio_addr(data);
|
|
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
|
|
|
|
qtest_irq_intercept_in(global_qtest, SYSCFG);
|
|
|
|
/* Setting a line high externally, configuring it in open-drain output */
|
|
/* And checking the pin was disconnected */
|
|
gpio_set_irq(gpio, pin, 1);
|
|
gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
|
|
gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
|
|
g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
|
|
g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
|
|
|
|
/* Setting a line low externally, configuring it in open-drain output */
|
|
/* And checking the pin wasn't disconnected */
|
|
gpio_set_irq(gpio2, pin, 0);
|
|
gpio_set_bit(gpio2, ODR, pin, 1);
|
|
gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
|
|
gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
|
|
g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
|
|
g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
|
|
reset(gpio2, IDR) & ~(1 << pin));
|
|
|
|
/* Trying to set a open-drain output pin, checking it doesn't work */
|
|
gpio_set_irq(gpio, pin, 1);
|
|
g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
|
|
g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
|
|
|
|
/* Trying to reset a open-drain output pin, checking it works */
|
|
gpio_set_bit(gpio, ODR, pin, 1);
|
|
gpio_set_irq(gpio, pin, 0);
|
|
g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
|
|
g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
|
|
reset(gpio2, IDR) & ~(1 << pin));
|
|
|
|
/* Clean the test */
|
|
disconnect_all_pins(gpio2);
|
|
gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
|
|
gpio_writel(gpio2, ODR, reset(gpio2, ODR));
|
|
gpio_writel(gpio2, MODER, reset(gpio2, MODER));
|
|
g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
|
|
disconnect_all_pins(gpio);
|
|
gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
|
|
gpio_writel(gpio, ODR, reset(gpio, ODR));
|
|
gpio_writel(gpio, MODER, reset(gpio, MODER));
|
|
g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
|
|
}
|
|
|
|
static void test_bsrr_brr(const void *data)
|
|
{
|
|
/*
|
|
* Test that writing a '1' in BSS and BSRR
|
|
* has the desired effect on ODR.
|
|
* In BSRR, BSx has priority over BRx.
|
|
*/
|
|
unsigned int pin = test_pin(data);
|
|
uint32_t gpio = test_gpio_addr(data);
|
|
|
|
gpio_writel(gpio, BSRR, (1 << pin));
|
|
g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
|
|
|
|
gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
|
|
g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
|
|
|
|
gpio_writel(gpio, BSRR, (1 << pin));
|
|
g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
|
|
|
|
gpio_writel(gpio, BRR, (1 << pin));
|
|
g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
|
|
|
|
/* BSx should have priority over BRx */
|
|
gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
|
|
g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
|
|
|
|
gpio_writel(gpio, BRR, (1 << pin));
|
|
g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
|
|
|
|
gpio_writel(gpio, ODR, reset(gpio, ODR));
|
|
}
|
|
|
|
static void test_clock_enable(void)
|
|
{
|
|
/*
|
|
* For each GPIO, enable its clock in RCC
|
|
* and check that its clock period changes to SYSCLK_PERIOD
|
|
*/
|
|
unsigned int gpio_id;
|
|
|
|
for (uint32_t gpio = GPIO_A; gpio <= GPIO_H; gpio += GPIO_B - GPIO_A) {
|
|
gpio_id = get_gpio_id(gpio);
|
|
g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c/clk",
|
|
gpio_id + 'a');
|
|
g_assert_cmpuint(get_clock_period(global_qtest, path), ==, 0);
|
|
/* Enable the gpio clock */
|
|
writel(RCC_AHB2ENR, readl(RCC_AHB2ENR) | (0x1 << gpio_id));
|
|
g_assert_cmpuint(get_clock_period(global_qtest, path), ==,
|
|
SYSCLK_PERIOD);
|
|
}
|
|
}
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
int ret;
|
|
|
|
g_test_init(&argc, &argv, NULL);
|
|
g_test_set_nonfatal_assertions();
|
|
qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
|
|
test_idr_reset_value);
|
|
/*
|
|
* The inputs for the tests (gpio and pin) can be changed,
|
|
* but the tests don't work for pins that are high at reset
|
|
* (GPIOA15, GPIO13 and GPIOB5).
|
|
* Specifically, rising the pin then checking `get_irq()`
|
|
* is problematic since the pin was already high.
|
|
*/
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
|
|
test_data(GPIO_C, 5),
|
|
test_gpio_output_mode);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
|
|
test_data(GPIO_H, 3),
|
|
test_gpio_output_mode);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
|
|
test_data(GPIO_D, 6),
|
|
test_gpio_input_mode);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
|
|
test_data(GPIO_C, 10),
|
|
test_gpio_input_mode);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
|
|
test_data(GPIO_B, 5),
|
|
test_pull_up_pull_down);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
|
|
test_data(GPIO_F, 1),
|
|
test_pull_up_pull_down);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
|
|
test_data(GPIO_G, 6),
|
|
test_push_pull);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
|
|
test_data(GPIO_H, 3),
|
|
test_push_pull);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
|
|
test_data(GPIO_C, 4),
|
|
test_open_drain);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
|
|
test_data(GPIO_E, 11),
|
|
test_open_drain);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
|
|
test_data(GPIO_A, 12),
|
|
test_bsrr_brr);
|
|
qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
|
|
test_data(GPIO_D, 0),
|
|
test_bsrr_brr);
|
|
qtest_add_func("stm32l4x5/gpio/test_clock_enable",
|
|
test_clock_enable);
|
|
|
|
qtest_start("-machine b-l475e-iot01a");
|
|
ret = g_test_run();
|
|
qtest_end();
|
|
|
|
return ret;
|
|
}
|