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111 lines
4.0 KiB
C
111 lines
4.0 KiB
C
/*
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* QTest testcase for PowerNV 10 Seeprom Communications
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <unistd.h>
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "qemu/bswap.h"
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#include "hw/ssi/pnv_spi_regs.h"
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#include "pnv-xscom.h"
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#define FLASH_SIZE (512 * 1024)
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#define SPIC2_XSCOM_BASE 0xc0040
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/* To transmit READ opcode and address */
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#define READ_OP_TDR_DATA 0x0300010000000000
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/*
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* N1 shift - tx 4 bytes (transmit opcode and address)
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* N2 shift - tx and rx 8 bytes.
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*/
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#define READ_OP_COUNTER_CONFIG 0x2040000000002b00
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/* SEQ_OP_SELECT_RESPONDER - N1 Shift - N2 Shift * 5 - SEQ_OP_STOP */
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#define READ_OP_SEQUENCER 0x1130404040404010
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/* To transmit WREN(Set Write Enable Latch in status0 register) opcode */
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#define WRITE_OP_WREN 0x0600000000000000
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/* To transmit WRITE opcode, address and data */
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#define WRITE_OP_TDR_DATA 0x0300010012345678
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/* N1 shift - tx 8 bytes (transmit opcode, address and data) */
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#define WRITE_OP_COUNTER_CONFIG 0x4000000000002000
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/* SEQ_OP_SELECT_RESPONDER - N1 Shift - SEQ_OP_STOP */
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#define WRITE_OP_SEQUENCER 0x1130100000000000
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static void pnv_spi_xscom_write(QTestState *qts, const PnvChip *chip,
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uint32_t reg, uint64_t val)
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{
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uint32_t pcba = SPIC2_XSCOM_BASE + reg;
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qtest_writeq(qts, pnv_xscom_addr(chip, pcba), val);
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}
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static uint64_t pnv_spi_xscom_read(QTestState *qts, const PnvChip *chip,
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uint32_t reg)
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{
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uint32_t pcba = SPIC2_XSCOM_BASE + reg;
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return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
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}
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static void spi_seeprom_transaction(QTestState *qts, const PnvChip *chip)
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{
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/* SPI transactions to SEEPROM to read from SEEPROM image */
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pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, READ_OP_COUNTER_CONFIG);
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pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, READ_OP_SEQUENCER);
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pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, READ_OP_TDR_DATA);
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pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, 0);
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/* Read 5*8 bytes from SEEPROM at 0x100 */
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uint64_t rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
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g_test_message("RDR READ = 0x%" PRIx64, rdr_val);
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rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
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rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
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rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
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rdr_val = pnv_spi_xscom_read(qts, chip, SPI_RCV_DATA_REG);
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g_test_message("RDR READ = 0x%" PRIx64, rdr_val);
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/* SPI transactions to SEEPROM to write to SEEPROM image */
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pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, WRITE_OP_COUNTER_CONFIG);
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/* Set Write Enable Latch bit of status0 register */
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pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, WRITE_OP_SEQUENCER);
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pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, WRITE_OP_WREN);
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/* write 8 bytes to SEEPROM at 0x100 */
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pnv_spi_xscom_write(qts, chip, SPI_SEQ_OP_REG, WRITE_OP_SEQUENCER);
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pnv_spi_xscom_write(qts, chip, SPI_XMIT_DATA_REG, WRITE_OP_TDR_DATA);
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}
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static void test_spi_seeprom(const void *data)
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{
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const PnvChip *chip = data;
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QTestState *qts = NULL;
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g_autofree char *tmp_path = NULL;
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int ret;
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int fd;
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/* Create a temporary raw image */
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fd = g_file_open_tmp("qtest-seeprom-XXXXXX", &tmp_path, NULL);
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g_assert(fd >= 0);
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ret = ftruncate(fd, FLASH_SIZE);
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g_assert(ret == 0);
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close(fd);
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qts = qtest_initf("-machine powernv10 -smp 2,cores=2,"
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"threads=1 -accel tcg,thread=single -nographic "
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"-blockdev node-name=pib_spic2,driver=file,"
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"filename=%s -device 25csm04,bus=pnv-spi-bus.2,cs=0,"
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"drive=pib_spic2", tmp_path);
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spi_seeprom_transaction(qts, chip);
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qtest_quit(qts);
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unlink(tmp_path);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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char *tname = g_strdup_printf("pnv-xscom/spi-seeprom/%s",
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pnv_chips[3].cpu_model);
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qtest_add_data_func(tname, &pnv_chips[3], test_spi_seeprom);
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g_free(tname);
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return g_test_run();
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}
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