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65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/*
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* QTest testcase for intel-iommu
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*
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* Copyright (c) 2024 Intel, Inc.
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*
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* Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "hw/i386/intel_iommu_internal.h"
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#define CAP_STAGE_1_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | \
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VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS)
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#define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \
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VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FLTS)
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static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)
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{
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return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
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}
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static void test_intel_iommu_stage_1(void)
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{
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uint8_t init_csr[DMAR_REG_SIZE]; /* register values */
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uint8_t post_reset_csr[DMAR_REG_SIZE]; /* register values */
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uint64_t cap, ecap, tmp;
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QTestState *s;
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s = qtest_init("-M q35 -device intel-iommu,x-scalable-mode=on,x-flts=on");
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cap = vtd_reg_readq(s, DMAR_CAP_REG);
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g_assert((cap & CAP_STAGE_1_FIXED1) == CAP_STAGE_1_FIXED1);
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tmp = cap & VTD_CAP_SAGAW_MASK;
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g_assert(tmp == (VTD_CAP_SAGAW_39bit | VTD_CAP_SAGAW_48bit));
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tmp = VTD_MGAW_FROM_CAP(cap);
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g_assert(tmp == VTD_HOST_AW_48BIT - 1);
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ecap = vtd_reg_readq(s, DMAR_ECAP_REG);
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g_assert((ecap & ECAP_STAGE_1_FIXED1) == ECAP_STAGE_1_FIXED1);
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qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, init_csr, DMAR_REG_SIZE);
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qobject_unref(qtest_qmp(s, "{ 'execute': 'system_reset' }"));
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qtest_qmp_eventwait(s, "RESET");
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qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, post_reset_csr, DMAR_REG_SIZE);
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/* Ensure registers are consistent after hard reset */
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g_assert(!memcmp(init_csr, post_reset_csr, DMAR_REG_SIZE));
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qtest_quit(s);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/q35/intel-iommu/stage-1", test_intel_iommu_stage_1);
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return g_test_run();
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}
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