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149 lines
4.2 KiB
C
149 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "loader.h"
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#include "elf.h"
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#include "target_elf.h"
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const char *get_elf_cpu_model(uint32_t eflags)
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{
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#ifdef TARGET_MIPS64
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switch (eflags & EF_MIPS_MACH) {
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case EF_MIPS_MACH_OCTEON:
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case EF_MIPS_MACH_OCTEON2:
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case EF_MIPS_MACH_OCTEON3:
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return "Octeon68XX";
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case EF_MIPS_MACH_LS2E:
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return "Loongson-2E";
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case EF_MIPS_MACH_LS2F:
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return "Loongson-2F";
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case EF_MIPS_MACH_LS3A:
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return "Loongson-3A1000";
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default:
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break;
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}
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switch (eflags & EF_MIPS_ARCH) {
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case EF_MIPS_ARCH_64R6:
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return "I6400";
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case EF_MIPS_ARCH_64R2:
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return "MIPS64R2-generic";
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default:
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break;
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}
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return "5KEf";
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#else
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if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {
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return "mips32r6-generic";
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}
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if ((eflags & EF_MIPS_ARCH_ASE) == EF_MIPS_ARCH_ASE_MICROMIPS) {
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return "M14Kc";
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}
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if ((eflags & EF_MIPS_ARCH_ASE) == EF_MIPS_ARCH_ASE_M16) {
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return "74Kf";
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}
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if (eflags & EF_MIPS_NAN2008) {
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return "P5600";
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}
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return "24Kf";
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#endif
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}
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/* See arch/mips/include/uapi/asm/hwcap.h. */
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enum {
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HWCAP_MIPS_R6 = (1 << 0),
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HWCAP_MIPS_MSA = (1 << 1),
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HWCAP_MIPS_CRC32 = (1 << 2),
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HWCAP_MIPS_MIPS16 = (1 << 3),
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HWCAP_MIPS_MDMX = (1 << 4),
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HWCAP_MIPS_MIPS3D = (1 << 5),
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HWCAP_MIPS_SMARTMIPS = (1 << 6),
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HWCAP_MIPS_DSP = (1 << 7),
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HWCAP_MIPS_DSP2 = (1 << 8),
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HWCAP_MIPS_DSP3 = (1 << 9),
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HWCAP_MIPS_MIPS16E2 = (1 << 10),
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HWCAP_LOONGSON_MMI = (1 << 11),
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HWCAP_LOONGSON_EXT = (1 << 12),
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HWCAP_LOONGSON_EXT2 = (1 << 13),
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HWCAP_LOONGSON_CPUCFG = (1 << 14),
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};
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#define GET_FEATURE_INSN(_flag, _hwcap) \
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do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0)
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#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
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do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
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#define GET_FEATURE_REG_EQU(_reg, _start, _length, _val, _hwcap) \
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do { \
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if (extract32(cpu->env._reg, (_start), (_length)) == (_val)) { \
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hwcaps |= _hwcap; \
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} \
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} while (0)
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abi_ulong get_elf_hwcap(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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abi_ulong hwcaps = 0;
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GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, CP0C0_AR_LENGTH,
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2, HWCAP_MIPS_R6);
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GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
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GET_FEATURE_INSN(ASE_LMMI, HWCAP_LOONGSON_MMI);
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GET_FEATURE_INSN(ASE_LEXT, HWCAP_LOONGSON_EXT);
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return hwcaps;
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}
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#undef GET_FEATURE_REG_EQU
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#undef GET_FEATURE_REG_SET
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#undef GET_FEATURE_INSN
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#define MATCH_PLATFORM_INSN(_flags, _base_platform) \
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do { if ((cpu->env.insn_flags & (_flags)) == _flags) \
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{ return _base_platform; } } while (0)
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const char *get_elf_base_platform(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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/* 64 bit ISAs goes first */
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MATCH_PLATFORM_INSN(CPU_MIPS64R6, "mips64r6");
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MATCH_PLATFORM_INSN(CPU_MIPS64R5, "mips64r5");
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MATCH_PLATFORM_INSN(CPU_MIPS64R2, "mips64r2");
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MATCH_PLATFORM_INSN(CPU_MIPS64R1, "mips64");
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MATCH_PLATFORM_INSN(CPU_MIPS5, "mips5");
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MATCH_PLATFORM_INSN(CPU_MIPS4, "mips4");
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MATCH_PLATFORM_INSN(CPU_MIPS3, "mips3");
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/* 32 bit ISAs */
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MATCH_PLATFORM_INSN(CPU_MIPS32R6, "mips32r6");
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MATCH_PLATFORM_INSN(CPU_MIPS32R5, "mips32r5");
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MATCH_PLATFORM_INSN(CPU_MIPS32R2, "mips32r2");
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MATCH_PLATFORM_INSN(CPU_MIPS32R1, "mips32");
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MATCH_PLATFORM_INSN(CPU_MIPS2, "mips2");
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/* Fallback */
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return "mips";
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}
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#undef MATCH_PLATFORM_INSN
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/* See linux kernel: arch/mips/kernel/process.c:elf_dump_regs. */
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void elf_core_copy_regs(target_elf_gregset_t *r, const CPUMIPSState *env)
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{
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for (int i = 1; i < ARRAY_SIZE(env->active_tc.gpr); i++) {
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r->pt.regs[i] = tswapl(env->active_tc.gpr[i]);
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}
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r->pt.regs[26] = 0;
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r->pt.regs[27] = 0;
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r->pt.lo = tswapl(env->active_tc.LO[0]);
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r->pt.hi = tswapl(env->active_tc.HI[0]);
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r->pt.cp0_epc = tswapl(env->active_tc.PC);
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r->pt.cp0_badvaddr = tswapl(env->CP0_BadVAddr);
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r->pt.cp0_status = tswapl(env->CP0_Status);
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r->pt.cp0_cause = tswapl(env->CP0_Cause);
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}
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