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69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
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* FPGA prototype platform
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*
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* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
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*
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*/
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#ifndef HW_XIANGSHAN_KMH_H
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#define HW_XIANGSHAN_KMH_H
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#include "hw/boards.h"
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#include "hw/riscv/riscv_hart.h"
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#define XIANGSHAN_KMH_MAX_CPUS 16
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typedef struct XiangshanKmhSoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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DeviceState *irqchip;
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MemoryRegion rom;
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} XiangshanKmhSoCState;
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#define TYPE_XIANGSHAN_KMH_SOC "xiangshan.kunminghu.soc"
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DECLARE_INSTANCE_CHECKER(XiangshanKmhSoCState, XIANGSHAN_KMH_SOC,
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TYPE_XIANGSHAN_KMH_SOC)
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typedef struct XiangshanKmhState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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XiangshanKmhSoCState soc;
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} XiangshanKmhState;
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#define TYPE_XIANGSHAN_KMH_MACHINE MACHINE_TYPE_NAME("xiangshan-kunminghu")
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DECLARE_INSTANCE_CHECKER(XiangshanKmhState, XIANGSHAN_KMH_MACHINE,
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TYPE_XIANGSHAN_KMH_MACHINE)
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enum {
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XIANGSHAN_KMH_ROM,
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XIANGSHAN_KMH_UART0,
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XIANGSHAN_KMH_CLINT,
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XIANGSHAN_KMH_APLIC_M,
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XIANGSHAN_KMH_APLIC_S,
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XIANGSHAN_KMH_IMSIC_M,
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XIANGSHAN_KMH_IMSIC_S,
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XIANGSHAN_KMH_DRAM,
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};
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enum {
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XIANGSHAN_KMH_UART0_IRQ = 10,
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};
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/* Indicating Timebase-freq (1MHZ) */
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#define XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ 1000000
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#define XIANGSHAN_KMH_IMSIC_NUM_IDS 255
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#define XIANGSHAN_KMH_IMSIC_NUM_GUESTS 7
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#define XIANGSHAN_KMH_IMSIC_GUEST_BITS 3
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#define XIANGSHAN_KMH_APLIC_NUM_SOURCES 96
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#endif
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