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578c6e9ed5
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register High(0x184)" and "Receive Ring Base Address Register High(0x18C)" to save the high part physical address of descriptor manager. Ex: TX descriptor manager address [34:0] The "Normal Priority Transmit Ring Base Address Register High(0x17C)" bits [2:0] which corresponds the bits [34:32] of the 64 bits address of the TX ring buffer address. The "Normal Priority Transmit Ring Base Address Register(0x20)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the TX ring buffer address. Introduce a new sub region which size is 0x100 for the set of new registers and map it at 0x100 in the container region. This sub region range is from 0x100 to 0x1ff. Introduce a new property and object attribute to activate the region for new registers. Introduce a new memop handlers for the new register read and write. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> |
5 months ago | |
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| .. | ||
| allwinner-sun8i-emac.h | 3 years ago | |
| allwinner_emac.h | 4 years ago | |
| cadence_gem.h | 4 years ago | |
| dp8393x.h | 1 year ago | |
| ftgmac100.h | 5 months ago | |
| imx_fec.h | 2 years ago | |
| lan9118.h | 10 months ago | |
| lance.h | 4 years ago | |
| lasi_82596.h | 10 months ago | |
| mii.h | 1 year ago | |
| msf2-emac.h | 4 years ago | |
| mv88w8618_eth.h | 3 years ago | |
| ne2000-isa.h | 10 months ago | |
| npcm7xx_emc.h | 2 years ago | |
| npcm_gmac.h | 10 months ago | |
| smc91c111.h | 10 months ago | |
| xlnx-versal-canfd.h | 2 years ago | |
| xlnx-zynqmp-can.h | 2 years ago | |