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83 lines
2.9 KiB
C
83 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch 7A1000 I/O interrupt controller definitions
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* Copyright (c) 2024 Loongson Technology Corporation Limited
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*/
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#ifndef HW_LOONGARCH_PIC_COMMON_H
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#define HW_LOONGARCH_PIC_COMMON_H
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#include "hw/pci-host/ls7a.h"
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#include "hw/sysbus.h"
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#define PCH_PIC_INT_ID_VAL 0x7000000UL
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#define PCH_PIC_INT_ID_VER 0x1UL
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#define PCH_PIC_INT_ID_LO 0x00
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#define PCH_PIC_INT_ID_HI 0x04
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#define PCH_PIC_INT_MASK_LO 0x20
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#define PCH_PIC_INT_MASK_HI 0x24
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#define PCH_PIC_HTMSI_EN_LO 0x40
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#define PCH_PIC_HTMSI_EN_HI 0x44
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#define PCH_PIC_INT_EDGE_LO 0x60
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#define PCH_PIC_INT_EDGE_HI 0x64
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#define PCH_PIC_INT_CLEAR_LO 0x80
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#define PCH_PIC_INT_CLEAR_HI 0x84
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#define PCH_PIC_AUTO_CTRL0_LO 0xc0
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#define PCH_PIC_AUTO_CTRL0_HI 0xc4
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#define PCH_PIC_AUTO_CTRL1_LO 0xe0
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#define PCH_PIC_AUTO_CTRL1_HI 0xe4
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#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100
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#define PCH_PIC_ROUTE_ENTRY_END 0x13f
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#define PCH_PIC_HTMSI_VEC_OFFSET 0x200
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#define PCH_PIC_HTMSI_VEC_END 0x23f
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#define PCH_PIC_INT_STATUS_LO 0x3a0
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#define PCH_PIC_INT_STATUS_HI 0x3a4
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#define PCH_PIC_INT_POL_LO 0x3e0
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#define PCH_PIC_INT_POL_HI 0x3e4
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#define STATUS_LO_START 0
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#define STATUS_HI_START 0x4
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#define POL_LO_START 0x40
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#define POL_HI_START 0x44
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#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
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OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
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LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
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struct LoongArchPICCommonState {
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SysBusDevice parent_obj;
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qemu_irq parent_irq[64];
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uint64_t int_mask; /* 0x020 interrupt mask register */
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uint64_t htmsi_en; /* 0x040 1=msi */
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uint64_t intedge; /* 0x060 edge=1 level=0 */
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uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
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uint64_t auto_crtl0; /* 0x0c0 */
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uint64_t auto_crtl1; /* 0x0e0 */
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uint64_t last_intirr; /* edge detection */
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uint64_t intirr; /* 0x380 interrupt request register */
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uint64_t intisr; /* 0x3a0 interrupt service register */
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/*
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* 0x3e0 interrupt level polarity selection
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* register 0 for high level trigger
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*/
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uint64_t int_polarity;
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uint8_t route_entry[64]; /* 0x100 - 0x138 */
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uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
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MemoryRegion iomem32_low;
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MemoryRegion iomem32_high;
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MemoryRegion iomem8;
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unsigned int irq_num;
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};
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struct LoongArchPICCommonClass {
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SysBusDeviceClass parent_class;
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DeviceRealize parent_realize;
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int (*pre_save)(LoongArchPICCommonState *s);
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int (*post_load)(LoongArchPICCommonState *s, int version_id);
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};
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#endif /* HW_LOONGARCH_PIC_COMMON_H */
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