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101 lines
3.7 KiB
C
101 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch 3A5000 ext interrupt controller definitions
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* Copyright (C) 2024 Loongson Technology Corporation Limited
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*/
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#ifndef LOONGARCH_EXTIOI_COMMON_H
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#define LOONGARCH_EXTIOI_COMMON_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "hw/loongarch/virt.h"
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#define LS3A_INTC_IP 8
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#define EXTIOI_IRQS (256)
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#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
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/* irq from EXTIOI is routed to no more than 4 cpus */
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#define EXTIOI_CPUS (4)
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/* map to ipnum per 32 irqs */
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#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
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#define EXTIOI_IRQS_COREMAP_SIZE 256
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#define EXTIOI_IRQS_NODETYPE_COUNT 16
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#define EXTIOI_IRQS_GROUP_COUNT 8
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#define APIC_OFFSET 0x400
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#define APIC_BASE (0x1000ULL + APIC_OFFSET)
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#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
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#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
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#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
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#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
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#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
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#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
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#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
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#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
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#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
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#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
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#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
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#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
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#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
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#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
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#define EXTIOI_SIZE 0x800
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#define EXTIOI_VIRT_BASE (0x40000000)
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#define EXTIOI_VIRT_SIZE (0x1000)
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#define EXTIOI_VIRT_FEATURES (0x0)
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#define EXTIOI_HAS_VIRT_EXTENSION (0)
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#define EXTIOI_HAS_ENABLE_OPTION (1)
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#define EXTIOI_HAS_INT_ENCODE (2)
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#define EXTIOI_HAS_CPU_ENCODE (3)
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#define EXTIOI_VIRT_HAS_FEATURES (BIT(EXTIOI_HAS_VIRT_EXTENSION) \
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| BIT(EXTIOI_HAS_ENABLE_OPTION) \
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| BIT(EXTIOI_HAS_CPU_ENCODE))
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#define EXTIOI_VIRT_CONFIG (0x4)
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#define EXTIOI_ENABLE (1)
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#define EXTIOI_ENABLE_INT_ENCODE (2)
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#define EXTIOI_ENABLE_CPU_ENCODE (3)
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#define EXTIOI_VIRT_COREMAP_START (0x40)
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#define EXTIOI_VIRT_COREMAP_END (0x240)
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#define TYPE_LOONGARCH_EXTIOI_COMMON "loongarch_extioi_common"
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OBJECT_DECLARE_TYPE(LoongArchExtIOICommonState,
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LoongArchExtIOICommonClass, LOONGARCH_EXTIOI_COMMON)
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typedef struct ExtIOICore {
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uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
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DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
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qemu_irq parent_irq[LS3A_INTC_IP];
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uint64_t arch_id;
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CPUState *cpu;
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} ExtIOICore;
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struct LoongArchExtIOICommonState {
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SysBusDevice parent_obj;
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uint32_t num_cpu;
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uint32_t features;
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uint32_t status;
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/* hardware state */
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uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
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uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
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uint32_t isr[EXTIOI_IRQS / 32];
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uint32_t enable[EXTIOI_IRQS / 32];
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uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
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uint32_t coremap[EXTIOI_IRQS / 4];
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uint32_t sw_pending[EXTIOI_IRQS / 32];
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uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
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uint8_t sw_coremap[EXTIOI_IRQS];
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qemu_irq irq[EXTIOI_IRQS];
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ExtIOICore *cpu;
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MemoryRegion extioi_system_mem;
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MemoryRegion virt_extend;
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};
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struct LoongArchExtIOICommonClass {
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SysBusDeviceClass parent_class;
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DeviceRealize parent_realize;
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int (*pre_save)(void *s);
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int (*post_load)(void *s, int version_id);
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};
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#endif /* LOONGARCH_EXTIOI_H */
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