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3dbab141d5
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" registers to save the high part physical address of Tx/Rx buffer address for master mode. It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers to save the high part physical address of Tx/Rx buffer address for slave mode. Ex: Tx buffer address for master mode [39:0] The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" bits [7:0] which corresponds the bits [39:32] of the 64 bits address of the Tx buffer address. The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the Tx buffer address. Introduce a new has_dma64 class attribute and new registers for the new mode to support DMA 64 bits dram address. Update new mode register number to 28. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> |
4 months ago | |
|---|---|---|
| .. | ||
| allwinner-i2c.h | ||
| arm_sbcon_i2c.h | ||
| aspeed_i2c.h | 4 months ago | |
| bcm2835_i2c.h | 11 months ago | |
| bitbang_i2c.h | ||
| i2c.h | ||
| i2c_mux_pca954x.h | ||
| imx_i2c.h | ||
| microbit_i2c.h | ||
| npcm7xx_smbus.h | ||
| pm_smbus.h | ||
| pmbus_device.h | 1 year ago | |
| pnv_i2c_regs.h | 11 months ago | |
| ppc4xx_i2c.h | ||
| smbus_eeprom.h | ||
| smbus_master.h | ||
| smbus_slave.h | ||