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133 lines
4.1 KiB
C
133 lines
4.1 KiB
C
/*
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* Nuvoton NPCM8xx SoC family.
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*
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* Copyright 2022 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM8XX_H
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#define NPCM8XX_H
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#include "hw/adc/npcm7xx_adc.h"
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#include "hw/core/split-irq.h"
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#include "hw/cpu/cluster.h"
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#include "hw/gpio/npcm7xx_gpio.h"
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#include "hw/i2c/npcm7xx_smbus.h"
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#include "hw/intc/arm_gic_common.h"
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#include "hw/mem/npcm7xx_mc.h"
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#include "hw/misc/npcm_clk.h"
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#include "hw/misc/npcm_gcr.h"
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#include "hw/misc/npcm7xx_mft.h"
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#include "hw/misc/npcm7xx_pwm.h"
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#include "hw/misc/npcm7xx_rng.h"
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#include "hw/net/npcm_gmac.h"
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#include "hw/net/npcm_pcs.h"
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#include "hw/nvram/npcm7xx_otp.h"
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#include "hw/sd/npcm7xx_sdhci.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "hw/ssi/npcm7xx_fiu.h"
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#include "hw/usb/hcd-ehci.h"
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#include "hw/usb/hcd-ohci.h"
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#include "target/arm/cpu.h"
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#include "hw/ssi/npcm_pspi.h"
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#define NPCM8XX_MAX_NUM_CPUS (4)
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/* The first half of the address space is reserved for DDR4 DRAM. */
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#define NPCM8XX_DRAM_BA (0x00000000)
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#define NPCM8XX_DRAM_SZ (2 * GiB)
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/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
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#define NPCM8XX_LOADER_START (0x00000000) /* Start of SDRAM */
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#define NPCM8XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */
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#define NPCM8XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */
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#define NPCM8XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
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#define NPCM8XX_NR_PWM_MODULES 3
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struct NPCM8xxMachine {
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MachineState parent_obj;
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/*
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* PWM fan splitter. each splitter connects to one PWM output and
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* multiple MFT inputs.
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*/
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SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES *
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NPCM7XX_PWM_PER_MODULE];
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};
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struct NPCM8xxMachineClass {
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MachineClass parent_class;
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const char *soc_type;
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};
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#define TYPE_NPCM8XX_MACHINE MACHINE_TYPE_NAME("npcm8xx")
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OBJECT_DECLARE_TYPE(NPCM8xxMachine, NPCM8xxMachineClass, NPCM8XX_MACHINE)
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struct NPCM8xxState {
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DeviceState parent_obj;
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ARMCPU cpu[NPCM8XX_MAX_NUM_CPUS];
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CPUClusterState cpu_cluster;
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GICState gic;
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MemoryRegion sram;
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MemoryRegion irom;
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MemoryRegion ram3;
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MemoryRegion *dram;
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NPCMGCRState gcr;
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NPCMCLKState clk;
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NPCM7xxTimerCtrlState tim[3];
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NPCM7xxADCState adc;
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NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES];
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NPCM7xxMFTState mft[8];
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NPCM7xxOTPState fuse_array;
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NPCM7xxMCState mc;
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NPCM7xxRNGState rng;
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NPCM7xxGPIOState gpio[8];
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NPCM7xxSMBusState smbus[27];
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EHCISysBusState ehci[2];
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OHCISysBusState ohci[2];
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NPCM7xxFIUState fiu[3];
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NPCMGMACState gmac[4];
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NPCMPCSState pcs;
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NPCM7xxSDHCIState mmc;
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NPCMPSPIState pspi;
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};
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struct NPCM8xxClass {
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DeviceClass parent_class;
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/* Bitmask of modules that are permanently disabled on this chip. */
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uint32_t disabled_modules;
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/* Number of CPU cores enabled in this SoC class. */
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uint32_t num_cpus;
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};
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#define TYPE_NPCM8XX "npcm8xx"
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OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8XX)
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/**
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* npcm8xx_load_kernel - Loads memory with everything needed to boot
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* @machine - The machine containing the SoC to be booted.
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* @soc - The SoC containing the CPU to be booted.
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*
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* This will set up the ARM boot info structure for the specific NPCM8xx
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* derivative and call arm_load_kernel() to set up loading of the kernel, etc.
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* into memory, if requested by the user.
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*/
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void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc);
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#endif /* NPCM8XX_H */
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