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84 lines
2.6 KiB
C
84 lines
2.6 KiB
C
/*
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* common defines for all CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_DEFS_H
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#define CPU_DEFS_H
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#ifndef COMPILING_PER_TARGET
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#error cpu.h included from common code
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#endif
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#include "qemu/host-utils.h"
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#include "qemu/thread.h"
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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#include "exec/memattrs.h"
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#include "hw/core/cpu.h"
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#include "cpu-param.h"
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#ifndef TARGET_LONG_BITS
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# error TARGET_LONG_BITS must be defined in cpu-param.h
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#endif
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#ifndef TARGET_PHYS_ADDR_SPACE_BITS
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# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
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#endif
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#ifndef TARGET_VIRT_ADDR_SPACE_BITS
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# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
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#endif
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#ifndef TARGET_PAGE_BITS
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# ifdef TARGET_PAGE_BITS_VARY
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# ifndef TARGET_PAGE_BITS_MIN
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# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
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# endif
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# else
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# error TARGET_PAGE_BITS must be defined in cpu-param.h
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# endif
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#endif
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#include "exec/target_long.h"
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#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
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#define CPU_TLB_DYN_MIN_BITS 6
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#define CPU_TLB_DYN_DEFAULT_BITS 8
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# if HOST_LONG_BITS == 32
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/* Make sure we do not require a double-word shift for the TLB load */
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# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
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# else /* HOST_LONG_BITS == 64 */
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/*
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* Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
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* 2**34 == 16G of address space. This is roughly what one would expect a
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* TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
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* Skylake's Level-2 STLB has 16 1G entries.
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* Also, make sure we do not size the TLB past the guest's address space.
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*/
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# ifdef TARGET_PAGE_BITS_VARY
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# define CPU_TLB_DYN_MAX_BITS \
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MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# else
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# define CPU_TLB_DYN_MAX_BITS \
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MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# endif
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# endif
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#endif /* CONFIG_SOFTMMU && CONFIG_TCG */
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#endif
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