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314 lines
10 KiB
C
314 lines
10 KiB
C
/*
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* RX62N Microcontroller
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*
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* Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
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* (Rev.1.40 R01UH0033EJ0140)
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*
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* Copyright (c) 2019 Yoshinori Sato
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* Copyright (c) 2020 Philippe Mathieu-Daudé
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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#include "hw/rx/rx62n.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/sysemu.h"
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#include "qapi/qmp/qlist.h"
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#include "qom/object.h"
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/*
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* RX62N Internal Memory
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*/
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#define RX62N_IRAM_BASE 0x00000000
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#define RX62N_DFLASH_BASE 0x00100000
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#define RX62N_CFLASH_BASE 0xfff80000
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/*
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* RX62N Peripheral Address
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* See users manual section 5
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*/
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#define RX62N_ICU_BASE 0x00087000
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#define RX62N_TMR_BASE 0x00088200
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#define RX62N_CMT_BASE 0x00088000
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#define RX62N_SCI_BASE 0x00088240
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/*
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* RX62N Peripheral IRQ
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* See users manual section 11
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*/
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#define RX62N_TMR_IRQ 174
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#define RX62N_CMT_IRQ 28
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#define RX62N_SCI_IRQ 214
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#define RX62N_XTAL_MIN_HZ (8 * 1000 * 1000)
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#define RX62N_XTAL_MAX_HZ (14 * 1000 * 1000)
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#define RX62N_PCLK_MAX_HZ (50 * 1000 * 1000)
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struct RX62NClass {
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/*< private >*/
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DeviceClass parent_class;
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/*< public >*/
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const char *name;
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uint64_t ram_size;
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uint64_t rom_flash_size;
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uint64_t data_flash_size;
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};
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typedef struct RX62NClass RX62NClass;
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DECLARE_CLASS_CHECKERS(RX62NClass, RX62N_MCU,
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TYPE_RX62N_MCU)
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/*
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* IRQ -> IPR mapping table
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* 0x00 - 0x91: IPR no (IPR00 to IPR91)
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* 0xff: IPR not assigned
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* See "11.3.1 Interrupt Vector Table" in hardware manual.
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*/
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static const uint8_t ipr_table[NR_IRQS] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */
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0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02,
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0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */
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0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */
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0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
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0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */
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0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */
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0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
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0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */
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0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59,
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0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */
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0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f,
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0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */
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0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66,
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0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */
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0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b,
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0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71,
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0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80,
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0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */
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0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff,
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0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */
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0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89,
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0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */
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};
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/*
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* Level triggered IRQ list
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* Not listed IRQ is Edge trigger.
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* See "11.3.1 Interrupt Vector Table" in hardware manual.
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*/
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static const uint8_t levelirq[] = {
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16, 21, 32, 44, 47, 48, 51, 64, 65, 66,
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67, 68, 69, 70, 71, 72, 73, 74, 75, 76,
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77, 78, 79, 90, 91, 170, 171, 172, 173, 214,
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217, 218, 221, 222, 225, 226, 229, 234, 237, 238,
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241, 246, 249, 250, 253,
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};
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static void register_icu(RX62NState *s)
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{
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int i;
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SysBusDevice *icu;
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QList *ipr_map, *trigger_level;
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object_initialize_child(OBJECT(s), "icu", &s->icu, TYPE_RX_ICU);
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icu = SYS_BUS_DEVICE(&s->icu);
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ipr_map = qlist_new();
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for (i = 0; i < NR_IRQS; i++) {
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qlist_append_int(ipr_map, ipr_table[i]);
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}
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qdev_prop_set_array(DEVICE(icu), "ipr-map", ipr_map);
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trigger_level = qlist_new();
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for (i = 0; i < ARRAY_SIZE(levelirq); i++) {
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qlist_append_int(trigger_level, levelirq[i]);
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}
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qdev_prop_set_array(DEVICE(icu), "trigger-level", trigger_level);
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sysbus_realize(icu, &error_abort);
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sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ));
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sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FIR));
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sysbus_connect_irq(icu, 2, qdev_get_gpio_in(DEVICE(&s->icu), SWI));
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sysbus_mmio_map(icu, 0, RX62N_ICU_BASE);
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}
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static void register_tmr(RX62NState *s, int unit)
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{
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SysBusDevice *tmr;
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int i, irqbase;
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object_initialize_child(OBJECT(s), "tmr[*]",
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&s->tmr[unit], TYPE_RENESAS_TMR);
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tmr = SYS_BUS_DEVICE(&s->tmr[unit]);
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qdev_prop_set_uint64(DEVICE(tmr), "input-freq", s->pclk_freq_hz);
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sysbus_realize(tmr, &error_abort);
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irqbase = RX62N_TMR_IRQ + TMR_NR_IRQ * unit;
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for (i = 0; i < TMR_NR_IRQ; i++) {
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sysbus_connect_irq(tmr, i,
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qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i));
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}
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sysbus_mmio_map(tmr, 0, RX62N_TMR_BASE + unit * 0x10);
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}
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static void register_cmt(RX62NState *s, int unit)
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{
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SysBusDevice *cmt;
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int i, irqbase;
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object_initialize_child(OBJECT(s), "cmt[*]",
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&s->cmt[unit], TYPE_RENESAS_CMT);
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cmt = SYS_BUS_DEVICE(&s->cmt[unit]);
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qdev_prop_set_uint64(DEVICE(cmt), "input-freq", s->pclk_freq_hz);
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sysbus_realize(cmt, &error_abort);
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irqbase = RX62N_CMT_IRQ + CMT_NR_IRQ * unit;
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for (i = 0; i < CMT_NR_IRQ; i++) {
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sysbus_connect_irq(cmt, i,
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qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i));
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}
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sysbus_mmio_map(cmt, 0, RX62N_CMT_BASE + unit * 0x10);
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}
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static void register_sci(RX62NState *s, int unit)
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{
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SysBusDevice *sci;
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int i, irqbase;
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object_initialize_child(OBJECT(s), "sci[*]",
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&s->sci[unit], TYPE_RENESAS_SCI);
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sci = SYS_BUS_DEVICE(&s->sci[unit]);
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qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit));
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qdev_prop_set_uint64(DEVICE(sci), "input-freq", s->pclk_freq_hz);
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sysbus_realize(sci, &error_abort);
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irqbase = RX62N_SCI_IRQ + SCI_NR_IRQ * unit;
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for (i = 0; i < SCI_NR_IRQ; i++) {
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sysbus_connect_irq(sci, i,
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qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i));
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}
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sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08);
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}
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static void rx62n_realize(DeviceState *dev, Error **errp)
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{
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RX62NState *s = RX62N_MCU(dev);
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RX62NClass *rxc = RX62N_MCU_GET_CLASS(dev);
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if (s->xtal_freq_hz == 0) {
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error_setg(errp, "\"xtal-frequency-hz\" property must be provided.");
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return;
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}
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/* XTAL range: 8-14 MHz */
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if (s->xtal_freq_hz < RX62N_XTAL_MIN_HZ
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|| s->xtal_freq_hz > RX62N_XTAL_MAX_HZ) {
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error_setg(errp, "\"xtal-frequency-hz\" property in incorrect range.");
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return;
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}
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/* Use a 4x fixed multiplier */
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s->pclk_freq_hz = 4 * s->xtal_freq_hz;
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/* PCLK range: 8-50 MHz */
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assert(s->pclk_freq_hz <= RX62N_PCLK_MAX_HZ);
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memory_region_init_ram(&s->iram, OBJECT(dev), "iram",
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rxc->ram_size, &error_abort);
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memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram);
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memory_region_init_rom(&s->d_flash, OBJECT(dev), "flash-data",
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rxc->data_flash_size, &error_abort);
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memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash);
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memory_region_init_rom(&s->c_flash, OBJECT(dev), "flash-code",
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rxc->rom_flash_size, &error_abort);
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memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash);
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/* Initialize CPU */
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object_initialize_child(OBJECT(s), "cpu", &s->cpu, TYPE_RX62N_CPU);
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qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
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register_icu(s);
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s->cpu.env.ack = qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0);
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register_tmr(s, 0);
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register_tmr(s, 1);
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register_cmt(s, 0);
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register_cmt(s, 1);
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register_sci(s, 0);
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}
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static Property rx62n_properties[] = {
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DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false),
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DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void rx62n_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = rx62n_realize;
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device_class_set_props(dc, rx62n_properties);
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}
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static void r5f562n7_class_init(ObjectClass *oc, void *data)
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{
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RX62NClass *rxc = RX62N_MCU_CLASS(oc);
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rxc->ram_size = 64 * KiB;
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rxc->rom_flash_size = 384 * KiB;
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rxc->data_flash_size = 32 * KiB;
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};
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static void r5f562n8_class_init(ObjectClass *oc, void *data)
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{
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RX62NClass *rxc = RX62N_MCU_CLASS(oc);
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rxc->ram_size = 96 * KiB;
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rxc->rom_flash_size = 512 * KiB;
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rxc->data_flash_size = 32 * KiB;
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};
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static const TypeInfo rx62n_types[] = {
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{
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.name = TYPE_R5F562N7_MCU,
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.parent = TYPE_RX62N_MCU,
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.class_init = r5f562n7_class_init,
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}, {
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.name = TYPE_R5F562N8_MCU,
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.parent = TYPE_RX62N_MCU,
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.class_init = r5f562n8_class_init,
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}, {
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.name = TYPE_RX62N_MCU,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(RX62NState),
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.class_size = sizeof(RX62NClass),
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.class_init = rx62n_class_init,
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.abstract = true,
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}
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};
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DEFINE_TYPES(rx62n_types)
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