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1054 lines
28 KiB
C
1054 lines
28 KiB
C
/*
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* QEMU PowerPC 440 embedded processors emulation
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/ppc/ppc4xx.h"
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#include "hw/pci-host/ppc4xx.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci/pci.h"
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#include "sysemu/reset.h"
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#include "cpu.h"
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#include "ppc440.h"
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/*****************************************************************************/
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/* L2 Cache as SRAM */
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/* FIXME:fix names */
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enum {
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DCR_L2CACHE_BASE = 0x30,
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DCR_L2CACHE_CFG = DCR_L2CACHE_BASE,
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DCR_L2CACHE_CMD,
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DCR_L2CACHE_ADDR,
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DCR_L2CACHE_DATA,
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DCR_L2CACHE_STAT,
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DCR_L2CACHE_CVER,
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DCR_L2CACHE_SNP0,
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DCR_L2CACHE_SNP1,
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DCR_L2CACHE_END = DCR_L2CACHE_SNP1,
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};
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/* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
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enum {
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DCR_ISRAM0_BASE = 0x20,
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DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE,
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DCR_ISRAM0_SB1CR,
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DCR_ISRAM0_SB2CR,
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DCR_ISRAM0_SB3CR,
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DCR_ISRAM0_BEAR,
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DCR_ISRAM0_BESR0,
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DCR_ISRAM0_BESR1,
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DCR_ISRAM0_PMEG,
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DCR_ISRAM0_CID,
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DCR_ISRAM0_REVID,
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DCR_ISRAM0_DPC,
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DCR_ISRAM0_END = DCR_ISRAM0_DPC
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};
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enum {
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DCR_ISRAM1_BASE = 0xb0,
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DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE,
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/* single bank */
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DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04,
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DCR_ISRAM1_BESR0,
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DCR_ISRAM1_BESR1,
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DCR_ISRAM1_PMEG,
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DCR_ISRAM1_CID,
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DCR_ISRAM1_REVID,
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DCR_ISRAM1_DPC,
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DCR_ISRAM1_END = DCR_ISRAM1_DPC
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};
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typedef struct ppc4xx_l2sram_t {
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MemoryRegion bank[4];
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uint32_t l2cache[8];
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uint32_t isram0[11];
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} ppc4xx_l2sram_t;
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static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
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{
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ppc4xx_l2sram_t *l2sram = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case DCR_L2CACHE_CFG:
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case DCR_L2CACHE_CMD:
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case DCR_L2CACHE_ADDR:
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case DCR_L2CACHE_DATA:
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case DCR_L2CACHE_STAT:
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case DCR_L2CACHE_CVER:
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case DCR_L2CACHE_SNP0:
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case DCR_L2CACHE_SNP1:
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ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE];
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break;
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case DCR_ISRAM0_SB0CR:
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case DCR_ISRAM0_SB1CR:
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case DCR_ISRAM0_SB2CR:
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case DCR_ISRAM0_SB3CR:
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case DCR_ISRAM0_BEAR:
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case DCR_ISRAM0_BESR0:
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case DCR_ISRAM0_BESR1:
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case DCR_ISRAM0_PMEG:
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case DCR_ISRAM0_CID:
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case DCR_ISRAM0_REVID:
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case DCR_ISRAM0_DPC:
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ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
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break;
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default:
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break;
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}
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return ret;
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}
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static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val)
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{
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/*ppc4xx_l2sram_t *l2sram = opaque;*/
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/* FIXME: Actually handle L2 cache mapping */
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switch (dcrn) {
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case DCR_L2CACHE_CFG:
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case DCR_L2CACHE_CMD:
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case DCR_L2CACHE_ADDR:
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case DCR_L2CACHE_DATA:
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case DCR_L2CACHE_STAT:
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case DCR_L2CACHE_CVER:
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case DCR_L2CACHE_SNP0:
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case DCR_L2CACHE_SNP1:
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/*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
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break;
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case DCR_ISRAM0_SB0CR:
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case DCR_ISRAM0_SB1CR:
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case DCR_ISRAM0_SB2CR:
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case DCR_ISRAM0_SB3CR:
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case DCR_ISRAM0_BEAR:
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case DCR_ISRAM0_BESR0:
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case DCR_ISRAM0_BESR1:
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case DCR_ISRAM0_PMEG:
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case DCR_ISRAM0_CID:
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case DCR_ISRAM0_REVID:
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case DCR_ISRAM0_DPC:
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/*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
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break;
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case DCR_ISRAM1_SB0CR:
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case DCR_ISRAM1_BEAR:
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case DCR_ISRAM1_BESR0:
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case DCR_ISRAM1_BESR1:
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case DCR_ISRAM1_PMEG:
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case DCR_ISRAM1_CID:
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case DCR_ISRAM1_REVID:
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case DCR_ISRAM1_DPC:
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/*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
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break;
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}
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}
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static void l2sram_reset(void *opaque)
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{
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ppc4xx_l2sram_t *l2sram = opaque;
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memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache));
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l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000;
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memset(l2sram->isram0, 0, sizeof(l2sram->isram0));
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}
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void ppc4xx_l2sram_init(CPUPPCState *env)
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{
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ppc4xx_l2sram_t *l2sram;
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l2sram = g_malloc0(sizeof(*l2sram));
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/* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
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memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
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64 * KiB, &error_abort);
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memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
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64 * KiB, &error_abort);
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memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
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64 * KiB, &error_abort);
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memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
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64 * KiB, &error_abort);
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qemu_register_reset(&l2sram_reset, l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_CFG,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_CMD,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_ADDR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_DATA,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_STAT,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_CVER,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_SNP0,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_SNP1,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB0CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB1CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB2CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB3CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_PMEG,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_DPC,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM1_SB0CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM1_PMEG,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM1_DPC,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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}
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/*****************************************************************************/
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/* Clocking Power on Reset */
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enum {
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CPR0_CFGADDR = 0xC,
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CPR0_CFGDATA = 0xD,
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CPR0_PLLD = 0x060,
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CPR0_PLBED = 0x080,
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CPR0_OPBD = 0x0C0,
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CPR0_PERD = 0x0E0,
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CPR0_AHBD = 0x100,
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};
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typedef struct ppc4xx_cpr_t {
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uint32_t addr;
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} ppc4xx_cpr_t;
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static uint32_t dcr_read_cpr(void *opaque, int dcrn)
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{
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ppc4xx_cpr_t *cpr = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case CPR0_CFGADDR:
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ret = cpr->addr;
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break;
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case CPR0_CFGDATA:
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switch (cpr->addr) {
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case CPR0_PLLD:
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ret = (0xb5 << 24) | (1 << 16) | (9 << 8);
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break;
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case CPR0_PLBED:
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ret = (5 << 24);
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break;
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case CPR0_OPBD:
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ret = (2 << 24);
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break;
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case CPR0_PERD:
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case CPR0_AHBD:
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ret = (1 << 24);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
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{
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ppc4xx_cpr_t *cpr = opaque;
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switch (dcrn) {
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case CPR0_CFGADDR:
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cpr->addr = val;
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break;
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case CPR0_CFGDATA:
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break;
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default:
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break;
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}
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}
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static void ppc4xx_cpr_reset(void *opaque)
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{
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ppc4xx_cpr_t *cpr = opaque;
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cpr->addr = 0;
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}
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void ppc4xx_cpr_init(CPUPPCState *env)
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{
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ppc4xx_cpr_t *cpr;
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cpr = g_malloc0(sizeof(*cpr));
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ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
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ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
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qemu_register_reset(ppc4xx_cpr_reset, cpr);
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}
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/*****************************************************************************/
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/* System DCRs */
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typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
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struct ppc4xx_sdr_t {
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uint32_t addr;
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};
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enum {
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SDR0_CFGADDR = 0x00e,
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SDR0_CFGDATA,
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SDR0_STRP0 = 0x020,
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SDR0_STRP1,
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SDR0_102 = 0x66,
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SDR0_103,
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SDR0_128 = 0x80,
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SDR0_ECID3 = 0x083,
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SDR0_DDR0 = 0x0e1,
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SDR0_USB0 = 0x320,
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};
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enum {
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PESDR0_LOOP = 0x303,
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PESDR0_RCSSET,
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PESDR0_RCSSTS,
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PESDR0_RSTSTA = 0x310,
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PESDR1_LOOP = 0x343,
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PESDR1_RCSSET,
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PESDR1_RCSSTS,
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PESDR1_RSTSTA = 0x365,
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};
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static uint32_t dcr_read_sdr(void *opaque, int dcrn)
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{
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ppc4xx_sdr_t *sdr = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case SDR0_CFGADDR:
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ret = sdr->addr;
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break;
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case SDR0_CFGDATA:
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switch (sdr->addr) {
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case SDR0_STRP0:
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ret = (0xb5 << 8) | (1 << 4) | 9;
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break;
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case SDR0_STRP1:
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ret = (5 << 29) | (2 << 26) | (1 << 24);
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break;
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case SDR0_ECID3:
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ret = 1 << 20; /* No Security/Kasumi support */
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break;
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case SDR0_DDR0:
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ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
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break;
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case PESDR0_RCSSET:
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case PESDR1_RCSSET:
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ret = (1 << 24) | (1 << 16);
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break;
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case PESDR0_RCSSTS:
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case PESDR1_RCSSTS:
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ret = (1 << 16) | (1 << 12);
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break;
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case PESDR0_RSTSTA:
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case PESDR1_RSTSTA:
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ret = 1;
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break;
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case PESDR0_LOOP:
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case PESDR1_LOOP:
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ret = 1 << 12;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
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{
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ppc4xx_sdr_t *sdr = opaque;
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switch (dcrn) {
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case SDR0_CFGADDR:
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sdr->addr = val;
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break;
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case SDR0_CFGDATA:
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switch (sdr->addr) {
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case 0x00: /* B0CR */
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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|
|
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static void sdr_reset(void *opaque)
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{
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ppc4xx_sdr_t *sdr = opaque;
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sdr->addr = 0;
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}
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|
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void ppc4xx_sdr_init(CPUPPCState *env)
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{
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ppc4xx_sdr_t *sdr;
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sdr = g_malloc0(sizeof(*sdr));
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qemu_register_reset(&sdr_reset, sdr);
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ppc_dcr_register(env, SDR0_CFGADDR,
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sdr, &dcr_read_sdr, &dcr_write_sdr);
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ppc_dcr_register(env, SDR0_CFGDATA,
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sdr, &dcr_read_sdr, &dcr_write_sdr);
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ppc_dcr_register(env, SDR0_102,
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sdr, &dcr_read_sdr, &dcr_write_sdr);
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ppc_dcr_register(env, SDR0_103,
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sdr, &dcr_read_sdr, &dcr_write_sdr);
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ppc_dcr_register(env, SDR0_128,
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sdr, &dcr_read_sdr, &dcr_write_sdr);
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ppc_dcr_register(env, SDR0_USB0,
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sdr, &dcr_read_sdr, &dcr_write_sdr);
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}
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|
|
/*****************************************************************************/
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/* PLB to AHB bridge */
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enum {
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AHB_TOP = 0xA4,
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AHB_BOT = 0xA5,
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};
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|
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typedef struct ppc4xx_ahb_t {
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uint32_t top;
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uint32_t bot;
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} ppc4xx_ahb_t;
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|
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static uint32_t dcr_read_ahb(void *opaque, int dcrn)
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{
|
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ppc4xx_ahb_t *ahb = opaque;
|
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uint32_t ret = 0;
|
|
|
|
switch (dcrn) {
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case AHB_TOP:
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ret = ahb->top;
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break;
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case AHB_BOT:
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ret = ahb->bot;
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break;
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default:
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break;
|
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}
|
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|
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return ret;
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}
|
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|
|
static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
ppc4xx_ahb_t *ahb = opaque;
|
|
|
|
switch (dcrn) {
|
|
case AHB_TOP:
|
|
ahb->top = val;
|
|
break;
|
|
case AHB_BOT:
|
|
ahb->bot = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_ahb_reset(void *opaque)
|
|
{
|
|
ppc4xx_ahb_t *ahb = opaque;
|
|
|
|
/* No error */
|
|
ahb->top = 0;
|
|
ahb->bot = 0;
|
|
}
|
|
|
|
void ppc4xx_ahb_init(CPUPPCState *env)
|
|
{
|
|
ppc4xx_ahb_t *ahb;
|
|
|
|
ahb = g_malloc0(sizeof(*ahb));
|
|
ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb);
|
|
ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb);
|
|
qemu_register_reset(ppc4xx_ahb_reset, ahb);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* DMA controller */
|
|
|
|
#define DMA0_CR_CE (1 << 31)
|
|
#define DMA0_CR_PW (1 << 26 | 1 << 25)
|
|
#define DMA0_CR_DAI (1 << 24)
|
|
#define DMA0_CR_SAI (1 << 23)
|
|
#define DMA0_CR_DEC (1 << 2)
|
|
|
|
enum {
|
|
DMA0_CR = 0x00,
|
|
DMA0_CT,
|
|
DMA0_SAH,
|
|
DMA0_SAL,
|
|
DMA0_DAH,
|
|
DMA0_DAL,
|
|
DMA0_SGH,
|
|
DMA0_SGL,
|
|
|
|
DMA0_SR = 0x20,
|
|
DMA0_SGC = 0x23,
|
|
DMA0_SLP = 0x25,
|
|
DMA0_POL = 0x26,
|
|
};
|
|
|
|
typedef struct {
|
|
uint32_t cr;
|
|
uint32_t ct;
|
|
uint64_t sa;
|
|
uint64_t da;
|
|
uint64_t sg;
|
|
} PPC4xxDmaChnl;
|
|
|
|
typedef struct {
|
|
int base;
|
|
PPC4xxDmaChnl ch[4];
|
|
uint32_t sr;
|
|
} PPC4xxDmaState;
|
|
|
|
static uint32_t dcr_read_dma(void *opaque, int dcrn)
|
|
{
|
|
PPC4xxDmaState *dma = opaque;
|
|
uint32_t val = 0;
|
|
int addr = dcrn - dma->base;
|
|
int chnl = addr / 8;
|
|
|
|
switch (addr) {
|
|
case 0x00 ... 0x1f:
|
|
switch (addr % 8) {
|
|
case DMA0_CR:
|
|
val = dma->ch[chnl].cr;
|
|
break;
|
|
case DMA0_CT:
|
|
val = dma->ch[chnl].ct;
|
|
break;
|
|
case DMA0_SAH:
|
|
val = dma->ch[chnl].sa >> 32;
|
|
break;
|
|
case DMA0_SAL:
|
|
val = dma->ch[chnl].sa;
|
|
break;
|
|
case DMA0_DAH:
|
|
val = dma->ch[chnl].da >> 32;
|
|
break;
|
|
case DMA0_DAL:
|
|
val = dma->ch[chnl].da;
|
|
break;
|
|
case DMA0_SGH:
|
|
val = dma->ch[chnl].sg >> 32;
|
|
break;
|
|
case DMA0_SGL:
|
|
val = dma->ch[chnl].sg;
|
|
break;
|
|
}
|
|
break;
|
|
case DMA0_SR:
|
|
val = dma->sr;
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
|
|
__func__, dcrn, chnl, addr);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
PPC4xxDmaState *dma = opaque;
|
|
int addr = dcrn - dma->base;
|
|
int chnl = addr / 8;
|
|
|
|
switch (addr) {
|
|
case 0x00 ... 0x1f:
|
|
switch (addr % 8) {
|
|
case DMA0_CR:
|
|
dma->ch[chnl].cr = val;
|
|
if (val & DMA0_CR_CE) {
|
|
int count = dma->ch[chnl].ct & 0xffff;
|
|
|
|
if (count) {
|
|
int width, i, sidx, didx;
|
|
uint8_t *rptr, *wptr;
|
|
hwaddr rlen, wlen;
|
|
hwaddr xferlen;
|
|
|
|
sidx = didx = 0;
|
|
width = 1 << ((val & DMA0_CR_PW) >> 25);
|
|
xferlen = count * width;
|
|
wlen = rlen = xferlen;
|
|
rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen,
|
|
false);
|
|
wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen,
|
|
true);
|
|
if (rptr && rlen == xferlen && wptr && wlen == xferlen) {
|
|
if (!(val & DMA0_CR_DEC) &&
|
|
val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
|
|
/* optimise common case */
|
|
memmove(wptr, rptr, count * width);
|
|
sidx = didx = count * width;
|
|
} else {
|
|
/* do it the slow way */
|
|
for (sidx = didx = i = 0; i < count; i++) {
|
|
uint64_t v = ldn_le_p(rptr + sidx, width);
|
|
stn_le_p(wptr + didx, width, v);
|
|
if (val & DMA0_CR_SAI) {
|
|
sidx += width;
|
|
}
|
|
if (val & DMA0_CR_DAI) {
|
|
didx += width;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (wptr) {
|
|
cpu_physical_memory_unmap(wptr, wlen, 1, didx);
|
|
}
|
|
if (rptr) {
|
|
cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case DMA0_CT:
|
|
dma->ch[chnl].ct = val;
|
|
break;
|
|
case DMA0_SAH:
|
|
dma->ch[chnl].sa &= 0xffffffffULL;
|
|
dma->ch[chnl].sa |= (uint64_t)val << 32;
|
|
break;
|
|
case DMA0_SAL:
|
|
dma->ch[chnl].sa &= 0xffffffff00000000ULL;
|
|
dma->ch[chnl].sa |= val;
|
|
break;
|
|
case DMA0_DAH:
|
|
dma->ch[chnl].da &= 0xffffffffULL;
|
|
dma->ch[chnl].da |= (uint64_t)val << 32;
|
|
break;
|
|
case DMA0_DAL:
|
|
dma->ch[chnl].da &= 0xffffffff00000000ULL;
|
|
dma->ch[chnl].da |= val;
|
|
break;
|
|
case DMA0_SGH:
|
|
dma->ch[chnl].sg &= 0xffffffffULL;
|
|
dma->ch[chnl].sg |= (uint64_t)val << 32;
|
|
break;
|
|
case DMA0_SGL:
|
|
dma->ch[chnl].sg &= 0xffffffff00000000ULL;
|
|
dma->ch[chnl].sg |= val;
|
|
break;
|
|
}
|
|
break;
|
|
case DMA0_SR:
|
|
dma->sr &= ~val;
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
|
|
__func__, dcrn, chnl, addr);
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_dma_reset(void *opaque)
|
|
{
|
|
PPC4xxDmaState *dma = opaque;
|
|
int dma_base = dma->base;
|
|
|
|
memset(dma, 0, sizeof(*dma));
|
|
dma->base = dma_base;
|
|
}
|
|
|
|
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
|
|
{
|
|
PPC4xxDmaState *dma;
|
|
int i;
|
|
|
|
dma = g_malloc0(sizeof(*dma));
|
|
dma->base = dcr_base;
|
|
qemu_register_reset(&ppc4xx_dma_reset, dma);
|
|
for (i = 0; i < 4; i++) {
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
}
|
|
ppc_dcr_register(env, dcr_base + DMA0_SR,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + DMA0_SGC,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + DMA0_SLP,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + DMA0_POL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* PCI Express controller */
|
|
/*
|
|
* FIXME: This is not complete and does not work, only implemented partially
|
|
* to allow firmware and guests to find an empty bus. Cards should use PCI.
|
|
*/
|
|
#include "hw/pci/pcie_host.h"
|
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
|
|
|
|
struct PPC460EXPCIEState {
|
|
PCIExpressHost parent_obj;
|
|
|
|
MemoryRegion busmem;
|
|
MemoryRegion iomem;
|
|
qemu_irq irq[4];
|
|
int32_t num;
|
|
int32_t dcrn_base;
|
|
PowerPCCPU *cpu;
|
|
|
|
uint64_t cfg_base;
|
|
uint32_t cfg_mask;
|
|
uint64_t msg_base;
|
|
uint32_t msg_mask;
|
|
uint64_t omr1_base;
|
|
uint64_t omr1_mask;
|
|
uint64_t omr2_base;
|
|
uint64_t omr2_mask;
|
|
uint64_t omr3_base;
|
|
uint64_t omr3_mask;
|
|
uint64_t reg_base;
|
|
uint32_t reg_mask;
|
|
uint32_t special;
|
|
uint32_t cfg;
|
|
};
|
|
|
|
enum {
|
|
PEGPL_CFGBAH = 0x0,
|
|
PEGPL_CFGBAL,
|
|
PEGPL_CFGMSK,
|
|
PEGPL_MSGBAH,
|
|
PEGPL_MSGBAL,
|
|
PEGPL_MSGMSK,
|
|
PEGPL_OMR1BAH,
|
|
PEGPL_OMR1BAL,
|
|
PEGPL_OMR1MSKH,
|
|
PEGPL_OMR1MSKL,
|
|
PEGPL_OMR2BAH,
|
|
PEGPL_OMR2BAL,
|
|
PEGPL_OMR2MSKH,
|
|
PEGPL_OMR2MSKL,
|
|
PEGPL_OMR3BAH,
|
|
PEGPL_OMR3BAL,
|
|
PEGPL_OMR3MSKH,
|
|
PEGPL_OMR3MSKL,
|
|
PEGPL_REGBAH,
|
|
PEGPL_REGBAL,
|
|
PEGPL_REGMSK,
|
|
PEGPL_SPECIAL,
|
|
PEGPL_CFG,
|
|
};
|
|
|
|
static uint32_t dcr_read_pcie(void *opaque, int dcrn)
|
|
{
|
|
PPC460EXPCIEState *s = opaque;
|
|
uint32_t ret = 0;
|
|
|
|
switch (dcrn - s->dcrn_base) {
|
|
case PEGPL_CFGBAH:
|
|
ret = s->cfg_base >> 32;
|
|
break;
|
|
case PEGPL_CFGBAL:
|
|
ret = s->cfg_base;
|
|
break;
|
|
case PEGPL_CFGMSK:
|
|
ret = s->cfg_mask;
|
|
break;
|
|
case PEGPL_MSGBAH:
|
|
ret = s->msg_base >> 32;
|
|
break;
|
|
case PEGPL_MSGBAL:
|
|
ret = s->msg_base;
|
|
break;
|
|
case PEGPL_MSGMSK:
|
|
ret = s->msg_mask;
|
|
break;
|
|
case PEGPL_OMR1BAH:
|
|
ret = s->omr1_base >> 32;
|
|
break;
|
|
case PEGPL_OMR1BAL:
|
|
ret = s->omr1_base;
|
|
break;
|
|
case PEGPL_OMR1MSKH:
|
|
ret = s->omr1_mask >> 32;
|
|
break;
|
|
case PEGPL_OMR1MSKL:
|
|
ret = s->omr1_mask;
|
|
break;
|
|
case PEGPL_OMR2BAH:
|
|
ret = s->omr2_base >> 32;
|
|
break;
|
|
case PEGPL_OMR2BAL:
|
|
ret = s->omr2_base;
|
|
break;
|
|
case PEGPL_OMR2MSKH:
|
|
ret = s->omr2_mask >> 32;
|
|
break;
|
|
case PEGPL_OMR2MSKL:
|
|
ret = s->omr3_mask;
|
|
break;
|
|
case PEGPL_OMR3BAH:
|
|
ret = s->omr3_base >> 32;
|
|
break;
|
|
case PEGPL_OMR3BAL:
|
|
ret = s->omr3_base;
|
|
break;
|
|
case PEGPL_OMR3MSKH:
|
|
ret = s->omr3_mask >> 32;
|
|
break;
|
|
case PEGPL_OMR3MSKL:
|
|
ret = s->omr3_mask;
|
|
break;
|
|
case PEGPL_REGBAH:
|
|
ret = s->reg_base >> 32;
|
|
break;
|
|
case PEGPL_REGBAL:
|
|
ret = s->reg_base;
|
|
break;
|
|
case PEGPL_REGMSK:
|
|
ret = s->reg_mask;
|
|
break;
|
|
case PEGPL_SPECIAL:
|
|
ret = s->special;
|
|
break;
|
|
case PEGPL_CFG:
|
|
ret = s->cfg;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
PPC460EXPCIEState *s = opaque;
|
|
uint64_t size;
|
|
|
|
switch (dcrn - s->dcrn_base) {
|
|
case PEGPL_CFGBAH:
|
|
s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_CFGBAL:
|
|
s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_CFGMSK:
|
|
s->cfg_mask = val;
|
|
size = ~(val & 0xfffffffe) + 1;
|
|
/*
|
|
* Firmware sets this register to E0000001. Why we are not sure,
|
|
* but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
|
|
* ignored.
|
|
*/
|
|
if (size > PCIE_MMCFG_SIZE_MAX) {
|
|
size = PCIE_MMCFG_SIZE_MAX;
|
|
}
|
|
pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size);
|
|
break;
|
|
case PEGPL_MSGBAH:
|
|
s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_MSGBAL:
|
|
s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_MSGMSK:
|
|
s->msg_mask = val;
|
|
break;
|
|
case PEGPL_OMR1BAH:
|
|
s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR1BAL:
|
|
s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR1MSKH:
|
|
s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR1MSKL:
|
|
s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR2BAH:
|
|
s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR2BAL:
|
|
s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR2MSKH:
|
|
s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR2MSKL:
|
|
s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR3BAH:
|
|
s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR3BAL:
|
|
s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR3MSKH:
|
|
s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR3MSKL:
|
|
s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_REGBAH:
|
|
s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_REGBAL:
|
|
s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_REGMSK:
|
|
s->reg_mask = val;
|
|
/* FIXME: how is size encoded? */
|
|
size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1);
|
|
break;
|
|
case PEGPL_SPECIAL:
|
|
s->special = val;
|
|
break;
|
|
case PEGPL_CFG:
|
|
s->cfg = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc460ex_set_irq(void *opaque, int irq_num, int level)
|
|
{
|
|
PPC460EXPCIEState *s = opaque;
|
|
qemu_set_irq(s->irq[irq_num], level);
|
|
}
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|
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#define PPC440_PCIE_DCR(s, dcrn) \
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ppc_dcr_register(&(s)->cpu->env, (s)->dcrn_base + (dcrn), (s), \
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&dcr_read_pcie, &dcr_write_pcie)
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|
|
|
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static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s)
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|
{
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PPC440_PCIE_DCR(s, PEGPL_CFGBAH);
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PPC440_PCIE_DCR(s, PEGPL_CFGBAL);
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PPC440_PCIE_DCR(s, PEGPL_CFGMSK);
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PPC440_PCIE_DCR(s, PEGPL_MSGBAH);
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PPC440_PCIE_DCR(s, PEGPL_MSGBAL);
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PPC440_PCIE_DCR(s, PEGPL_MSGMSK);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR1BAH);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR1BAL);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR1MSKH);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR1MSKL);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR2BAH);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR2BAL);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR2MSKH);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR2MSKL);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR3BAH);
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|
PPC440_PCIE_DCR(s, PEGPL_OMR3BAL);
|
|
PPC440_PCIE_DCR(s, PEGPL_OMR3MSKH);
|
|
PPC440_PCIE_DCR(s, PEGPL_OMR3MSKL);
|
|
PPC440_PCIE_DCR(s, PEGPL_REGBAH);
|
|
PPC440_PCIE_DCR(s, PEGPL_REGBAL);
|
|
PPC440_PCIE_DCR(s, PEGPL_REGMSK);
|
|
PPC440_PCIE_DCR(s, PEGPL_SPECIAL);
|
|
PPC440_PCIE_DCR(s, PEGPL_CFG);
|
|
}
|
|
|
|
static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev);
|
|
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
|
|
int i;
|
|
char buf[20];
|
|
|
|
if (!s->cpu) {
|
|
error_setg(errp, "cpu link property must be set");
|
|
return;
|
|
}
|
|
if (s->num < 0 || s->dcrn_base < 0) {
|
|
error_setg(errp, "busnum and dcrn-base properties must be set");
|
|
return;
|
|
}
|
|
snprintf(buf, sizeof(buf), "pcie%d-mem", s->num);
|
|
memory_region_init(&s->busmem, OBJECT(s), buf, UINT64_MAX);
|
|
snprintf(buf, sizeof(buf), "pcie%d-io", s->num);
|
|
memory_region_init(&s->iomem, OBJECT(s), buf, 64 * KiB);
|
|
for (i = 0; i < 4; i++) {
|
|
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
|
|
}
|
|
snprintf(buf, sizeof(buf), "pcie.%d", s->num);
|
|
pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq,
|
|
pci_swizzle_map_irq_fn, s, &s->busmem,
|
|
&s->iomem, 0, 4, TYPE_PCIE_BUS);
|
|
ppc460ex_pcie_register_dcrs(s);
|
|
}
|
|
|
|
static Property ppc460ex_pcie_props[] = {
|
|
DEFINE_PROP_INT32("busnum", PPC460EXPCIEState, num, -1),
|
|
DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
|
|
DEFINE_PROP_LINK("cpu", PPC460EXPCIEState, cpu, TYPE_POWERPC_CPU,
|
|
PowerPCCPU *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->realize = ppc460ex_pcie_realize;
|
|
device_class_set_props(dc, ppc460ex_pcie_props);
|
|
dc->hotpluggable = false;
|
|
}
|
|
|
|
static const TypeInfo ppc460ex_pcie_host_info = {
|
|
.name = TYPE_PPC460EX_PCIE_HOST,
|
|
.parent = TYPE_PCIE_HOST_BRIDGE,
|
|
.instance_size = sizeof(PPC460EXPCIEState),
|
|
.class_init = ppc460ex_pcie_class_init,
|
|
};
|
|
|
|
static void ppc460ex_pcie_register(void)
|
|
{
|
|
type_register_static(&ppc460ex_pcie_host_info);
|
|
}
|
|
|
|
type_init(ppc460ex_pcie_register)
|